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Design, simulation, and investigation of basic logic gates by using NAND logic
gate

Conference Paper in AIP Conference Proceedings · March 2023

DOI: 10.1063/5.0119320

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 Design, Simulation, and Investigation of Basic Logic Gates
by Using NAND Logic Gate
Wael Saad Ahmed1, a), Nabeel Abdulrazaq yaseen2, b) and Nsaif Jasim
AlChaabawi2, c)

1
Tikrit University, Tikrit Medical College, Iraq.
2
University of Misan, College of Engineering, Department of Petroleum, Iraq.

a)
Corresponding author: wael.alrawi@tu.edu.iq
b)
nabil@uomisan.edu.iq
c)
nsf_jsm@uomisan.edu.iq

Abstract. The NAND logic gate is one of the universal logic gates. We can use it to design and build a digital logic gate
like (not, and, or) gates. This paper gives Design, Simulation, and Investigation of Basic gates by utilizing NAND Gate
with perfect output logic standards with preserving similar performance for all digital logic in this design, we can use it
easily to create very large-scale integration (VLSI)designing. In our simulation has been tested on the hspice program at 32
nm CMOS technology. The results show this design has low lower dissipation and delay when compared with other designs.
When compared to some of these designs, the findings reveal that the intended gate is typically quicker, shorter, and with
much less energy dissipation, and there's a boom in pace and electricity dissipation for the reason that processing era
improves 32nm. In addition, the recommended 4T became proven to be quicker than others. In evaluation to the standard
CMOS NAND gate, which employs a few transistors, the recommended layout has furnished a sparkling new shape for
developing a enter NAND gate making use of simply 4 transistors. The suggested design gate can predict the creation of
devices with significantly improved speed, energy consumption, and computationally efficiency.

Keywords: NAND, CMOS, Hspice, Power Dissipation, Delay.

INTRODUCTION
The logic NAND gate is one gate of the universal gates can be utilized to building a lot of very-large-scale
integration similar not, and, or, xor. Improving the presentation of the NAND gate can lead to an improved
performance system (VLSI) [4]. The plan of our gate is will be submitting a major improvement with power
consumption and delay. Many digital gates have been planned and developed to reduce energy consumption and reduce
delays, and these have become the basics in digital design [1]. Pass-transistor logic is a popular and frequently used
alternative to complementary CMOS. By enabling the primary inputs to drive gate terminals, pass-transistor logic tries
to reduce the number of transistors required to realize the logic [7-10-11]. This paper suggests four transistors NAND
gate with 32nm technology CMOS which minimizes the threshold loss a big problem in old designs, also improves
power deposition. This paper proves that using four transistors (NAND) can build any gate or VLSI. This paper
includes the following section 2the standard design of basic gate former work reviewed. Section 3 proposed the design
of four transistor NAND gate. section 4 the simulation result and dissection. a comparison will be made standard
design with the proposed design. in the last section consolation.
 THE STANDARD DESGIN OF THE BASIC GATE FORMER WORD REVIEWED
In the last decades and present the longest MOSFET transistor channels were measured in the micro-unit, but in
modern integrated circuits the of MOSFET transistor channels was reduced to the nanoscale and as a result of this
small size MOSFET transistor counter for modern circuits increased when the length of MOSFET transistor channel
was reduced, high integration and high performance were achieved [2.3].in this section will review the construction
of basic gate like

Construction of Inverter Gate (Not)

It is one of the basic gates in electronic circuits, as it is also called the inverter gate, as the standard design contains
only two transistors as shown in Fig 1.

FIGURE 1. Not circuit

It is part of the basic gates in electronic circuits as it is also called the inverted gate as the standard design contains
only two transistors as shown in the figure, as the circuit contains one input and one output. the work of the inverter is
to reverse the signal input if the entry 0 exit will be one vice versa as shown in Fig, 2 and Table 1.

FIGURE 2. input – output waveforms for NOT gate

 TABEL 1. input-output NOT gate
Input Output
0 1
1 0
Construction of AND Gate
The AND gate is one of all the fundamental gates within the world of electronic circuits [7]. just like the inverted
gate. the gate in mathematics represents the multiplication process, therefore the output gate affects the input gate.
The gate has one output, either the input has two or more as need or the circuit design. the logical equation for the
function is Q=A.B where Q the output, A and B are the input, as is that the subject of the Table 2 and Fig 3.

FIGURE 3. AND gate cricuit

TABLE 2. input – output AND gate

A B Output
0 0 0
0 1 0
1 0 0
1 1 1
Construction of OR Gate
This gate is one in every of the fundamental logic gates that are employed in electronic circuits, output this gate
depend upon the input because the signaling one indicates the input inevitably contains one this gate may be described
by the mathematical (+) the gate is with this function A+B=Q because the Table 3 below is shown however will this
logic work and a figure representing OR gate [5].

TABLE 3. input – output OR gate

A B Output
0 0 0
0 1 1
1 0 1
1 1 1
PROPOSED FOUR TRANSISTOR NAND GATE USING 32N TECHNOLOGY
In – Fig. 4. the gate NAND is shown to us, it contains four transistors containing type PMOS two and kinds NMOS
two as each transistor takes specific voltage in keeping with the technology used. the signaling depends on the input
value during this case we've got two input the primary first (A) and second (B) so when the worth of (AB)= 00 so main
the behavior of the NAND circuit is as follows: Q3 and Q4 are off and Q1 and Q2 are on it main they exist is 1 if the
input (A, B) =01 then (Q2, Q3) =off then (Q1, Q4) thereon means output gate =1. if the (A, B) =10 then (Q4, Q1) =off
then (Q2, Q3) thereon means output gate =1. if the (A, B) =11 then (Q1, Q2) =off (Q4, Q3) thereon means output gate
=0. this process to the Table 4.

(a) (b)
FIGURE 4. (a) NAND circuit (b) symbol NAND circuit

TABLE 4. input – output NAND gate

A B Output
0 0 1
0 1 1
1 0 1
1 1 0

SIMULATION RESULT AND INESTIGATION LOGIC GATE FOR BUILDING

UNIVERSAL GATE

Construction NOT Logic Gate Based on NAND Gate

The NAND-based induction of the NOT door has appeared in Fig. 5. Moreover, it's miles vital to notice that the
inputs gate doorways are related together. the NAND-based setup was determined, the two conceivable inputs, zero
and one, were tried, and the comes about were watched. Hence, from the comes about, able to conclude that
embedding's the same input through a 2-input NAND door will result within the complement of the input; consistent
invalidation is executed which concurs to the fact chart appeared in Fig. 2. If we tend to see the output to the gate of
the figure (5) in Fig. 6. we'll see on output clone of the work of NOT gate.
 FIGURE 5. NOT gate using NAND gate

FIGURE 6. input-output waveforms NOT gate

Construction AND Gate Based on NAND Gate

If we might wish to vogue associate) AND gate) utilizing (NAND Gate), we'll like a pair of gates from the NAND
circuit like in Fig. 7. the first contains a pair of entries as a outcome of the preliminary exit is that the doorway to the
second logic gate, that might work like NOT logic gate, as a outcome of the exit of the last or second logic gate is sort
of just like the operate of the AND gate as shown among the Table 2.in Fig. 8. we'll output AND gate vogue by a pair
of gates of NAND.

FIGURE 7. AND logic gate

 FIGURE 8. input-output waveforms AND gate

Construction OR Gate Based on NAND Gate

If we might prefer to vogue the gate using a gate. then we'll need three gates from the gate like in Fig. 6. the first
and second gate goes to be work like not gate and thus the third -gate as gate the output of the third -gate square
measure attending to be output gate goes to be similar because the perform of the gate as shown among the Table 3.in
Fig. 10. we'll the output of gate vogue by three gates of NAND.
 FIGURE 9. OR logic gate

FIGURE 10. input-output waveform

TABEL 7. Effects of simulation of proposed designs in comparison to current designs

Design Delay Power PDP
Proposed AND 10.19n 18.474n 188.20
2-input AND [7] 86.45n 340n 29393
2-input AND [8] 15.6n 10020n 156312
Proposed OR 20.0642n 14.0048n 280.84
2-input OR [9] 78.77n 330n 25994
2-input OR [9] 10.5n 20400n 214200
CONCLUSION
The proposed design has presented a brand-new structure for designing a two-input NAND gate using only four
transistors as compared to the standard CMOS NAND gate which uses some transistors. The proposed gate was
simulated at 32nm process technologies for performance evaluation. The effects acquired have proven that the
deliberate gate is typically faster, smaller, and with much less strength dissipation while placed subsequent too few of
those structures, and there is a development in velocity and strength dissipation due to the fact the method generation
improves 32nm.Also, the proposed 4T changed into determined to be higher than others in velocity. the proposed
layout gate can verify the improvement of gadgets that can offer a whole lot better overall performance in velocity,
strength consumption, and computational efficiency.
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