Name:Shikhar Barthwal Roll No:2001178

Experiment -2 Design of NAND Gate using CMOS

Objective

To study NAND gate & validate the truth table

Theory
For the design of any circuit with the CMOS technology; We need parallel or series connections
of NMOS and PMOS with a NMOS source tied directly or indirectly to ground and a PMOS
source tied directly or indirectly to Vdd. A basic CMOS structure of any 2-input logic gate can be
drawn as follows: MOS NOR gate circuit uses four MOSFETs just likethe NAND gate, except
that its transistors are differently arranged.
Instead of two paralleled sourcing (upper) transistors connected to Vddand two series-
connected sinking (lower) transistors connected to ground, the NOR gate uses two series-
connected sourcing transistorsand two parallel-connected sinking transistors

Circuit Diagram
Result and Observations

A B A NAND B

0 0 1

0 1 1

1 0 1

1 1 0

Conclusion

From the above observations, we conclude that we successfully created NAND circuit with
CMOS technology And verified results with truth tables..