1120 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO.

12, DECEMBER 2007

Quantization Effects in All-Digital

Phase-Locked Loops
Paolo Madoglio, Student Member, IEEE, Marco Zanuso, Student Member, IEEE,
Salvatore Levantino, Member, IEEE, Carlo Samori, Member, IEEE, and Andrea L. Lacaita, Senior Member, IEEE

Abstract—This brief analyzes the impact of the quantization

noise sources in all-digital phase-locked loops (ADPLLs), recently
employed as frequency synthesizers. In general, the in-band
phase noise is not only caused by the phase quantization of the
time-to-digital converter, but also by the frequency quantization
of the digitally controlled oscillator (DCO). The delta–sigma mod-
ulator placed at the DCO input refines the frequency quantization
and adds another source of in-band PLL noise. Interestingly, the
higher the modulator order, the higher this source of in-band
phase noise. A method for the estimation of all the quantization
noise contributors is provided, which is proven by mixed-mode
simulations.

(16)
Index Terms—All-digital phase-locked loops (ADPLLs),
delta–sigma modulation, frequency synthesizers, jitter, Fig. 1. All-digital PLL for frequency synthesis [1].
phase noise, quantization, radio communication.

What has been neglected up to this point is the concurrent

I. INTRODUCTION
NE of the most recent and significant advancements in the
O area of RF integrated circuits is undoubtedly the adop-
tion of all-digital phase-locked loops (ADPLLs) as frequency
synthesizers for RF transceivers. This structure offers the re-
markable advantage of replacing the charge pump and the off-
chip loop filter with a digital filter [1], [2]. In the implementa-
tion in Fig. 1, taken from [1], the phase error and the oscillator
tuning control are quantized by employing a time-to-digital con-
verter (TDC) and a digitally controlled LC oscillator (DCO) [3],
respectively.
The key characteristic of any RF synthesizer is still the phase
noise, which in an ADPLL is mainly determined by quantiza-
tion operations performed within the loop. Previous works, such
as [4]–[6], treat the case in which the DCO is a digital clocked
system and the quantization at its input is the only one per-
formed in the PLL.
More recently, [7] highlights the role of the TDC resolution
in limiting the ADPLL in-band noise. In [3], the quantization at
the input of a free-running DCO is demonstrated to produce a
-shaped spectrum. This noise is high-pass-filtered when
the DCO is closed in the PLL and it provides negligible contri-
bution to the in-band noise.
Manuscript received June 21, 2007. This work was supported by the Com-
munications Circuits Laboratory, Intel Corporation, Hillsboro, OR. This paper
was recommended by Associate Editor G. Manganaro.
P. Madoglio, M. Zanuso, S. Levantino and C. Samori are with the Dipar-
timento di Elettronica e Informazione, Politecnico di Milano, Milan I-20133,
Italy (e-mail: samori@elet.polimi.it).
A. L. Lacaita is with the Dipartimento di Elettronica e Informazione, Politec-
nico di Milano, Milan I-20133, Italy, and also with IFN Sezione Milano, Milan
I-20133, Italy (e-mail: lacaita@elet.polimi.it).
Digital Object Identifier 10.1109/TCSII.2007.906171
1549-7747/$25.00 © 2007 IEEE
presence of the TDC and the DCO. The brief will demonstrate
that the sampling of the DCO phase operated by the TDC causes
folding of the DCO quantization noise. The net result is that the
DCO frequency quantization adds another white noise contrib-
utor to the ADPLL in-band noise.
To improve the DCO frequency granularity, a delta–sigma
modulator is often placed between the loop filter and the
DCO, as shown in Fig. 1. As it will be demonstrated, the effect
of the TDC on the quantization noise is equivalent to an
accumulate-and-dump decimation filter, which results again in
an in-band white noise contributor.
II. TDC QUANTIZATION NOISE
An equivalent model of the synthesizer in Fig. 1 is first de-
rived which will be useful in the following derivations.
The reference counting is measured by accumulating
the number FCW at rate , while the DCO
counting by accumulating ones at rate ,
i.e., by counting the DCO periods. In a type-II PLL, the counting
error calculated at rate is forced
to be zero by the feedback loop. This implies that
at steady state. The measurement of the time delay
between the reference and the DCO edges, performed by the ac-
cumulators and the adder only, has resolution equal to the DCO
period . Consequently, the minimum counting error
is 1. This coarse time quantization is refined by a TDC, which
gives a more accurate measurement of the delay between refer-
ence and DCO.
Fig. 2 shows the linear equivalent model of the ADPLL, [8].
The first accumulator is modeled by a discrete-time integrator.
The block in the feedback path has the additional scaling factor
, since its output is increased by the number of DCO
periods in , i.e., , at each reference cycle.
MADOGLIO et al.: QUANTIZATION EFFECTS IN ALL-DIGITAL PLLS 1121

If the finite frequency resolution of the DCO is modeled as

a random variable added to TW, with uniform distribution and
white spectrum, as in [3], the DCO frequency quantization pro-
duces a phase noise. This noise is filtered by a high-pass
transfer function with 40 dB slope within the band-
width of a type-II PLL. Therefore, the resulting slope of the
in-band phase noise spectrum would be 20 dB .
Unfortunately, this approach is oversimplified and it under-
estimates the output noise at low frequency offsets. In prac-
tice, the DCO quantization alters the effective resolution of the
TDC, i.e., the error in Fig. 2. To account for this behavior,
Fig. 2. Linear discrete-time model of the digital PLL in Fig. 1. we first observe that, for a proper choice of the loop filter, the
counting error is able to enforce the minimum change in
the DCO frequency. At first order, the relative period variation
The limited resolution of the TDC causes a counting error, of the DCO, say , is equal to .
which is represented in the model by an additive noise source Hence, the minimum accumulated delay after is equal to
. Since multiple quantization levels are spanned, we assume
that the quantization error has a uniform distribution and white
spectrum. Given the TDC time resolution, its variance (4)
is . The variance of the counting error is
, as a time delay produces a counting
Note that this accumulated time delay is a continuous-time
error of 1. The corresponding double-sided power-spectral den-
variable, sampled at the reference frequency by the TDC. If
sity (PSD) is
is larger than , the DCO causes time error variations
larger than the TDC resolution. Thus, the TDC works with less
(1) bits, as if it were a coarser converter. This phenomenon derives
from the subsampling of the DCO phase operated by the TDC.
Concerning the DCO, its frequency is equal to The longer the reference period, the larger the accumulated time
, with the free-running frequency delay of the DCO and the time quantization error.
and the minimum frequency step produced by the Since is the delay variation detected by the TDC after
variation of the tuning word (TW). Being the DCO frequency the minimum DCO frequency change, another source of error,
constant over , the DCO acts as a zero-order-hold dig- whose variance is , has to be added to the quantization
ital-to-analog converter. Thus, the transfer function from the error of the TDC. At first order, the two phenomena can be as-
discrete-time frequency to the continuous-time phase sumed to provide independent errors, so that the total time error
is . variance to be used in (2) is given by
From the model in Fig. 2, it is easy to demonstrate that the
transfer function from to the output phase is low-pass-
shaped and it is equal to within the bandwidth. As a result, (5)
the output in-band phase noise can be written as
The errors due to the TDC and to the DCO are equal when the
(2) DCO least-significant bit (LSB), , is

Making the substitution , we obtain the

same result given in [7] (6)

If the DCO LSB is larger than , (3) becomes

(3)

In the following section, we intend to demonstrate that the (7)

granularity of can degrade the in-band with re-
spect to the estimation in (3).
IV. MODULATION OF THE DCO TUNING INPUT
III. EFFECTS OF THE DCO FREQUENCY QUANTIZATION
The DCO resolution can be improved using a modulator,
The DCO can synthesize a discrete set of frequencies. In prac- as shown in Fig. 1 [1]. The bits representing the integer part of
tice, the PLL target frequency is never equal to any TW drive directly the DCO, whereas those representing the frac-
of these frequencies. Thus, varies between two or more tional part of TW drive a modulator, whose output controls
discrete frequencies and its mean value is equal to the target one. the DCO LSBs.
1122 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 12, DECEMBER 2007

TABLE I
16 QUANTIZATION NOISE POWER AFTER ACCUMULATE-AND-DUMP

Fig. 3. DCO period modulated by the 16 stream.

The modulator, which has a clock frequency higher than If the provided no quantization noise, the minimum vari-
, allows to change the average DCO frequency in steps ation of the sum in (11) would be OS times the minimum vari-
finer than . The average DCO frequency resolution ation of the input, i.e., , because of its limited input
becomes resolution. In reality, is also affected by the quanti-
zation noise. Let be the variance of the sum. Under the as-
sumption of independent stochastic processes, the total variance
(8) of the DCO-induced time delay is given by the sum of the two
variances
having denoted as the number of the modulator input bits.
Thus, the second term in (5) should be scaled by . (12)
However, the adds quantization noise. Following the
analysis in [3], this noise would only affect the out-of-band part
of the spectrum and would be negligible in the evaluation of the The variance of the sum of the output can be obtained
in-band noise. Again, this argument neglects the subsampling by multiplying first the spectrum of the quantization noise
operation of the TDC on the DCO phase noise. by the frequency response of the accumulate-and-dump
To evaluate the contribution of the -driven DCO to the operation [9], which is
in-band white noise, first note that the output
, where is an integer number, updates the DCO
frequency once every . The percentage
variation of the DCO frequency is . (13)
Consequently, the DCO period varies by The noise power is then given by integrating the spectrum
over the bandwidth

(9)
(14)
Referring to Fig. 3, the accumulated delay between ref-
erence and DCO after is , where where
, since is constant over . Thus,
the delay after is given by
(15)

(10)
is the spectrum of an -th order MASH modulator.
The integral in (14), which can be simplified as
Substituting (9) in (10) and defining as oversampling the ratio
, the accumulated time delay can be written (16)
as
has been calculated analytically for from 1 to 3. The results are
shown in Table I, together with the ranges of OS in which these
(11) results are valid. The oversampling ratio can be also written as

The main implication of (11) is that the time delay measured
by the TDC after depends on the decimated moving av-
erage of the modulator output. The average is performed
by the DCO, while the decimation at the rate by the TDC.
The whole operation is also known as accumulate-and-dump.
This operation entails an intrinsic undersampling from to
and, therefore, a folding of the noise spectrum.
(17)
Typically, FCW varies between 10 and 100, while . Thus,
the results in Table I are correct in any practical case.
Moreover, if OS is about 10 and the number of input
bits of the modulator is greater than, let us say, 10, the term
in (12) can be neglected. Therefore, the total time
MADOGLIO et al.: QUANTIZATION EFFECTS IN ALL-DIGITAL PLLS 1123

variance to be substituted in (2), which accounts for the quanti-

zation of both the TDC and the -driven DCO, becomes

(18)

This variance decreases at higher OS and, on the basis of the

values of in Table I, increases as the order of the mod-
ulator increases. Lowest quantization noise is achieved using a
first-order modulator. This result, surprising at first sight, can
be intuitively explained by recalling the noise folding inherent
in the accumulate-and-dump operation in (11). The same situa- Fig. 4. In-band PLL phase noise versus DCO LSB magnitude: simulation re-
tion happens in the first stage of the decimation sinc filter of a sults with no16 modulator (squares), with third-order 16 OS = 6 25
at :

analog-to-digital converter. As explained in [9], the order of OS = 12 5

(circles) and : (triangles), theoretical estimations (solid lines).

the sinc filter should be . In the ADPLL, the DCO/TDC

performs inherently a first-order average [see (11)], which is in- of wider-bandwidth modulations tends to increase the feasible
sufficient even for a first-order modulator. Thus, the noise . In the realization in [1], 6 bits are sufficient to span
performance using high-order modulators worsens. the 1-MHz Bluetooth channel. In higher-data-rate communica-
The comparison of (5) and (18) leads to the conclusion that tion standards with channel bandwidths in the order of 10 MHz,
the presence of the modulator lowers the variance of the the same number of bits would increase by one order
DCO quantization noise by a factor , independently of magnitude. DCOs with higher number of bits and intrinsi-
on the number of the modulator input bits. The value of OS cally monotonic characteristic may be not feasible. In fact, they
equating the two contributions in (18) is given by require large area and long routing, because of the need of ther-
mometer-coded capacitors, and achieve limited tuning range.
(19) VI. MIXED-MODE SIMULATIONS

In some cases, the value of OS given from (19) may not be A. Model
feasible, since OS is limited upwards by FCW (being ). A behavioral model of the system in Fig. 1 has been built
where all the blocks, except for the DCO, are described in
V. NUMERICAL EXAMPLE VHDL language. The DCO is implemented as an analog block
As an example, let us suppose a reference frequency of in Verilog-AMS language. The digital loop filter is an integrator
40 MHz, , thus, the target DCO frequency is with a stabilization zero, whose transfer function is
1 GHz. Moreover, we assume that the TDC resolution
is 10 ps.
The in-band output phase noise caused by the (20)
phase quantization of the TDC follows after (3) and it is
dBc Hz. The LSB which makes the contribu- No amplification has been added since a gain before the
tion of the DCO quantization equal to the TDC one is 400 kHz DCO is equivalent to increasing the DCO LSB to .
from (6). If is, for instance, 4 MHz, the in-band noise A time-domain mixed-mode simulator has been used to ex-
is entirely set by the DCO frequency granularity and tract the output phase spectrum. Since no noise source is in-
approximated by (7) is dBc Hz. cluded, the output phase noise is entirely caused by the quanti-
We assume now that a first-order modulator is employed zation phenomena. The spectrum of the DCO tuning word has
to drive the DCO. The oversampling ratio making the contri- been obtained by filtering with the Welch window and calcu-
bution of the TDC and the DCO equal is given from (19) and lating the FFT of samples of TW at 100-GHz sampling fre-
it is , which is lower than the maximum OS equal quency. The phase spectrum has been derived from the spec-
to . A value of OS equal to 12.5 is close to trum of TW, after multiplying by , according to
and, on the basis of (17), it makes the division factor be- the model in Fig. 2.
tween the DCO and the clock frequencies equal to 2, al-
lowing for an easy implementation of the -divider. The ex- B. Results
pected given from the combination of (2) and (18) is Having set the values of , FCW and as in the
about dBc Hz. numerical example in Section V, the PLL has been first simu-
Although LC-tuned DCOs with frequency step of tens of kilo- lated without a modulator. Simulations have been repeated
hertz has been reported [1], [3], the contribution of the DCO to varying from 10 kHz to 4 MHz. For each value of
the ADPLL in-band phase noise is expected to be relevant in , the parameter in (20) has been chosen which maxi-
practical cases for two main reasons. First, in order to take ad- mizes the loop bandwidth.
vantage of high-resolution TDCs, the minimum is ex- Fig. 4 shows the simulated in-band noise floor versus
pected to decrease. If becomes about 1 ps [10], as square dots and the theoretical curve predicted from the com-
reduces by one order of magnitude [see (6)]. Second, the need bination of (2) and (5) as solid line. The error bars associated to
1124 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 12, DECEMBER 2007
Fig. 5. Output phase spectrum of the ADPLL (with DCO LSB f 1 =4
16 modulator. Mixed-mode simulations (solid lines) and theoretical noise contributors (dashed lines).
the simulation results dots come from the numerical variance of
the FFT. Simulations and theory are in good agreement. For low
values, the noise floor is limited by the TDC resolution.
For kHz, the in-band noise versus
has dB slope, as predicted from (7).
The simulations have been repeated after the introduction
of a first-order modulator. The is 4 MHz. Fol-
lowing the numerical example in Section V, a convenient choice
of the oversampling ratio OS is 12.5. The resulting simulated
phase spectrum is shown in Fig. 5(a). The in-band noise floor
is dBc Hz, which is within 2 dB from the theoretical
value of dBc Hz.
Then, a PLL with a third-order MASH 1-1-1 modulator
has been simulated. The in-band noise floor is plotted in Fig. 4
as a function of the for two different values of the over-
sampling: (or ) and (or ) [1] R. B. Staszewski, C.-M. Hung, K. Maggio, J. Wallberg, D. Leipold,
as circles and triangles, respectively. The theoretical curves es-
timated by (2) and (18), and plotted as solid lines in Fig. 4 are
in fair agreement with the simulations.
Fig. 5(b) shows the simulated phase spectrum of the PLL with
MHz, third-order and . [3] R. B. Staszewsky, C. Hung, N. Barton, M. Lee, and D. Leipold, “A dig-
The graphs in Fig. 5 shows also the two dominant noise con-
tributions obtained from theory. The in-band quantization noise
is caused by the folded noise of the -driven DCO, as high-
lighted so far, and it is low-pass shaped by the loop. The out-of-
band dominant noise comes linearly from the modulator.
Its quantization noise is integrated by the DCO and then high-
pass-filtered by the type-II loop, as discussed in [3]. The fair
agreement between theoretical and simulated spectra is a fur-
ther validation of the mixed-mode simulation.
VII. CONCLUSION
This brief has quantitatively shown that the frequency granu-
larity of the DCO in an ADPLL does not only produce out-of-
band phase noise, as typically believed. It additionally
causes an increase in the in-band white noise. This phenomenon
is related to the concurrent presence of the TDC and the DCO
MHz and OS = 12 5: ), employing (a) a first-order and (b) a third-order MASH 1-1-1
quantization and it is caused by the under-sampling of the DCO
phase performed by the TDC. The same folding of the DCO
noise spectrum takes place even when a modulator drives
the DCO tuning word. The higher the modulator order and the
lower the oversampling ratio, the higher the ADPLL in-band
noise degradation.
ACKNOWLEDGMENT
The authors wish to thank the Associate Editor and the re-
viewers for their contributions, which improved the quality of
this brief.
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