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SERDES Transceiver for Supply-Induced Jitter Sensitivity Methodology Based

on PDN analysis

Conference Paper · October 2019

DOI: 10.1109/IMPACT47228.2019.9024989

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 SERDES TRANSCEIVER FOR SUPPLY-INDUCED JITTER SENSITIVITY
METHODOLOGY BASED ON PDN ANALYSIS
Michael Chang
88 Section 3, Zhongxing Road Xindian District, New Taipei City 231 Taiwan, R.O.C.
michael_chang@htc.com

Abstract II. DESIGN CHALLENGE FOR SERDES TRANSMITTER

Chip-package-printed circuit board co-design has been
attracting attention recently as a design methodology in
development. One of the most important elements is to present
detailed analysis of supply induced jitter sensitivity of Serdes
transceiver. General SERDES transmitter architecture is serial-
to-parallel converter and is sensitive to supply noise. The
SERDES transmitter has power domains that have different
influences in the jitter-sensitivity contribution of analog circuits.
The jitter sensitivity is dependent of each circuit block silicon
characterization and combined with Data/CLK path. It explains
the jitter sensitivity contribution of each analog block circuit and
provides a solution to its individual challenge. With jitter
sensitivity extraction of analog block circuit (PLL/Duty cycle
corrector/clock tree/parallel to serial/2to1/pre-driver/current
mode IO), it is possible to enable accurate jitter-aware target
impedance calculation. It gives the in-depth SI/PI insight into
analog design field and optimization/achieving on silicon success.
I. INTRODUCTION
Considering the scaled down supply voltages and the higher
data-rate speeds, one of the most challenging tasks for the
system requirement is to maintain the integrity of signal and
power in the deep-submicron technologies. General serdes
transmitter architecture is serial-to-parallel converter and is
sensitivity to the supply noise. The serdes transmitter has
separated power domains which have different influences in
the jitter-sensitivity contribution. The jitter sensitivity is
dependent of each block silicon characterization and combined
with data and clock path as figure 1. Due to the supply-
induced jitter sensitivity, the timing margins are affected and
there maybe violations in timing of the system.
For all these increasingly difficult competition, achieving
very low jitter requirement to meet the timing budget is one of
the most challenging tasks in multi-gigabit I/O interface
design. It is a common understanding that the dynamic range
of supply noise needs to be strictly defined because it directly
affects the circuit function for proper device operation and
therefore causes circuit performance degradation or even leads
to system malfunction.
A. PSIJ-CLK path : DCC & CLK tree buffer and its side
effect
Duty cycle corrector is commonly used to adjust the duty
cycle of clock signals from PLL, to improve the signal quality
of the clock signal and to ensure a ~50% duty cycle that
maintain the high speed signal performance as figure 2.
Merge core power and clock core power in Die-package bump
region that causes the very strict requirement of target
impedance because core power supply many blocks which is
power hungry such as transmitter logics and pre-drivers as
figure 3. However its supply-induced jitter sensitivity is
increased and the performance is affected.

Figure 2: Jitter-accumulation of Low Power Transmitter CLK path approach

Figure 1: Jitter-accumulation of SERDES Transmitter Data & CLK path

approach
Figure 3: Supply-induced jitter sensitivity plot of Low Power Transmitter
CLK path approach
B. PSIJ-Data path : Pre-driver & Current mode IO
For optimizing this jitter performance induced by supply
noise of data path, characterizing the jitter distribution
between different power domains is the key to resource
allocation of PDN design. The simulation shows that an
internal data path is consisting of voltage mode pre-driver, it is
sensitive to core power supply noise.
Figure 4: Supply-induced jitter sensitivity plot of Low Power Transmitter data
path approach
C. PSIJ-Design challenge for Receiver
Due to the complexity of common mode signal noise and
supply noise generated from non-linear power supply
noise/non-symmetry IO/packaging/PCB field, the effect
method is analyzed independently to investigate the common
and supply noise inside receiver as figure 5.
Figure 5: Supply-induced jitter sensitivity of front-end receiver data path
approach
D. PSIJ-Design challenge for PLL
For design cost, small area, large tuning range, multi-phase
clock generation and low power effectiveness, a ring VCO
based on PLL is first considered to use as figure 6. To
optimize a supply-induced noise performance of PLL design,
achieving very low jitter to meet the timing budget is one of
the most challenging tasks in multi-gigabit PLL design.
Figure 6: Low Power PLL clock path diagram
III. SOLUTION TO DESIGN CHALLENGE
A conventional approach to determining the jitter sensitivity
profile is to use transient simulation with circuit simulator. A
single-tone sinusoidal signal with small amplitude is injected
into the supply node as the stimulus. After the circuit
simulation stabilizes, the resulting jitter transient is recorded
by observing the output clock jitter measurement.
A. Solution to CLK path : Active & passive method
The regulator filters the high frequency noise form Vref power
and forces REG output to track VREF in low frequency and
filter high frequency noise. The jitter sensitivity of CLK core
power is reduced ~1 order above ~5MHz and the jitter
sensitivity of CLK path of VDDA supply increased 1 order
under ~1MHz as figure 7 and 8.
Figure 7: Bandgap as Vref or core power as Vref and On-chip regulator.
Figure 8: Jitter sensitivity of IO and Core power domain of clock path
Separate core power and clock core power in Die-package and
merge together under board-level BGA region. Specification
requirement is relaxed by ~2 order and likely to meet.
Separated layout skill is similar to on-chip regulator behavior
and without any additional power consumption of on-chip
regulator.
Figure 9: Separated coupling layout skill similar to on-chip regulator behavior

Figure 10: Voltage transfer curve between core power and clock core power.
B. Solution to Data path: Current frequency modulation skill
Current profile modulation skill is applied in analog skill to
analyze the improvement of target impedance of core power
domain PDN of data path. Specification requirement is relaxed
by 1~2 order as shown figure 11, 12 and 13.
Figure 11: Current modulation skill in analog implementation
Figure 12: Current profile w/ and w/o frequency modulation skill.
Figure 13: Jitter-aware target impedance w/ and w/o frequency modulation.
C. Solution to Jitter-accumulation of Low Power PLL
approach
To optimize a supply-induced phase noise performance of
PLL architecture, PSIJ of PLL architecture is analyzed to
provide the robust solution to performance. Divider supply-
induced jitter dominates the performance inside closed-loop
frequency bandwidth. VCO cell supply-induced jitter
dominates the performance outside closed-loop frequency
bandwidth. PLL supply-induced jitter performance is low pass
filter behavior. To optimize a supply-induced phase noise
performance of PLL designs, analysis to provide the robust
solution to performance. Improve the divider of analog circuit
design to achieve the optimal performance by ~20% as figure
16 based on jitter-sensitivity analysis optimization.
Figure 14: Closed-loop bandwidth of Low Power PLL clock
Figure 15: Supply-induced jitter sensitivity Plot of Low Power PLL CLK path
Figure 16: Improve jitter-sensitivity of the divider of analog circuit design.
IV. JITTER-AWARE TARGET IMPEDANCE OF POWER DELIVERY
NETWORK DESIGN IN FREQUENCY DOMAIN
To complete the PDN analysis, it is necessary to determine the
target impedance of the overall power delivery network.
However conventional target impedance only shows on-chip
supply noise value information calculated from the product of
current profile of circuit and PDN impedance. With jitter
sensitivity extraction, jitter-aware target impedance is
proposed as below shown as figure 17.

Figure 17: Jitter-aware target impedance
V. SUMMARY
Advanced Jitter-sensitivity analysis in analog field is
applied for low power transceiver and provide three kinds of
skills to solve the jitter performance improvement based on
PDN analysis. It gives the in-depth SI/PI insight into analog
design field and optimization/achieving on silicon success.
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