NARAYANA ENGINEERING COLLEGE::NELLORE

Muthukur Road, Nellore-524004

Approved by AICTE and Permanently Affiliated to JNTUA , Ananthapuramu,

An ISO 9001:2015 Certified Institution, Recognized by UGC U/S 2(f) & 12(B) and ranked "A" grade by Govt. of AP

Accredited by NAAC with “A+” Grade

Course: B.TECH II Year II SEM Academic Year: 2020-21

Name of the Subject: COMPUTER ORGANIZATION (19A05401) Class/Sec: II-CSE-A&B
Name of the Staff: Mr.V.MUNIRAJU NAIDU Department: CSE

MCQ’s Question Bank

MCQ: Multiple Choice Question

Unit
S.NO Labels to the right indicate: CO=Course Outcome, BL=BLOOMS level, ANS=Correct Answer. CO BL ANS
No:
On completion of the Lecture/ Tutorial/ Lab on a topic, students must be able to:

1. An electronic device which is used to processing the digitized data

1. 1 1 1 A
a) Computer b) Calculator c) both a and b d) None
2. Most common type of computer found in homes and schools
2. 1 1 1 B
a) Enterprise computers b) personal computers c) super computers d) All the above
3. Which computers used in weather forecasting
3. 1 1 1 C
a) Personal computers b) Workstations c) super computers d) Enterprise systems
4. Which unit stores the data and programs in computer
4. 1 1 1 D
a) Control unit b) Input unit c) output unit d) memory unit
5. 1
5. Group of lines that serve as a connecting port for several parts of a computer is called 1 1 A
a) Bus b) network c) inter connection d) Multi ports
6. 1
6. The collection of programs to accomplish a huge task or set of tasks is called 1 1 B
a) hardware b) Software c) Spyware d) Sky ware
7. The software like MS Office, Websites written in high level languages usually called
7. 1 1 1 C
a) System Software b) Simply software c) Application software d) None
8. The intermediary software between hardware and the system user is
8. 1 1 1 D
a) Compilers b) Interpreters c) Editors d) System software
9. A single computer system that operates with multiple CPUs is called
9. 1 1 1 A
a) Multiprocessor systems b) Multi computer systems c) both a and b d) None
10. Which operation reads the contents of a memory location
10. 1 1 1 B
a) Write b) Read c) Read / Write d) Write / Read
11. How many types operation the main memory can support
11. 1 1 1 C
a) 1 b) 3 c) 2 d) 4
12. The instruction without address field is called
12. 1 1 2 D
a) Tow address b) One address c) Three address d) Zero address
13. The way of resolving the address in the address field of the instruction is called
13 1 1 1 A
a) Addressing mode b) Direct mode c) Indirect mode d) Specific mode
14. The addressing mode in which the data operand is a part of the instruction
14 1 1 1 B
a) Immediate mode b) Direct mode c) Register mode d) None
15 1
15. The addressing mode in which the effective address is part in the instruction 1 1 C
a) Immediate mode b) Register mode c) Direct mode d) None
16. The addressing mode in which an operand is specified in another register or memory
16 1 location 1 1 D
a) Immediate mode b) Register mode c) Direct mode d) Indirect mode
17. The addressing mode in which the register is the source of an operand for an instruction
17 1 1 1 A
a) Register mode b) Immediate mode c) Direct mode d) Indirect mode
 MCQ: Multiple Choice Question
Unit
S.NO Labels to the right indicate: CO=Course Outcome, BL=BLOOMS level, ANS=Correct Answer. CO BL ANS
No:
On completion of the Lecture/ Tutorial/ Lab on a topic, students must be able to:

18. Insertion operation of a stack is also called

18 1 1 1 B
a) POP b) PUSH c) LIFO d) FIFO
19. Delete operation of a stack is also called
19 1 1 1 C
a) PUSH b) LIFO c) POP d) FIFO
20. The data structure which follows LIFO operation
20 1 1 2 D
a) Queue b) array c) Tree d) Stack
1. Adding two’s complement of negative number to a positive number is
21 2 2 1
a) Addition b) Subtraction c) Just two’s Complement d) None B
2. Overflow can occur when the sign of the two operands is
22 2 2 1 C
a) Different b) either different or same c) same d) none
23
2
3. In a 4 bit adder s0 available after ________ gate delays 2 1 D
a) 3 b) 2 c) 4 d) 1
4. In a 4 bit adder c1 is available after _________ gate delays
24 2 2 1 A
a) 2 b) 1 c) 3 d) 4
5. In a 4 bit adder s1 is available after __________ gate delays
25 2 2 2 B
a) 2 b) 3 c) 1 d) 4
6. In a adder/subtractor circuit if add/ subtract control is 0 then the circuit acts as
26 2 2 1 C
a) Subtractor b) multiplier c) adder d) none
7. In adder / subtractor circuit if add/ subtract control is 1 then the circuit acts as
27 2 2 1 D
a) Adder b) multiplier c) either adder or subtractor d) subtractor
8. For an n-bit adder, sn-1 is available after _______gate delays
28 2 2 1 A
a) 2n-1 b) n-1 c) 2n d) n
9. For an n-bit adder cn is available after_________ gate delays
29 2 2 2 B
a) 2n-1 b) 2n c) n-1 d) n
10. In the equation CI+1= GI+PI ci , the Gi is called
30 2 2 1 C
a) General function b) Special function c) Generate function d) Generation function
11. In the equation CI+1= GI+PI ci , the Pi is called
31 2 2 1 D
a) General function b) Special function c) Generate function d) Propagation function
12. Product of 2 n-bit numbers is at most a _________ bit number
32 2 2 1 A
a) 2n b) n+1 c) 2n+1 d) 2n-1
13. Overflow occurs if the sign of the result is different from the sign of the ______
33 2 2 1 B
a) One of the operand b) both the operands c) both a and b d) all the above
14. In singed magnitude numbering system the MSB represents
34 2 2 1 C
a) Magnitude b) Mantissa c) sign d) exponent
15. Combinatorial array multipliers are
35 2 2 1 D
a) Efficient b) extremely efficient c) inefficient d) Extremely inefficient
16. Booth’s multiplication works for
36 2 2 1 A
a) Both signed and unsigned b) only signed c) only +ve d) only –ve
17. In IEEE floating point notation the single precision representation consist of
37 2 ________ bit 2 1 B
a) 64 bits b) 32 bits c) 24 bits d) 8 bits
18. In IEEE floating point notation the single precision number mantissa contains
38 2 2 1 C
a) 64 bits b) 32 bits c) 24 bits d) 8 bits
19. In IEEE floating point notation the double precision number contains
39 2 2 1 D
a) 32 bits b) 24 bits c) 52 bits d) 64 bits
20. In IEEE floating point notation the double precision number mantissa contains
40 2 2 1 A
a) 52 bits b) 32 bits c) 24 bits d) 64 bits
1. A 16-bit computer that generates 16-bit addresses is capable of addressing up to
41 3 3 1 C
a) 16 K locations b) 16 M locationsc) 64 K locations d) 64 M locations
2. Which memory is used to increase the effective speed
42 3 3 1 D
a) Main memory b) Secondary memory c) Register memory d) cache
3. Which memory used to increase the effective size
43 3 3 1 A
a) Virtual memory b) Main memory c) Secondary memory d) cache
 MCQ: Multiple Choice Question
Unit
S.NO Labels to the right indicate: CO=Course Outcome, BL=BLOOMS level, ANS=Correct Answer. CO BL ANS
No:
On completion of the Lecture/ Tutorial/ Lab on a topic, students must be able to:

4. Memory circuits that capable of retaining their state as long as power is applied is
44 3 know 3 1 B
a) Dynamic memories b) Static memories c) a and b d) All the above
5. Memory cells are organized in the form of
45 3 3 1 C
a) a tree b) a linked list c) an arrays d) B trees
6. The amount of time it takes to transfer a word of data to or from the memory is
46 3 called 3 1 D
a) Turnaround time b) Burst time c) waiting time d) latency
7. The number of bits or bytes that can be transferred in one second is called
47 3 3 1 A
a) Bandwidth b) Latency c) Frequency d) All the above
8. ROM allow the data to be loaded by the user
48 3 3 1 B
a) EPROM b) PROM c) EEPROM d) Flash memory
9. In which ROM stored data can be erased and new data can be loaded
49 3 3 1 C
a) EEPROM b) PROM c) EPROM d) Flash memory
10. Which ROM memory can be physically removed from the circuit
50 3 3 1 D
a) EPROM b) PROM c) Flash Memory d) EEPROM
51 3
11. Which ROM memories are having higher density 3 2 A
a) Flash memory b) EPROM c) EEPROM d) PRO
12. In memory hierarchy what is the place of the register
52 3 3 1 B
a) Bottom b) On top c) Middle d) All the above
13. Which cache is available in the processor chip
53 3 3 1 C
a) L3 cache b) L2 Cache c) L1 cache d) none
14. Which cache is available in between processor and main memory
54 3 3 2 D
a) L3 cache b) L4 Cache c) L2 Cache d) L1 Cache
15. If the requested data is available in cache that is called
55 3 3 1 A
a) Cache hit b) cache miss c) Processor hit d) Processor Miss
56 3
16. If the processor is obtained the data from the cache then it is called 3 1 B
a) Cache hit b) Read hit c) Write hit d) Cache miss
17. If the requested data is not present in the cache then it is called
57 3 3 1 C
a) Cache hit b) Read Miss c) Cache miss d) Write miss
18. An area in the main memory that holds one page is called
58 3 3 1 D
a) Page table b) User space c) System Space d) Page Frame
19. Page Table Base Register consists the ___________of the page table
59 3 3 1 A
a) Base address b) Offset address c) both a and bd) none
20. In which state the processor executes the user programs
60 3 3 1 B
a) Supervisor state b) User state c) Privileged state d) none
61 4
1. Multiple I/O devices may be connected to the 4 1 D
a) Only processor b) Only memory c) neither a nor b d) a and b
2. Bus consists of ________ many lines to carry address, data and control signals
62 4 4 1 A
a) 3 b) 2 c) None d) 5
3. Each device is assigned a ________
63 4 4 1 B
a) Number b) Unique address c) Neither a nor b d) None
4. To access an I/O device, the processor places the _________ of a device on the
64 4 address line 4 1 C
a) IP number b) Device name c) Address d) Place of device
5. Which circuit coordinates the I/O transfers
65 4 4 1 D
a) Interrupts interface b) I/O Processor c) I/O Devices d) I/O Interface
6. I/O devices and Memory can share __________ memory space
66 4 4 2 A
a) Same or different b) Same c) Different d) None
7. Which register holds the data that is being transferred to or from the processor
67 4 a) Instruction Register b) Data register c) Buffer Register d) None of 4 1 B
the above
8. DMA stands for
68 4 4 1 C
a) Direct Mapping Access b) Direct Multi Access c) Direct Memory Access
 MCQ: Multiple Choice Question
Unit
S.NO Labels to the right indicate: CO=Course Outcome, BL=BLOOMS level, ANS=Correct Answer. CO BL ANS
No:
On completion of the Lecture/ Tutorial/ Lab on a topic, students must be able to:

d) None
69 4
9. Interrupts can be 4 1 D
a) Enabled b) Disabled c) Neither a nor b d) Both a and b
10. Any event that causes an interrupt is called
70 4 4 1 A
a) Exception b) Interrupt root c) Interrupt cause d) interrupt reason
11. In which mode exception occurs after the execution of every instruction
71 4 4 2 B
a) Break point b) Trace c) Debugging d) All the above
12. In which mode exception occurs only at specific points selected by the user
72 4 4 1 C
a) Trace b) Debugging c) Breakpoint d) All the above
13. process of selecting the bus master is called
73 4 a) Bus Mastering b) Bus Master altering c) Bus master selection d) Bus 4 1 D
arbitration
14. In which method a single bus arbiter select the next bus master
74 4 4 1 A
a) Centralized b) Distributed c) a and b d) None
15. In which method all devices participate in the selection on next bus master
75 4 4 1 B
a) Centralized b) Distributed c) a and b d) None
76 4
16. Which signals specifies the read and write operations 4 2 C
a) Data signals b) Address signals c) Control signals d) All the above
17. Bus also includes the lines to support the ____________________
77 4 4 1 D
a) Interrupts b) arbitration c) Neither a Nor b d) Both a and b
18. which bus all devices derive the timing information from the common clock
78 4 4 1 A
a) Synchronous b) Asynchronous c) Master d) device
19. In handshake protocol who places the address and command on the bus
79 4 4 1 B
a) Slave b) Master c) Processor d) I/O Device
20. Who removes all the signals from the bus, once slave-ready is asserted
80 4 4 1 C
a) Slave b) Processor c) Master d) I/O Device
1. Simultaneous data-processing is also called
81 5 a) Simultaneous processing b) Serial processing c) Processing d) Parallel 4 1 D
Processing
2. The purpose of parallel processing is
82 5 a) Speed up Processing b) reducing speed c) increasing processing time 5 1 A
d) None
3. The system which works on single instructions stream and single data stream
83 5 5 1 B
a) SIMD b) SISD c) MISD d) MIMD
4. The system which works on single instruction stream and multiple data streams
84 5 5 1 C
a) SISD b) MISD c) SIMD d) MIMD
5. The system which works on multiple instructions stream and single data stream
85 5 5 1 D
a) SISD b) SIMD c) MIMD d) MISD
6. The system which works on multiple instructions stream and multiple data stream
86 5 5 2 A
a) MIMD b) SISD c) SIMD d) MISD
7. Multiprocessors are also known as
87 5 a) Vector processors b)Array processors c) scalar processor d) None of 5 1 B
the above
8. How many types of array processors are there
88 5 5 1 C
a) One b) three c) two d) four
9. The organization of a single computer containing multiple processors operating
89 5 parallel 5 1 D
a) SISD b) Attached Array processor c) MIMD d) SIMD
10. Which processors are attached to the general purpose computers to improve the
90 5 performance 5 1 A
a)Attached array processors b) SIMD c) SISD d) MIMD
91 5
11. Processing Elements (PEs) in MIMD works 5 1 B
a) Synchronously b) Asynchronously c) not a not b c) None
 MCQ: Multiple Choice Question
Unit
S.NO Labels to the right indicate: CO=Course Outcome, BL=BLOOMS level, ANS=Correct Answer. CO BL ANS
No:
On completion of the Lecture/ Tutorial/ Lab on a topic, students must be able to:

12. In MIMD systems Processing Elements (PEs) are couple to the

92 5 5 2 C
a) Secondary memory b) Processor c) Main memory c) I/O devices
13. Which systems are not available commercially
93 5 5 1 D
a) SISD b) SIMD c) MISD d) MIMD
14. Dominant representative SISD systems are
94 5 5 2 A
a) IBM PC b) HP PC c) INTEL PC d) None
15. In SISD systems all the instructions and data to be processed have to be stored in
95 5 5 1 B
a) Cache memory b) Main memory c) secondary memory d) none
16. Machines based on SIMD are well suited for
96 5 5 2 C
a) Commercial computing b) education purpose c) Scientific purpose d) None
17. Dominant representative SIMD systems are
97 5 5 2 D
a) IBM PC b) HP PC c) INTEL PC d) Cray’s Vector machine
18. Which is a central processing unit that work on an entire vector in on instruction
98 5 5 2 A
a) Vector processor b) Scalar processor c) Double array processor d) None
19. Array processors increases the overall
99 5 5 1 B
a) Capacity b) instruction processing speed c) instruction sized) All the above
20. Which processors achieves high performance by means of parallel processing with
100 5 a) Single functional units b) multiple memory units c) Multiple functional 5 1 C
units d) None