Secure Hardware-based System Design – PA192

Synthesis of the sequential circuits

Lecture notes for course PA192/5

Content

5 Synthesis of the sequential circuit.........................................................................................2

5.1 Finite state machine as a mathematical model of a sequential system...................3
5.2 Ways to describe the behavior of the automaton....................................................4
5.3 sequential circuit design..........................................................................................4
5.4 Synthesis of asynchronous sequential circuits with delay......................................5
5.4.1 Example of synchronous sequential circuits with delay design..............................6
5.5 Synthesis of the synchronous sequential logic circuits...........................................7
5.5.1 Fundamental sort of the flip-flops...........................................................................8
5.5.1.1 Topology of the flip-flops...................................................................................9
5.5.1.2 Asynchronous R-S flip-flop................................................................................9
5.5.1.3 J-K flip-flop......................................................................................................11
5.5.1.4 D flip-flop.........................................................................................................12
5.5.1.5 T flip-flop..........................................................................................................14
5.5.2 Principles of synchronization of the flip-flops......................................................15
5.5.2.1 Synchronization events.....................................................................................16
5.5.2.2 More-input J-K flip-flops with two level synchronization inputs....................17
5.5.2.3 Two-phases synchronized flip-flops.................................................................18
5.5.2.4 Derivative flip-flops..........................................................................................19
List of figures............................................................................................................................22

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5 Synthesis of the sequential circuit

Sequential logic circuits generate a vector of output variables based on a vector of current
input variables and a sequence of previous vectors of input variables. Depending on the
previous input vectors, the sequencing system may generate different output vectors for a
particular input vector. This means that the sequential circuit has a memory. The information
stored in the circuit memory represents the internal variables of the system. The behavior of a
sequential logic system can be described by the function:
Fs : X* → Z*

where X*, Z* are infinite sets of all sequences with finite length composed of input vectors xi
of the set X resp. output vectors zi from the set Z. X* and Z* are called input and output
words.

The function Fs assigns an output word Z* to each input word X*. The input word X* is
a sequence of vectors xi from the time t = 0 at which the system was in state s0. The Fs
function is called a sequential system function (sequential display).

This view can be expressed using two separate functions:

si+1 = fs (xi,si)
zi = fz (xi,si)

Meaning of symbols:
fs - subsequent system state function - transient function,
fz - output functions of the system,
xi - the current input vector of the system from the set X,
zi, - the current output vector of the system from the set Z,
si - the current state of the system from the set S, which is given by the immediate
state of the internal variables,
S - the set of all possible internal states of the system - corresponds to the degree
of information stored by the system,

input Combinationa outputzi =

xi l part - Ks fz(xi, si)
current following
statesi memory statesi+1 = fs(x,
si)
i - the sequence value of the discrete time step
Figure 5.1: Block diagram of a sequential circuit

The sequential system thus forms a feedback system composed of a combination network Ks
(realizes the output display and the display of the subsequent state) and the memory of the
current state. The internal state memory can be dynamic (delay lines) or more often static
(flip-flops). If the system memory will be formed by flip-flops, then the designation used
represents:
Si+1 - excitation function of internal state variable flip-flops,
Si - internal state variables,

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 Ks - combinational network realizing the display fs a fz.

The displays fs and fz can be decomposed into the following displays for m outputs and n
states
z1(i)= fz1(x(i),s(i)) s1(i+1)= fs1(x(i),s(i))
z2(i)= fz2(x(i),s(i)) s2(i+1)= fs2(x(i),s(i))
: :
: :
zm(i)= fzm(x(i),s(i)) sn(i+1)= fsn(x(i),s(i))
where applicable:
s(i)  Si  S, x(i)  Xi  X, z(i)  Zi  Z

5.1 Finite state machine as a mathematical model of a sequential system

The behavior of a sequential system as a discrete dynamic system with memory can be
described by an algebraic system, which is an automaton (sequential machine). It is a model
of the behavior of sequential systems - but not a model of structure.

The finite automaton (sequential machine) is arranged six:

M = < X, S, Z, ω, δ, S0 >
where the meaning of the individual variables is as follows:
X - finite set of all input vectors
Z - finite set of all output vectors
S - finite set of all internal states
δ - transition function (subsequent state function) - display δ : X x S → S
ω - output function - display ω : X x S → Z nebo ω : S → Z
S0 - initial condition S0  S

Basic types of machines:

The finite automaton (machine) - the machine has a finite set of states defined (with a
total transition - output - function)
Fully designed machine - display δ and ω are defined for each Cartesian product
(X * S)
Incompletely determined automaton - for some Cartesian product (X * S) views δ and
ω are not defined
No initial automaton - the machine is designed only for five where S0 is missing
Deterministic automaton - views δ a ω are described deterministically and are constant
Stochastic automaton - views δ a ω are described by probabilistic expressions
(suitable use for the introduction of noise, reliability of
structural elements, etc.)

Transition function δ assigns to each pair xi, si (current input and current state) subsequent
(next) internal state si+1 and is identical to the function fs:
si+1 = δ(xi, si)
The output function ω can be defined in two ways:
1. The current output vector is a function of the pair xi, si (current input and current
status)
zi = ω(xi, si) - corresponds to the function fz and represents the so-called MEALY
automaton type,

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 2. The current output vector is a function of si (current status)
zi = ω(si) - corresponds to the function fz and represents the so-called MOORE
automaton type.

The MOORE automaton assigns the output only to stable states and not to transitions. It also
does not allow to change the output in one stable state according to the current value of the
input. However, this is made possible by the MEALY machine, which can lead to a smaller
number of states and therefore to a simpler solution.

MEALY machine MOORE machine

input outpu input
X combination t X combination
al part - Ks Z = (X * al part 1 - Ks
S) 1
S S = (X * S S = (X *
memory S) memory S)
combinatorial outpu
part 2 - Kz t
Z=
(S)

Figure 5.2: Block diagram of MEALY and MOORE type machines

5.2 Ways to describe the behavior of the automaton

We describe the behavior of the automaton verbally, by a time diagram of output and input
vectors and exact descriptions enabling the design of a sequential circuit:
 table of transitions,
 graphical (time course) description of the function of the sequential automaton,
 textual (verbal) description of the sequence automaton function,
 graph of transitions,
 matrix of transitions.

5.3 sequential circuit design

The aim of the synthesis is to design a logical circuit witch by the beforehand given set of
digital components realize the function of sequential circuit inscribed in the table of
transitions or graph of transitions or another method.

Set of digital components consists of function blocks as:

 basic simple gates,
 function blocks with fixed structure and function (MSI, LSI, μP, etc.),
 function blocks with programmable structure (PLA, PAL, GAL, FPGA, etc.).

He methodology of the design is based on the idea of MOORE or MEALY automat. The
general procedure of the design is following:
 submission of the timing diagram of the working sequence,
 submission of the table of transitions or graph of transitions,
 minimize the internal state set,
 selection of the internal code,

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  deduction maps of internal function (δ projection) and output function (ω projection),
 selection of the design components (gates, flip-flops, etc.),
 analytic representation of internal and output variables,
 test of the hazards and elimination of one,
 final design of the sequential logic circuit.

A sequential circuit is as a matter of fact combination net with back coupling. In the back
coupling are used memory components hold code of the internal state. The memory of
precedent code can work in static or dynamic mode.

5.4 Synthesis of asynchronous sequential circuits with delay

Memory is realized by the back coupling of the internal variable with exactly defined delay.
Time delay τ provides fixation of the transitional processes (assuring of the fundamental
mode) and filtering of the hazards (elimination of the cardinal hazard). As time delay τ is
possible use self-delay of the CN gates (i.e. τ = 0).

Xi Zi
Combinat
ionnet si+
si
τ (CN)
1

Figure 5.3: Fundamental scheme of the asynchronous sequential circuit

One of the big problems in the design of sequential circuits is choosing the correct number of
internal states. Their determination may serve the following definitions.
Note:
The internal state of a sequential logic circuit (more precisely, the state of internal variables) is the state
of the output and the current internal state (both in terms of implementation and design) necessary to change
these output variables.

For design is useful to use a minimal number of the internal states. Whatever combination of
real output variables can be accepted as a minimum set of state of the circuit. This set of states
during the proposal complements the conditions that are necessary for terms of physics the
specified task (counting the input variables, the addition of conditions necessary for the
controlled system, etc.) and subsequently states that eliminate some unsuitable properties of
the designed circuit (oscillation, the concurrence of internal variables and the like.).

There are next sorts of the internal states (in view of xi ):

 stable si = δ(si, xi)
 unstable sk = δ(si, xi)

Advantages of the asynchronous sequential circuits with delay are:

 the most general in compare with other sorts of the realization,
 the most fast, maximal working frequency is near of value f = 1/T, where T is delay of
the CN back coupling,
 very convenient for simple systems (central synchronization system is passed).

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Characterization of the automat fundamental mode:
 internal code is change in 1 variable only (elimination of the CN function hazard),
 change of the output vector is realized in the stable state of the CN only (limitation of
the working frequency),
 transitions end in stable state only (elimination of the internal state cycling, loops are
enabled),
 codes of the neighboring states differ in one bit only (elimination of the concourse).

5.4.1 Example of synchronous sequential circuits with delay design

Start with assessment:

 number of input variables,
 number of output variables,
 number of internal states - heuristic process.

If the description of the function given only sequential circuit is first step chart diagram
drawing time base sequence analysis of the behavior of the circuit by a verbal description.
The number of internal states determines the timing diagram of the basic sequence or directly
from a verbal description, which is the most common. Significant changes in the behavior of
the circuit are assigned the internal states of an automat.

The next step is the design of the transition table or graph transition in which we write the
function machine. When compiling a table of transitions start from the basic sequence typing
and then evaluate the legitimacy of the inclusion of other sequential orders (in the extreme
case, we do not accept - depending on contracting authority).
Example:
Design serial binary adder for arithmetical fusing of the two binary variables.
Solving:
The full adder performs the sum of two semantically identical bits of two variables and
adds them to transfer from a lower order (so-called the carry bit) and generates a transfer
(carry bit) to a higher order. Variables can be expressed in inverse or complementary code
and transmission of a sign bit indicates overflow. Bits of two variables represent inputs, the
sum is the output variable and the carry of the lower order can be interpreted as an internal
variable of the sequential circuit. The combinational part of a sequential circuit will
generate a carry bit to a higher order, which after the delay will represent a carry bit for the
sum of the higher-order input variables. Based on this reasoning, we can define the
following parameters:
 number of input variables 2 (bits of two operands),
 number of output variable 1 (bit of the sum),
 number of internal states 1 (carry to higher rank - digital place).
t6 t5 t4 t3 t2 t1
t t t t t t1
X1 0 0 1 1 0
X 0 05 14 13 02 0
6
0 serialadder Z
X 01111 X
1 0 1 1 1 1 0
2 0 Z2 1 0 1 0 1 0

Figure 5.4: Graph specification and table of the serial binary adder function
11/ x1, x2
00 01 11 10
01/ 0 01/
A B A A/0 A/1 B/0 A/1
110 010 B A/1 B/0 B/1 B/0
/1 /0
00/ 00/ 11/
0
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 Figure 5.5: Graph of transitions and table of transitions for the serial binary
adder
The graph of transitions is designed so that the internal state A corresponds to 0 of the
carry bit from a lower order and internal state B corresponds to 1 of the carry bit from one.
The arithmetic operation ADD begins so that the carry bit of lower order is equal to 0 - the
machine is starting in state A. Adder gets to state B only when the additional bits of both
operands are equal to 1. The adder goes back to state A when the summation bits of both
operands are equal to 0.
For further derivation, we encode internal states. In this task, we are working with two
internal states, which can be interpreted by one-bit internal variables. We specify Y as the
name of the internal variable. Internal state A we assign the value of the internal variable 0
and to the internal state of B, we assign a value 1.
From the graph of transitions is a designed table of transitions. One is based on the
definition of the output logic function and internal state logic function. See next tables.
x1 x1 x1
0/0 0/1 1/0 0/1 x2 0 0 1 0 x2 0 1 0 1 x2
U Y *
Z
0/1 1/0 1/1 1/0 0 1 1 1 1 0 1 0
Y Y Y
Forced transition table Y* - cary Z - sum
Figure 5.6: Definition of logical functions of the next state and the output
From table we get logic function for Y* a pro Z.
Z = Y x1 x2 + Y x1 x2 + Y x1 x2 + Y x1
x2
Y* = x1 x2 + Y x1 + Y x2
From these formulas we deduce scheme of sequential automat for realization of two
binary variables fuse – see Figure 5 .7.
Note:
The memory of the previous state of the adder is in this example a delay circuit (a line) to ensure the
arrival of the signal Y *, representing the carry bit from the lower order, on the input’s adder with a higher bit
of operands. Using a delay line as the memory of the previous state is currently not very common due to the
difficult physical implementation in an integrated form. This diagram assumes that the frequency of the
individual orders delivering is precisely in relation to the delay of the delay line. In current applications is
used in the delay circuit a D flip-flop, whose functions and implementation will be discussed in the following
text.

x1 &
x2 1 Z
x1 & x1 &
x2 x2
& & 1 Y*

& &

Y
t

Figure 5.7: Scheme asynchronous serial binary adder

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5.5 Synthesis of the synchronous sequential logic circuits

Synchronous circuits are based on quantization of the time. Time quantization defines
a synchronization event. For sequential circuits is this mode of operation is characteristic.
Code of the previous state of the sequence circuit is stored in the memory of the internal state,
where it is stored and used for generating the output values and generation of the next internal
state cede. Synchronization events are changed the internal state of the sequence circuit. As
a memory of internal state is using flip-flops (FF). Flip-flop is the memory of one bit of the
internal state here.

5.5.1 Fundamental sort of the flip-flops

The flip-flop is the simplest sequential circuit and represents the basic component of the more
complex sequential circuits. Flip-flop is the basis of sequential circuits and can be termed a
sequential logic element. The Block diagram of the basic symmetric flip-flop is shown next –
see Figure 5 .8.
E T Q
E
1 Q
1

2 1

Figure 5.8: Block scheme of the basic sequential logic component (flip-flop)

Flip-flop is controlled by two inputs E1 and E2. Input E1 causes that the output Q is set to 1
and the second set one to 0. The circuit has a complementary output Q, which may or may not
be escorted outside the circuit. Output Q is also an internal variable flip-flop, and therefore
the sequential logic element can be described by the next logical equation:
Q* = H(E1, E2, Q)
The following flip-flop state is the first function of the input variables E1 and E2 and secondly,
of the previous state expressed by variable Q. If we use sequential logic element in the
function of the internal variables’ memory, we obtain a sequential circuit diagram shown in
next – see Figure 5 .9.

Xi Zi

Combina
tion net

y1= T E1
QQ1 1E
21
1

yr= E1
T
QQr E2
r

r r

Figure 5.9: Fundamental scheme of the sequential circuit with flip-flops

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 D T Q
Q

From the diagram of a sequential circuit with flip-flops as memory, internal variables can be
seen that we must replace the function Y* adjusting the following internal state
Y* = G(X, Y)
by functions for controlling flip-flops, which was already mentioned earlier and has the form,
whereas apply
Q* = H(E1, E2, Q)
Y* = Q *
To properly generate Q * signals must derive formulas for generating control signals E1, E2.
This requirement meets the following symbolic equation:
E1,2 = e (X, Y, Q)
For circuits with multiple internal states, this equation splits into several logical equations
used flip-flops:
E1i = e1i(X, Y, Q)
E2i = e2i(X, Y, Q)
where e1i and e2i express logical relationships to set or reset the flip-flop i.

If we implement internal memory states of the sequential circuit by sequential logic elements,
we have to derive the equations for their setting and resetting from transitions table of one.

5.5.1.1 Topology of the flip-flops

Basic types of flip-flops.

S T Q J T Q S T Q S T Q P T Q
R Q K Q R Q R Q Q Q
R-S J-K S R P-Q
S=R=1 J=K=1 S=R=1 S=R=1 P=Q=1
prohibited Q*= Q Q*= 1 Q *= 0 Q*= Q

D
T T Q D T Q
Q V Q
T D-V
T=1 then Q*= Q V=1 then Q*= D
Q*= D
T=0 then Q*= Q V=0 then Q*= Q

5.5.1.2 Asynchronous R-S flip-flop

Flip-flop R-S is the basic and simplest biostable flip-flop realized by digital gates. Exist
realizations by NAND, NOR, or AND-OR-INVERT gates. Flip-flop R-S is a fundamental
part of all the flip-flop types.

The logic equations of the excitation signals and the circuit diagram of the R-S flip-flop can
be inferred by using the Karnaugh map – see Figure 5 .10 and Figure 5 .11.

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 R Qi+1 = S + Qi R = S (Qi R)Qi+1 = S + (Qi +
S
0 1 - 0 R)
Qi+1 Qi+1 = R + Qi S = R (Qi S)Qi+1 = R + (Qi +
1 1 - 0
Q S)
i a)b)
Figure 5.10: Asynchronous R-S flip-flop
a) map of transitions, b) logic function of the R-S flip-flop

S R R
& Q 1 Q &1
Q
&

& Q 1 Q &1
Q
R S S &

a)b) c)
Figure 5.11: Realization of the asynchronous R-S flip-flop by:
a) NAND gates,
b) NOR gates,
c) AND-OR-INVERT gates.

To use the R-S flip-flop, it is advisable to derive an application table of this flip-flop. Use the
application table to easily derive the excitation functions of the R-S circuit. The application
table is created based on the transition table and the modified transition table of this flip-flop.
R
S
0 1 - 0 Q - Q* abbreviation S R
Q*= S +
1 1 - 0 QR 0-0 u0 0 -
Q
R 0-1 s 1 0
S
u0 s - u0 1-0 r 0 1
Q Q*
u1 u1 - r 1-1 u1 - 0
Q
a)b)
Figure 5.12: Design of synchronous R-S flip-flop tables
a) transition map and modified transition map,
b) application table.

The R-S flip-flop is an essential element of other types of flip-flops. These are accomplished
by adding auxiliary logic to implement the respective functions.

Various authors emphasize that the combination S = R = 1 is prohibited, but do not state why.
If we analyze the real realization of the R-S flip-flop by NAND or NOR gates, we find that
both outputs are set to the same value. This is a possible unwanted condition that may not be
the cause of problems in many applications. If one of the input variables changes, the circuit
returns to the standard state.

The problem occurs if both input variables change at the same time. In this case, it is not
possible to determine exactly to which state the circuit will return – see Figure 5 .13. This is

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due to several reasons - practically the two signals do not change at exactly the same time, it
depends on the delay of the gates, it depends on the length of the wires for signal routing, etc.

S S
R R
S 1 0 S S S
10 0 R
R R R
S 1 S
S S S S
R R R R R
SR R SR
S S
S Q R ? R 11
S T S S
R a Q R R
R S S
R S R
a
a)b)c) R

Figure 5.13: Detailed analysis of the behavior of the R-S flip-flop:.

a) schematic mark
b) graph of transitions
c) rectified graph of transitions

5.5.1.3 J-K flip-flop

Flip-flop J-K is another basic structural element of sequential circuits. It is typical for the flip-
flop J-K that if both input signals are equal to 1, its output is inverted - it works as a counter
(divider by two). To derive its structure, we use a different procedure than to derive the
structure of the flip-flop R-S, where we proceeded from the description of its function by a
logical equation. In this case, we will implement the structure of the R-S flip-flop into a new
type of flip-flop.
0 0 1 1 J Q - Q* abbreviation S R
K
1 0 0 1 0–0 u0 0 -
Q*= JQ +
KQ 0–1 s 1 0
Q
J
u0 u0 s s 1–0 r 0 1
Q*

K
u1 r r u1 Q Q* 1–1 u1 - 0
Q
K

Q
J

a)b) J
K
0- 0- 10 10 0 0 1 1
S=QJ
-0 01 01 -0 - 0 0 -
Q
J
Q

- - 0 0 K
R=QK
0 1 1 0
Q
c)d)
Figure 5.14: Realization of the asynchronous J-K flip-flop
a) transition map and modified transition maps,
b) application table of the R-S flip-flop,
c) derivation of common excitation functions of the flip-flop R-S for realization of

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 the J-K flip-flop functions,
d) derivation of excitation functions of inputs S and R of the R-S flip-flop.

To design the transformation function of the control signals, we will use the application table
of the flip-flop circuit (i.e. the application table of the flip-flop circuit R-S), which will be
used for the implementation of the proposed circuit. The derivation of the structure and

Sa Sa
J & S & Q &1 Q
Sa K
Q &
J J T
CL CL
K K Q K & & K
R Q &1 Q
CL K J &
K R Ra
a
a) b)c) Ra

function of the J-K flip-flop is also a guide on how to design sequential circuits.
Figure 5.15: Asynchronous J-K flip-flop
a) schematic mark (gray lines show the level of synchronization circuits),
b) NAND gate realization,
c) AND-OR-INVERT gates realization.

The procedure for deriving the J-K flip-flop application table is similar – see next text.
J
K
0 0 1 1 Q - Q* abbreviation J K
Q*
1 0 0 1 0-0 u0 0 -
Q
J 0-1 s 1 -
u0 u0 s s K 1-0 r - 1
u1 r r u1
Q Q* 1-1 u1 - 0
Q a)b)
Figure 5.16: Design tables of asynchronous J-K flip-flop
a) transition map and modified transition map,
b) application table.

5.5.1.4 D flip-flop

Flip-flop D is the basic memory element. Due to its properties, it is a basic building block of
digital systems. Flip-flop D is a memory element, the input signal becomes an internal
variable after the arrival of the synchronization event. The derivation of its function is given
below - see Figure 5 .17

D
0 1 Q - Q* abbreviation S R
Q = *
0 1 0-0 u0 0 -
D
Q 0-1 s 1 0
D
u0 s 1-0 r 0 1
Q
Q*
Q
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 r u1 1-1 u1 - 0

D D D
0- 10 0 1 - 0
Q Q* S=D R=
01 -0 0 - 1 0 D
Q Q Q
c) d)d)
Figure 5.17: Realization of the asynchronous D flip-flop
a) transition map and modified transition map,
b) application table of the R-S flip-flop,
c) derivation of common excitation functions of the flip-flop R-S for realization of
the D flip-flop function,
d) derivation of excitation functions of inputs S and R of the R-S flip-flop.

Sa Sa
D & S & Q
D Q
DT
Q
CL CL
& R & Q
K K
Ra
Ra
Figure 5.18: Schematic diagram of the D flip-flop

The D flip-flop must be supplemented with a suitable central synchronization signal

processing logic. Then the circuit acts as a delay circuit with a delay given by the
synchronization period. The connection of the asynchronous flip-flop circuit type D and its
schematic mark are given above - see Figure 5 .18
D
0 1 Q* Q - Q* abbreviation D
0 1 0-0 u0 0
Q
0-1 s 1
D
u0 s 1-0 r 0
Q
r u1 Q* 1-1 u1 1
Q
a)b)
Figure 5.19: To build up the asynchronous D flip-flop
a) transition map and modified transition map,
b) application table.
Note:
The level synchronization circuits of this flip-flop circuit are marked in gray. In this scheme, the value at
input D is written to the flip-flop R-S only at the log.1 value of the CLK signal. Without sampling by the CLK
signal, the value of the D signal would be written directly to the flip-flop memory element immediately after
the delay caused by the components, and the circuit would lose the ability to store the inserted information for
a long time.
Similar to the J-K flip-flop, the asynchronous inputs for setting and resetting the D-type flip-flop are
highlighted in gray. Asynchronous inputs are used to set the sequential circuit to the default state or after
turning on the power.

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5.5.1.5 T flip-flop

The T-type flip-flop is another representative of single-input flip-flops. Due to its properties,
it is often used for the construction of some functional blocks of digital systems. Flip-flop T
represents one order of the binary counter. It is a fact that counters can generally be designed
from different types of flip-flops and that this type of single-input flip-flop is not represented
in the basic component series of electronic component manufacturers. In the following text
and in the following chapters, the design procedure of this type of flip-flop circuit will be
described, including its applications in the design of counters.
T
0 1 Q - Q* abbreviation S R
Q*=Q*T+Q
1 0 0-0 u0 0 -
*T
Q 0-1 s 1 0
T
u0 s 1-0 r 0 1
Q
u1 r 1-1 u1 - 0
Q*
Q
a)b)
T T T
0- 10 0 1 - 0
Q Q* S = TQ R = TQ
-0 01 - 0 0 1
Q Q Q
c) d) d)
Figure 5.20: Realization of the asynchronous T flip-flop
a) transition map and modified transition map,
b) application table of the R-S flip-flop,
c) derivation of common excitation functions of the flip-flop R-S for realization of
the T flip-flop function,
d) derivation of excitation functions of inputs S and R of the R-S flip-flop.

In order for the implemented flip-flop circuit of the T type to fulfill the above-mentioned
function correctly, it is necessary to supplement the scheme with a suitable logic for
processing the central synchronization signal (e.g. by a sampling circuit).

Sa
Sa T & S & Q

T Q
TT
Q CL
K & R & Q
CL
KR
Ra
a

Figure 5.21: Schematic diagram of the T flip-flop

Note:
For the exact derivation of the structure of the synchronous flip-flop circuit type T, it is possible to use the
previous procedure of the table and extend the map by the signal CLK, which at the time when it takes the
value of log. 0 passivates the flip-flop function. This will make the tables and maps a bit more complicated, but

568335159.docx 14
 the obtained equations will contain another CLK variable. We reach the same result if we use the principle of
superposition, described in the chapter on the synthesis of logic circuits.

T
0 1 Q* Q - Q* abbreviation T
1 0 0-0 u0 0
Q 0-1 s 1
T
u0 s 1-0 r 1
Q
u1 r Q* 1-1 u1 0
Q
a)b)
Figure 5.22: To build up the asynchronous T flip-flop
a) transition map and modified transition map,
b) application table.

5.5.2 Principles of synchronization of the flip-flops

In terms of structure and function of the additional logic we distinguish flip-flops:

 asynchronous,
 synchronous.

As indicated in the case of the D-type flip-flop, the individual types of flip-flops operate in
asynchronous mode with great difficulty. For this reason, flip-flops are equipped with other
technical equipment, which allows to precisely define synchronization events causing writing
to the memory part of the flip-flop within a discrete time. The source of discrete time in
digital systems is a synchronization signal generated centrally for the entire device.

It has been emphasized several times that the memory element of the flip-flops is an
asynchronous flip-flop R-S. The properties of a specific type of flip-flop are provided by
additional logic, the design of which we demonstrated on two examples of flip-flops J-K and
D.

Asynchronous design is complicated. Synchronization allows simplify the design of

sequential circuits. Response of the FF to input variables takes place at precisely defined
times of the central synchronization signal – CLK (clock). Synchronization provides
additional logic of the FF. General scheme of the synchronous flip-flop is shown below – see
Figure 5 .23.

E S Q
T
E
1 R Q
2 logic of the
CL flip-flop
K synchroniza
tion

Figure 5.23: General scheme of flip-flop

Larger digital systems require more careful timing of the synchronization signals of the
individual flip-flops to eliminate the time delays of their function blocks. For this reason, they

568335159.docx 15
are equipped with a timing synchronization system that generates sequences of
synchronization signals, so-called cycles and phases. With this type of synchronization, it is
not necessary to use derivative or two-phase flip-flops to design a digital system. Writing to
the individual flip-flops connected in series is ensured by different phases of one cycle of the
synchronization system, which ensures the time interval of writing to the individual flip-flops
- see Figure 5 .26. Thanks to this, significantly simpler level flip-flops can be used for the
construction of the system without any problems.

5.5.2.1 Synchronization events

synchronization by level

synchronization by raising
edge

synchronization by falling
edge
external synchronization

Figure 5.24: Types of sync events of synchronous sequential circuits

Synchronous flip-flops can be classified according of the type of synchronization as:

 level synchronized flip-flops,
 two-phases flip-flops,
 derivative flip-flops,
 central synchronized.

M. S.
S & Q
Q E T
1
Q E1 Q
Sa T E2
Sa T sampler
Sa T
Q E2
R & Ra
Q Ra
Q Ra Q
T T
T
Q Q Q E1 Q
Sa T ST E1 T T
Q R Q E2 T Q E2
Q
Ra T
T T T
a) b) c)d)

Figure 5.25: Schematic mark and symbolic diagram of the different types of the
flip-flop circuits according to the synchronization methods
a) asynchronous FF
b) level synchronized FF
c) two-phase’s FF
d) derivative FF

Asynchronous flip-flops do not have a synchronization event generation module in the

additional logic. The correct behavior of this type of flip-flop must be ensured by the relevant

568335159.docx 16
behavior of the input signals.

Level-synchronized flip-flops have a synchronization event defined by the active level of the
synchronization signal. It is typical for this synchronization that the state of the internal
memory of the flip-flop may change depending on the changes of the input signals for the
duration of the active level of the synchronization signal. In order to prevent the incorrect
setting of the flip-flop function, the input signals must be stable during the active level of the
synchronization signal - transients on the input signals of the additional logic must disappear
before the arrival of the active level of the synchronization signal.

CL
M. S.
KT Q
1 E1 T Q
T2 E Sa T
2
Q Ra
T Q
T3 T
1

T4 2

cycle
a)b)
Figure 5.26: Central synchronization system used for synchronization of the
two phase’s flip-flop
a) the timing diagram of the central synchronization system,
b) the block diagram of the flip-flop.

5.5.2.2 More-input J-K flip-flops with two level synchronization inputs

Examples two inputs flips-flops.

R &1 Q
Q* = CLK*R + (Q + CLK*S) &
Q* = CLK*S + (Q + CLK*R) CL
K &1 Q
S &
Figure 5.27: Wiring diagram of a level synchronous R-S flip flop

R1 &1 Q
R2 &
Q* = X1 R1 + (Q + X1 S1) + X2 R2 + (Q + X2 S2) &
X2
Q* = X1 S1 + (Q + X1 R1) + X1 S1 + (Q + X2 R2) X1
&1
S Q
&
S
1 &
2

Figure 5.28: Wiring diagram of the level synchronous R-S flip-flop with two
synchronization signals and two group of the input variables

568335159.docx 17
 K &1 Q
K
1 &
2 &
Q* = CLK1 (JQ + KQ) + CLK2 (JQ + KQ) CLK
CLK
2

1
&1 Q
J1 &
J2 &
Figure 5.29: Wiring diagram of the level synchronous circuit J-K flip-flop with
two synchronization inputs

Sa
J1 & S
1
CL & Q
K1 & R
K 1
1
J2 & S
2
& Q
CL
K2 & R
2
R
a

Figure 5.30: Wiring diagram of the level synchronous circuit J-K flip-flop
realized by NAND gates with two synchronization signals and two group
of the input variables

568335159.docx 18
 Q
Q
&1

&1
&

&
&

Q
Q
&1

&1
&

&
S

R
Ka

Ji

a
CL
i

K
5.5.2.3 Two-phases synchronized flip-flops
Figure 5.31: Diagram of two-phases synchronized J-K flip-flop

S
Ka
&1 Q & &T Q
1
K & 1
2 &
CL &
K
CL
2
K1 &1 & &
J1 & Q Q

J2 &
R
a

Figure 5.32: Wiring diagram of three-inputs two-phases synchronous J-K FF

with two groups of input variables and two synchronization signals - the
first option

568335159.docx 19
 Q
Q&1

&1
&

&
&

Q
Q
&1

&1
&
&

&
&
S

2R
Ka
K

a
J
J
1
1

2
CL
CL
2
K1
K
Figure 5.33: Wiring diagram of three-inputs synchronous J-K flip-flop with two
groups of input variables and two synchronization signals – see second
option

M
J1 . Q
J 1T
K K Q S
Q
1
CL S .T
K1 M R
a Q
J2 . Q
J 2T a
K K Q
2
CL
K2 &

Figure 5.34: Diagram of two-phases synchronous J-K flip-flop with two

synchronized sections made up of flip-flops

5.5.2.4 Derivative flip-flops

Derivative flip-flops use sampling circuitry for generating of the synchronization events. The
function of the sampling circuit is based on usage of the combinational logic hazards – see
Figure 5 .35 – or sampling circuit.

568335159.docx 20
T
+
 T &

T(τ
tpd

)
T(τ
T

T
)T
+

T+
&

T(τ)
3*tpd
T(τ)

T
T+
T

Figure 5.35: The principle of the hazard synchronization operation – raising

edge

S & Sa & Q

CL
K & Ra & Q
R
Figure 5.36: Derivative S-R flip-flop circuit with a hazard generation of the
synchronization signal

568335159.docx 21
 S
a &
S

Sa
S Q & Sa & Q
S T
R R Q
CL CL
K & Ra &
K Q
Ra

&
R
Ra

Sa &

& Sa & Q
Sa
D DT Q
CL & & Q
CL Q K
KR Ra
a

&
D
Ra
Figure 5.37: Logic diagram of the derivative R-S flip-flop with sampling circuit
Figure 5.38: Logical diagram the derivation type D flip-flop with sampling
circuit

568335159.docx 22
 List of figures

Figure 5.1: Block diagram of a sequential circuit.......................................................................2

Figure 5.2: Block diagram of MEALY and MOORE type machines.......................................4
Figure 5.3: Fundamental scheme of the asynchronous sequential circuit..................................5
Figure 5.4: Graph specification and table of the serial binary adder function.........................6
Figure 5.5: Graph of transitions and table of transitions for the serial binary adder...............6
Figure 5.6: Definition of logical functions of the next state and the output...............................7
Figure 5.7: Scheme asynchronous serial binary adder..............................................................7
Figure 5.8: Block scheme of the basic sequential logic component (flip-flop)..........................8
Figure 5.9: Fundamental scheme of the sequential circuit with flip-flops.................................8
Figure 5.10: Asynchronous R-S flip-flop...................................................................................9
Figure 5.11: Realization of the asynchronous R-S flip-flop by:...............................................10
Figure 5.12: Design of synchronous R-S flip-flop tables.........................................................10
Figure 5.13: Detailed analysis of the behavior of the R-S flip-flop:........................................11
Figure 5.14: Realization of the asynchronous J-K flip-flop.....................................................11
Figure 5.15: Asynchronous J-K flip-flop.................................................................................12
Figure 5.16: Design tables of asynchronous J-K flip-flop.......................................................12
Figure 5.17: Realization of the asynchronous D flip-flop........................................................13
Figure 5.18: Schematic diagram of the D flip-flop...................................................................13
Figure 5.19: To build up the asynchronous D flip-flop............................................................13
Figure 5.20: Realization of the asynchronous T flip-flop.........................................................14
Figure 5.21: Schematic diagram of the T flip-flop...................................................................14
Figure 5.22: To build up the asynchronous T flip-flop............................................................15
Figure 5.23: General scheme of flip-flop..................................................................................15
Figure 5.24: Types of sync events of synchronous sequential circuits.....................................16
Figure 5.25: Schematic mark and symbolic diagram of the different types of the flip-flop
circuits according to the synchronization methods...........................................................16
Figure 5.26: Central synchronization system used for synchronization of the two phase’s flip-
flop....................................................................................................................................17
Figure 5.27: Wiring diagram of a level synchronous R-S flip flop..........................................17
Figure 5.28: Wiring diagram of the level synchronous R-S flip-flop with two synchronization
signals and two group of the input variables....................................................................17
Figure 5.29: Wiring diagram of the level synchronous circuit J-K flip-flop with two
synchronization inputs......................................................................................................18
Figure 5.30: Wiring diagram of the level synchronous circuit J-K flip-flop realized by NAND
gates with two synchronization signals and two group of the input variables..................18
Figure 5.31: Diagram of two-phases synchronized J-K flip-flop.............................................18
Figure 5.32: Wiring diagram of three-inputs two-phases synchronous J-K FF with two groups
of input variables and two synchronization signals - the first option...............................19
Figure 5.33: Wiring diagram of three-inputs synchronous J-K flip-flop with two groups of
input variables and two synchronization signals – see second option..............................19
Figure 5.34: Diagram of two-phases synchronous J-K flip-flop with two synchronized
sections made up of flip-flops...........................................................................................19
Figure 5.35: The principle of the hazard synchronization operation – raising edge.................20
Figure 5.36: Derivative S-R flip-flop circuit with a hazard generation of the synchronization
signal.................................................................................................................................20
Figure 5.37: Logic diagram of the derivative R-S flip-flop with sampling circuit...................20
Figure 5.38: Logical diagram the derivation type D flip-flop with sampling circuit...............21

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