IPD075N03LG

MOSFET
OptiMOSª3Power-Transistor,30V DPAK

tab
Features
•FastswitchingMOSFETforSMPS
•OptimizedtechnologyforDC/DCconverters
•QualifiedaccordingtoJEDEC1)fortargetapplications
•N-channel,logiclevel
•ExcellentgatechargexRDS(on)product(FOM) 2
1
•Verylowon-resistanceRDS(on)
•Avalancherated 3
•Pb-freeplating;RoHScompliant
•Halogen-freeaccordingtoIEC61249-2-21

Drain
Pin 2, Tab
Table1KeyPerformanceParameters
Parameter Value Unit
Gate
Pin 1
VDS 30 V
RDS(on),max 7.5 mΩ Source
Pin 3

ID 50 A

Type/OrderingCode Package Marking RelatedLinks

IPD075N03L G PG-TO252-3 075N03L -

1)
J-STD20 and JESD22
Final Data Sheet 1 Rev.2.2,2020-09-14
 OptiMOSª3Power-Transistor,30V
IPD075N03LG

TableofContents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Final Data Sheet 2 Rev.2.2,2020-09-14

 OptiMOSª3Power-Transistor,30V
IPD075N03LG

1Maximumratings
atTA=25°C,unlessotherwisespecified

Table2Maximumratings
Values
Parameter Symbol Unit Note/TestCondition
Min. Typ. Max.
- - 50 VGS=10V,TC=25°C
- - 43 VGS=10V,TC=100°C
Continuous drain current ID A
- - 49 VGS=4.5V,TC=25°C
- - 35 VGS=4.5V,TC=100°C
Pulsed drain current1) ID,pulse - - 350 A TC=25°C
Avalanche current, single pulse 2)
IAS - - 50 A TC=25°C
Avalanche energy, single pulse EAS - - 50 mJ ID=12A,RGS=25Ω
Gate source voltage VGS -20 - 20 V -
Power dissipation Ptot - - 47 W TC=25°C
IEC climatic category;
Operating and storage temperature Tj,Tstg -55 - 175 °C
DIN IEC 68-1: 55/175/56

2Thermalcharacteristics

Table3Thermalcharacteristics
Values
Parameter Symbol Unit Note/TestCondition
Min. Typ. Max.
Thermal resistance, junction - case RthJC - - 3.2 K/W -
SMD version, device on PCB,
RthJA - - 75 K/W -
minimal footprint
SMD version, device on PCB,
RthJA - - 50 K/W -
6 cm² cooling area3)

1)
See figure 3 for more detailed information
2)
See figure 13 for more detailed information
3)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection.
PCB is vertical in still air.
Final Data Sheet 3 Rev.2.2,2020-09-14
 OptiMOSª3Power-Transistor,30V
IPD075N03LG

3Electricalcharacteristics
atTj=25°C,unlessotherwisespecified

Table4Staticcharacteristics
Values
Parameter Symbol Unit Note/TestCondition
Min. Typ. Max.
Drain-source breakdown voltage V(BR)DSS 30 - - V VGS=0V,ID=1mA
Gate threshold voltage VGS(th) 1 - 2.2 V VDS=VGS,ID=250µA
- 0.1 1 VDS=30V,VGS=0V,Tj=25°C
Zero gate voltage drain current IDSS µA
- 10 100 VDS=30V,VGS=0V,Tj=125°C
Gate-source leakage current IGSS - 10 100 nA VGS=20V,VDS=0V
- 9.1 11.4 VGS=4.5V,ID=30A
Drain-source on-state resistance1) RDS(on) mΩ
- 6.3 7.5 VGS=10V,ID=30A
Gate resistance RG - 1.3 - Ω -
Transconductance gfs 30 61 - S |VDS|>2|ID|RDS(on)max,ID=30A

Table5Dynamiccharacteristics
Values
Parameter Symbol Unit Note/TestCondition
Min. Typ. Max.
Input capacitance2) Ciss - 1400 1900 pF VGS=0V,VDS=15V,f=1MHz
Output capacitance2) Coss - 580 770 pF VGS=0V,VDS=15V,f=1MHz
Reverse transfer capacitance 2)
Crss - 29 44 pF VGS=0V,VDS=15V,f=1MHz
VDD=15V,VGS=10V,ID=30A,
Turn-on delay time td(on) - 4.3 - ns
RG=1.6Ω
VDD=15V,VGS=10V,ID=30A,
Rise time tr - 3.6 - ns
RG=1.6Ω
VDD=15V,VGS=10V,ID=30A,
Turn-off delay time td(off) - 17 - ns
RG=1.6Ω
VDD=15V,VGS=10V,ID=30A,
Fall time tf - 2.8 - ns
RG=1.6Ω

Table6Gatechargecharacteristics3)
Values
Parameter Symbol Unit Note/TestCondition
Min. Typ. Max.
Gate to source charge Qgs - 4.6 - nC VDD=15V,ID=30A,VGS=0to4.5V
Gate charge at threshold Qg(th) - 2.2 - nC VDD=15V,ID=30A,VGS=0to4.5V
Gate to drain charge Qgd - 2.1 - nC VDD=15V,ID=30A,VGS=0to4.5V
Switching charge Qsw - 4.4 - nC VDD=15V,ID=30A,VGS=0to4.5V
Gate charge total Qg - 8.7 - nC VDD=15V,ID=30A,VGS=0to4.5V
Gate plateau voltage Vplateau - 3.3 - V VDD=15V,ID=30A,VGS=0to4.5V
Gate charge total Qg - 18 - - VDD=15V,ID=30A,VGS=0to10V
Gate charge total, sync. FET Qg(sync) - 7.6 - nC VDS=0.1V,VGS=0to4.5V
Output charge Qoss - 15 - - VDD=15V,VGS=0V

1)
Measured from drain tab to source pin
2)
Defined by design. Not subject to production test
3)
See ″Gate charge waveforms″ for parameter definition
Final Data Sheet 4 Rev.2.2,2020-09-14
 OptiMOSª3Power-Transistor,30V
IPD075N03LG

Table7Reversediode
Values
Parameter Symbol Unit Note/TestCondition
Min. Typ. Max.
Diode continuous forward current IS - - 42 A TC=25°C
Diode pulse current IS,pulse - - 350 A TC=25°C
Diode forward voltage VSD - 0.89 1.1 V VGS=0V,IF=30A,Tj=25°C
Reverse recovery charge 1)
Qrr - - 10 nC VR=15V,IF=IS,diF/dt=400A/µs

1)
Defined by design. Not subject to production test
Final Data Sheet 5 Rev.2.2,2020-09-14
 OptiMOSª3Power-Transistor,30V
IPD075N03LG

4Electricalcharacteristicsdiagrams

Diagram1:Powerdissipation Diagram2:Draincurrent
50 60

50
40

40

30
Ptot[W]

ID[A]
30

20

20

10
10

0 0
0 50 100 150 200 0 50 100 150 200
TC[°C] TC[°C]
Ptot=f(TC) ID=f(TC);VGS≥10V

Diagram3:Safeoperatingarea Diagram4:Max.transientthermalimpedance
3
10 101

1 µs

102 10 µs 0.5

100
100 µs
0.2
DC
ZthJC[K/W]

0.1
ID[A]

101
0.05
1 ms
0.02

10 ms 10-1 0.01

0
10 single pulse

10-1 10-2
10-1 100 101 102 10-6 10-5 10-4 10-3 10-2 10-1 100
VDS[V] tp[s]
ID=f(VDS);TC=25°C;D=0;parameter:tp ZthJC=f(tp);parameter:D=tp/T

Final Data Sheet 6 Rev.2.2,2020-09-14

 OptiMOSª3Power-Transistor,30V
IPD075N03LG

Diagram5:Typ.outputcharacteristics Diagram6:Typ.drain-sourceonresistance
120 20
5V 4.5 V
3.2 V
100
16
10 V

80 3.5 V 4V

4V 12

RDS(on)[mΩ]
ID[A]

4.5 V
60

8 5V
10 V
40 3.5 V
11.5 V

4
20 3.2 V

3V
2.8 V
0 0
0 1 2 3 0 20 40 60 80 100
VDS[V] ID[A]
ID=f(VDS);Tj=25°C;parameter:VGS RDS(on)=f(ID);Tj=25°C;parameter:VGS

Diagram7:Typ.transfercharacteristics Diagram8:Typ.forwardtransconductance
100 100

80 80

60 60
gfs[S]
ID[A]

40 40

20 20

175 °C
25 °C
0 0
0 1 2 3 4 5 0 20 40 60 80 100
VGS[V] ID[A]
ID=f(VGS);|VDS|>2|ID|RDS(on)max;parameter:Tj gfs=f(ID);Tj=25°C

Final Data Sheet 7 Rev.2.2,2020-09-14

 OptiMOSª3Power-Transistor,30V
IPD075N03LG

Diagram9:Drain-sourceon-stateresistance Diagram10:Typ.gatethresholdvoltage
16 2.5

14

2.0
12

10
1.5
RDS(on)[mΩ]

VGS(th)[V]
98 %
8

typ 1.0
6

4
0.5

0 0.0
-60 -20 20 60 100 140 180 -60 -20 20 60 100 140 180
Tj[°C] Tj[°C]
RDS(on)=f(Tj);ID=30A;VGS=10V VGS(th)=f(Tj);VGS=VDS;ID=250µA

Diagram11:Typ.capacitances Diagram12:Forwardcharacteristicsofreversediode
4
10 103
25 °C
25 °C, max
175 °C
175 °C, max

103 Ciss

102
Coss
C[pF]

IF[A]

102

Crss
101

101

100 100
0 10 20 30 0.0 0.5 1.0 1.5 2.0
VDS[V] VSD[V]
C=f(VDS);VGS=0V;f=1MHz IF=f(VSD);parameter:Tj

Final Data Sheet 8 Rev.2.2,2020-09-14

 OptiMOSª3Power-Transistor,30V
IPD075N03LG

Diagram13:Avalanchecharacteristics Diagram14:Typ.gatecharge
2
10 12
15 V

6V 24 V
10

150 °C 100 °C 25 °C

VGS[V]
IAV[A]

101 6

100 0
10-1 100 101 102 103 0 4 8 12 16 20 24
tAV[µs] Qgate[nC]
IAS=f(tAV);RGS=25Ω;parameter:Tj(start) VGS=f(Qgate);ID=30Apulsed;parameter:VDD

Diagram15:Drain-sourcebreakdownvoltage Diagram Gate charge waveforms

34

32

30

28
VBR(DSS)[V]

26

24

22

20
-60 -20 20 60 100 140 180
Tj[°C]
VBR(DSS)=f(Tj);ID=1mA

Final Data Sheet 9 Rev.2.2,2020-09-14

 OptiMOSª3Power-Transistor,30V
IPD075N03LG

5PackageOutlines

MILLIMETERS
DIMENSION
MIN. MAX.
DOCUMENT NO.
A 2.16 2.41
Z8B00003328
A1 0.00 0.15
b 0.64 0.89 REVISION
b2 0.65 1.15 07
b3 4,95 5.50 SCALE:
c 0.46 0.61
10:1
c2 0.40 0.98
D 5.97 6.22 0 1 2mm
D1 5.02 5.84
E 6.35 6.73
E1 4.32 5.50 EUROPEAN PROJECTION
e 2.29
e1 4.57
N 3
H 9.40 10.48
L 1.18 1.78
L3 0.89 1.27 ISSUE DATE
L4 0.51 1.02 01.04.2020

Figure1OutlinePG-TO252-3,dimensionsinmm

Final Data Sheet 10 Rev.2.2,2020-09-14

 OptiMOSª3Power-Transistor,30V
IPD075N03LG

RevisionHistory
IPD075N03L G

Revision:2020-09-14,Rev.2.2
Previous Revision
Revision Date Subjects (major changes since last revision)
2.2 2020-09-14 Update POD

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Final Data Sheet 11 Rev.2.2,2020-09-14