BOARD PRACTICAL EXAMINATIONS – OCTOBER 2017

CENTRE 386-Dr.M.G.R. Polytechnic College , ARNI-632317

COURSE ELECTRONICS & COMMUNICATION ENGG

SUBJECT VERY LARGE SCALE INTEGRATION LAB SUBJECT CODE 34057

DATE 09.10.17 Max.Marks 75

TIME 3 Hrs Min.Marks 35

SPECIMEN QUESTION PAPER

1. To Simulate the VHDL code for combinational circuit

2. To Simulate the VHDL code for arithmetic circuits
3. To Simulate the VHDL code for multiplexer
4. To Simulate the VHDL code for Demultiplexer
5. To implement the VHDL code for multiplexer
6. .To implement the VHDL code for Demultiplexer
7. .To implement the VHDL code for 7 segment decoder
8. .To implements the VHDL code for 7 segment decoder by LUT
9. .To implement the VHDL code for encoder
10. To Simulate the VHDL code for delay
11. .To implement the VHDL code for blinking a led
12. To Simulate the VHDL test bench code for testing a gate
13. .To implement the VHDL code for blinking a array of LED
14. .To implement the VHDL code for speller with an array of LED
15. .To implement the VHDL code for 7 segment display

INTERNAL EXAMINER EXTERNAL EXAMINER

 BOARD PRACTICAL EXAMINATIONS – OCTOBER 2017

CENTRE 386-Dr.M.G.R. Polytechnic College , ARNI-632317

COURSE ELECTRONICS & COMMUNICATION ENGG

SUBJECT VERY LARGE SCALE INTEGRATION LAB SUBJECT CODE 34057

DATE 09.10.17 Max.Marks 75

TIME 3 Hrs Min.Marks 35

MARK ALLOCATION

A - INTERFACE CIRCUIT DIAGRAM - 10

B - ALGORITHM/FLOW CHAT - 20

C - PROGRAM - 20

D - OBSERVATION - 10

E - RESULT - 10

V - VIVA VOICE - 05

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TOTAL - 75

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INTERNAL EXAMINER EXTERNAL EXAMINER