Instituto Tecnológico de Santo Domingo (INTEC)

Clave: IEC208L

Sección: 4

Tema:

Bloques combinacionales en VHDL

Nombre

Gian Susana Sánchez

ID:1099881

Asignatura: LAB. FUNDAMENTOS ELECTRÓNICA DIGITAL

Nombre del profesor/a: YOBANY DIAZ ROQUE

Objetivo: Implementar en VHDL un Full Adder de dos entradas de 4 bits y
un Decodificador BCD a display de 7 segmentos (Ánodo Común). Hacerle el
testbench y analizar las señales generadas. Hacer reporte en pdf.

Procedimiento
En el caso del display el VHDL seria:
-- Decodificador BCD para display de leds.
library IEEE;
use IEEE.std_logic_1164.all;

entity decoderBCD4to7segments is
port (
a, b, c, d, e, f, g : out std_logic;
x3, x2, x1, x0 : in std_logic
);
end entity;

architecture arch of decoderBCD4to7segments is

begin

-- Decodificamos..
process (x3, x2, x1, x0)
variable auxVectOut : std_logic_vector (6 downto 0);
variable auxVectIn : std_logic_vector (3 downto 0);
begin

-- Cargamos entradas al vector auxiliar.

auxVectIn(3) := x3;
 auxVectIn(2) := x2;
auxVectIn(1) := x1;
auxVectIn(0) := x0;

if auxVectIn = "0000" then auxVectOut := "1111110"; -- 0

elsif auxVectIn = "0001" then auxVectOut := "0110000"; -- 1
elsif auxVectIn = "0010" then auxVectOut := "1101101"; -- 2
elsif auxVectIn = "0011" then auxVectOut := "1111001"; -- 3
elsif auxVectIn = "0100" then auxVectOut := "0110011"; -- 4
elsif auxVectIn = "0101" then auxVectOut := "1011011"; -- 5
elsif auxVectIn = "0110" then auxVectOut := "1011111"; -- 6
elsif auxVectIn = "0111" then auxVectOut := "1110000"; -- 7
elsif auxVectIn = "1000" then auxVectOut := "1111111"; -- 8
elsif auxVectIn = "1001" then auxVectOut := "1110011"; -- 9
else auxVectOut := "UUUUUUU";
end if;

-- Cargamos salidas al vector auxiliar.

a <= auxVectOut(6);
b <= auxVectOut(5);
c <= auxVectOut(4);
d <= auxVectOut(3);
e <= auxVectOut(2);
f <= auxVectOut(1);
g <= auxVectOut(0);

end process;
end architecture;

library IEEE;
use IEEE.std_logic_1164.all;

entity decoderBCD4to7segments_tb is
end entity;

architecture arch of decoderBCD4to7segments_tb is

component decoderBCD4to7segments is
port (
a, b, c, d, e, f, g : out std_logic;
x3, x2, x1, x0 : in std_logic
);
end component;

signal tbVectOut : std_logic_vector (6 downto 0);

signal tbVectIn : std_logic_vector (3 downto 0);

begin

unit_unde_test: decoderBCD4to7segments port map (

a => tbVectOut(6),
b => tbVectOut(5),
c => tbVectOut(4),
 d => tbVectOut(3),
e => tbVectOut(2),
f => tbVectOut(1),
g => tbVectOut(0),
x3 => tbVectIn(3),
x2 => tbVectIn(2),
x1 => tbVectIn(1),
x0 => tbVectIn(0)
);

generate_input_signals : process
begin
tbVectIn <= "UUUU"; wait for 10 ns;
tbVectIn <= "0000"; wait for 10 ns;
tbVectIn <= "0001"; wait for 10 ns;
tbVectIn <= "0010"; wait for 10 ns;
tbVectIn <= "0011"; wait for 10 ns;
tbVectIn <= "0100"; wait for 10 ns;
tbVectIn <= "0101"; wait for 10 ns;
tbVectIn <= "0110"; wait for 10 ns;
tbVectIn <= "0111"; wait for 10 ns;
tbVectIn <= "1000"; wait for 10 ns;
tbVectIn <= "1001"; wait for 10 ns;
tbVectIn <= "1010"; wait for 10 ns;
tbVectIn <= "1011"; wait for 10 ns;
tbVectIn <= "1100"; wait for 10 ns;
tbVectIn <= "1101"; wait for 10 ns;
 tbVectIn <= "1110"; wait for 10 ns;
tbVectIn <= "1111"; wait for 10 ns;
report "Simulación terminada.";
wait;
end process;

end architecture;