A MODIFIED PSEUDORANDOM BIT
GENERATOR AND ITS VLSI ARCHITECTURE
Student : SARANG P C (T19150)
Guide: Dr. Hitesh Shrimali
Abstract—Pseudorandom bit sequence plays an important role
when it comes to secured data transmission and storage. A pseu-
dorandom sequence is generated by a well defined mathematical
algorithm. A circuit which generates a pseudorandom sequence
is known as a pseudorandom sequence generator. A new method
for generating pseudorandom bits is mentioned in this paper
along with its VLSI architecture. The comparison of this method
with the current state of art is described and the simulation
results are given after making the architecture using a hardware
descriptive language.
I. INTRODUCTION
One of the major concern in various internet of things appli-
cations is the security of the data which is being transmitted.
The pseudorandom bit generator is an essential component
to manage user privacy in IoT enabled resource constraint
devices. Pseudorandom sequence can be used in the encryption
of the data which is being transmitted so that the transmission
of data is secure. The pseudorandom sequences have been
widely used in numerous essential areas such as information
security, telecommunications etc. A pseudorandom sequence
generator is nothing but a circuit with a well defined mathe-
matical algorithm that produces a sequence that appears to be
random and is indistinguishable from a real random sequence.
In order for a sequence to be accepted as a pseudorandom se-
quence, it should pass all the fifteen benchmark tests proposed
by the National Institute of Standard and Technology (NIST).
Many of the previous methods either fails this tests or they
consume a larger hardware area or more latency is consumed.
The new method proposed is a modified version of coupled
linear congruential method [1]. The proposed method passes
all fifteen benchmark tests of NIST standard. It consumes
lesser hardware cost and clock latency is also reduced to a
single clock cycle. The length of the sequence generated is
also doubled compared to the previous method and also an
output bit is being generated in every clock cycle.
II. T HEORY
One of the major application of pseudorandom sequence
is in the field of spread spectrum communication [2]. Spread
spectrum communication is used to transmit low frequency
data signals by spreading it with high frequency pseudorandom
signals. Pseudorandom signals have very high frequency and
since it is having random nature, they appear almost like noise
signals. Therefore, after spreading the message signals with
high frequency pseudorandom signals, the spreaded output
appears almost like a noise and is being transmitted securely.
Fig. 1. Spread Spectrum Communication
Spread spectrum communication method finds its applica-
tion in defense related communication where security of the
data being transmitted is of prime importance. At the receiver
side, the same pseudorandom sequence generator is used with
the same initial seed so that the same sequence is generated
and this is used in the recovery of the message signal from the
spreaded signal. This is called despreading of the signal. After
despreading, the original message signal is obtained back.
The major focus of this paper is the formation of the
PN Sequence Generator block used in spread spectrum
communication. A new method for generation of PN sequence
has been proposed along with its VLSI architecture [1] . The
main aim is to implement the VLSI architecture using a HDL
tool and to burn the code in a standard FPGA board and
analyse the working of the PN generator.
A. Linear Congruential Generator
The major building block in the method proposed is a linear
congruential generator, more commonly known as LCG [3].
An LCG is nothing but a mathematical algorithm for the
synthesis of random sequence. The mathematical algorithm
for generating the sequence is given by
xi+1 = a × xi + b mod2n .
Where xi+1 is the next number in the sequence, xi is the
current number in the sequence. ’a’ and ’b’ are constant
parameters and ’n’ is the total number of bits used. Initially,
a number x0 is being given as input to the LCG and is called
the initial seed. Depending upon the value of a, b, and initial
seed, the sequence obtained is different from one another. Even
though Pseudorandom numbers appear to be non repetitive,
 x0 y0
they are periodic with sufficiently large period. The maximum Start Start

length of the sequence or period is obtained in an LCG under

some conditions [3]. MUX MUX
• The constant b should be relatively prime with the value xi yi
<< <<
2n
• The constant a-1 should be divisible by 4. 2r1*xi 2r2*yi

If these conditions are obtained, the maximum sequence length

in an LCG can be obtained which is 2n .
An example of an LCG for a given set of parameters and initial b1 b2

seed is given below. Here the values of parameters used were,

a=5, b=1 , n=3 and the initial seed X0 is given as 3. For these
set of inputs, the sequence obtained is (0,1,6,7,4,5,2,3). REG REG

xi+1 yi+1
x0 Start

MUX
CMP
xi <<
Bi
2r*xi

Fig. 3. Architecture of a coupled LCG

C. The dual-CLCG method

REG
xi+1
Fig. 2. Architecture of a simple LCG
The block diagram of an LCG is shown in figure 2. Since
the constant ’a-1’ should be multiplied by 4, we can replace
’a’ with 2r +1. Where the multimple of 4 is replaced with
2r . Therefore, the equation of LCG can be re-obtained by
substituting the value for ’a’ and therefore we obtain
xi+1 = 2r × xi + xi + b mod2n .
The multiplication of xi with 2r is obtained by left shifting xi
r times.
The dual-CLCG Method [1] uses two CLCGs instead of
a single CLCG. The first is called the controller CLCG and
the second one is the controlled CLCG. The overall output is
being controlled by the output of the controller CLCG. The
output of controller CLCG determines whether the output of
the controlled CLCG is to be given as the overall output or not.
xi+1 = a1 × xi + b1 mod2n .
yi+1 = a2 × yi + b2 mod2n .
Bi = 1 if xi+1 > yi+1 and zero otherwise
pi+1 = a3 × pi + b3 mod2n .
qi+1 = a4 × qi + b4 mod2n .
Ci = 1 if pi+1 > qi+1 and zero otherwise

B. Coupled Linear Congruential Generator The overall output Zi is given by

In coupled LCG or CLCG [3], two LCGs are used and
their outputs are compared with each other. The output of
both LCGs are compared with each other. If the output of 1st
LCG is greater than second LCG, the resulting output is logic
one and else logic zero. The coupled LCG provides bit wise
output for the sequence generated by the LCG. The coupled
LCG generates output whenever both the LCGs generate
output. Hence, the bit output is generated at each clock cycle.
Zi = Bi if Ci = 0
This method gives better randomness as now two LCGs are
used to generate the sequence. However , the output bit is
not being generated in every clock cycle because output bit is
generated only when Ci = 0. Ci being random cannot be zero
always. As Ci is random , Ci occurs for approximately 2n−1
times and overall bit length of output is approximately
2n−1 .

xi+1 = a1 × xi + b1 mod2n . D. The modified dual-CLCG method

yi+1 = a2 × yi + b2 mod2n .
Bi = 1 if xi+1 > yi+1 and zero otherwise
Consider an example of CLCG bit generator where a1 =5,
b1 =5, a2 =5, b2 =3. Initial seed (x0 ,y0 ) be (2,7). Then, xi
obtained is (7,0,5,6,3,4,1,2) and yi obtained is (6,1,0,3,2,5,4,7).
Therefore, Bi obtained is (1,0,1,1,1,0,0,0)
This method is a simple modification of the previous
method. Here also, two dual CLCGs are used and their
outputs are undergone XOR operation to get the overall
output.
Zi = Bi XOR Ci
An example has been given to show the working of
this method. a1 =5, b1 =5, a2 =5, b2 =3, a3 =5, b3 =1, a4 =5,
b4 =7 and m=23 . Initial seeds be (X0 ,Y0 ,P0 ,Q0 ) = (2,7,3,4).
The sequences xi+1 , yi+1 , pi+1 and qi+1 obtained is given by
xi+1 = (7,0,5,6,3,4,1,2) pi+1 = (0,1,6,7,4,5,2,3)
yi+1 = (6,1,0,3,2,5,4,7) qi+1 = (3,6,5,0,7,2,1,4)
Bi = (1,0,1,1,1,0,0,0) Ci = (0,0,1,1,0,1,1,0)
Zi = (1,0,0,0,1,1,1,0)
1) Algorithm Explained: The algorithm for the proposed
method is given in figure 4. The first step involves the
initialization of all constant parameters a0 , a1 , a2 , a3 , b0 , b1 ,
b2 , b3 so that they satisfy the conditions in which the LCGs
obtain maximum period. Only for the conditions in which the
LCGs give maximum period, the overall sequence will give
maximum period. Next we need to give the input seeds x0 , y0 ,
p0 and q0 which is of n bits length. The output pattern depends
on the input parameters given and also the initial seed. In the
first iteration, the initial seeds are used as the input and in the
remaining iterations, the output of the final step is taken as
input of first step. This is controlled by a MUX being placed
at the start of the execution cycle. Now, the values of xi+1 ,
yi+1 , pi+1 and qi+1 are determined from the equations of the
dual-CLCG. From the values of xi+1 and yi+1 , the bit value
of Bi is obtained and similarly, from the values of pi+1 and
qi+1 the bit value of Ci is obtained. Now, finally, to obtain
the output, the bits Bi and Ci are done XOR with each other
to produce the final output Zi . This cycle repeats and for each
iteration, a particular output bit is obtained.
being selected and thereafter, output of previous iteration is
selected as input xi .
The multiplication operation of xi with 2r is done by shifting
xi r times towards left. This can be done with the help of
a left shifter where 0 is padded at the right hand side when
the sequence is moved left and MSB is being moved out
of the sequence each time a left shifting operation is being
performed. For example, the sequence 110011 when left
shifter gives 100110 where the MSB was moved out of the
sequence and a new 0 has been padded to the LSB.
The operation of the LCG xi+1 = 2r × xi + xi + b mod 2n is
done with the help of an adder and the overflowing bits are
neglected because we only need the remainder after dividing
with 2n . Consider the example mentioned above, where n
was 3 bits and 2n was 8. In order to divide 2r × xi + xi +
b with 8 and take the remainder, it is enough to do addition
of 2r × xi , xi and b and take the least significant 3 bits. i.e.,
we neglect the overflowing bits. This will give the remainder
after dividing with 8. Similarly, for any number of bits, it is
enough to consider the first n bits after addition to get the
remainder after dividing with 2n . The inputs 2r × xi , xi and
b are given as inputs to adder where each of them has n bits
and the output xi+1 also has n bits.
The comparator is used to compare the values of xi+1 and
yi+1 for 1st CLCG and that of pi+1 and qi+1 for 2nd CLCG.
The output of comparators are the bit sequences Bi and Ci
respectively. The registers are used before comparators so that
both the inputs of the comparator arrives at the same instant
and proper comparison can be made. The final element is an
XOR gate which performs bit wise XOR operation of the bit
streams Bi and Ci .

x0 Start Start y0 x0 Start Start y0

MUX MUX MUX MUX

xi << << yi xi << << yi

2r1*xi 2r2*yi 2r1*xi 2r2*yi

b1 b2 b1 b2

REG REG REG REG

xi+1 yi+1 xi+1 yi+1

CMP CMP

Zi

Fig. 5. Architecture of the proposed pseudorandom bit generator

Fig. 4. Algorithm of the proposed pseudorandom bit generator

2) Architecture: The architecture for the method proposed
is given in figure 5. The MUX is used for selecting from
previous output and the initial seed depending on the select
line start. In the beginning of the iteration, initial seed is
3) Comparator: The basic building block of the n-bit
comparator used is a 2-bit comparator. n-bit comparator is
made using a collection of 2-bit comparators. The logical
expression of the 2-bit comparator can be synthesized from
the truth table.
 ai+1 ai bi+1 bi Abig Bbig bn-1
an-1 Abig
2-bit 2-bit 2-bit 2-bit
bn-2
0 0 0 0 0 0 an-2 CMP CMP CMP CMP Bbig

0 0 0 1 0 1 bn-3
an-3
0 0 1 0 0 1 bn-4 2-bit
CMP
an-4
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 0 0
0 1 1 0 0 1
0 1 1 1 0 1 b7
a7
1 0 0 0 1 0 b6 2-bit 2-bit 2-bit
CMP CMP CMP
a6
1 0 0 1 1 0
b5
1 0 1 0 0 0 a5
2-bit
b4
1 0 1 1 0 1 a4 CMP

1 1 0 0 1 0 b3
a3
1 1 0 1 1 0 b2
2-bit 2-bit
CMP CMP
a2
1 1 1 0 1 0
b1
1 1 1 1 0 0 a1
2-bit
bo
CMP
a0
Table.1 Truth table of 2-bit comparator
Fig. 7. n-Bit Comparator
The overall expression of Abig and Bbig is obtained after
K-Map reduction.
0 0 0 0 0
Abig = a1 b1 + a1 b1 a0 b0 + a1 b1 a0 b0
0 0 0 0 0
Bbig = a1 b1 + a1 b1 a0 b0 + a1 b1 a0 b0 Carry save adder for addition of three n bit number has two
The gate level circuit of the expression for Abig and Bbig is parts.
shown in figure 6. The comparator gives an output Abig = 1
• n full adders in parallel. A bit of same weightage from
bi+1 each of the three input numbers is given to each full adder
Abig
stacked in parallel and the corresponding sum and carry
ai+1 of each full adder is passed to the second stage.
• The second stage is an n-1 bit ripple-carry adder which
bi receives sum and carry outputs from each of the full
Bbig adders stacked above.
ai
The detailed diagram of a carry save adder for computing
Fig. 6. 2-bit comparator addition of three four bit numbers is shown in figure 8. Unlike
a ripple carry adder, there is no carry chaining in carry save
and Bbig = 0 when 1st input number ’a’ is bigger than second adder. Carry Save Adder (CSA) eliminates the carry chaining
input number ’b’. The output is Abig = 0 and Bbig = 1 when by saving the carry and provides the carry to the next stage
b is greater than a. When both inputs have equal magnitude, of addition instead of adding it to the next higher bit adder.
then Abig = Bbig = 0. The output bit at each position is obtained by adding the
The formation of n bit comparator requires (n-1) 2-bit com- sum corresponding to that position with the carry obtained
parators - (n/2) 2-bit comparators in the first stage, (n/4) 2-bit from the previous position in the carry save stage with the
comparators in the second and goes on till we have a single overflow from the sum in the previous position in the ripple
two bit comparator in the last stage. i.e. 8-bit comparator carry stage. The area used for the carry save adder used for
requires 7 2-bit comparators. The detailed diagram is given n bit addition of three operands is given by:
in figure 7. The 2-bit comparators are connected such that A3C S A = (2n-1)AF A .
the one at the MSB is given the maximum priority. The
outputs of the 2-bit comparator from higher order bit in present Total area is contributed by n Full adders stacked in first
stage is being given at higher order input bits in the next stage. stage and (n-1) full adders used in second stage in ripple
This connection goes on till the final stage. This connection carry adder.
ensures proper comparison of n-bit numbers by giving more The critical path in the addition is obtained as nTF A
significance for the comparison of higher order bits. which is time taken to generate the MSB output bit, which
4) Carry save adder for 3 operand addition: Carry save is the delay of a single full adder in the first stage and (n-1)
adder is used to compute sum of three or more n-bit binary full adders in the ripple carry adder stage.
numbers. A carry save adder consists of a ladder of full adders.
 cn-1 bn-1 an-1 cn-2 bn-2 an-2 cn-3 bn-3 an-3 c 1 b1 a 1 c0 b0 a0

FA FA FA FA FA

FA FA FA FA 0

sn sn-1 s2 s1 s0

Fig. 8. Carry save adder

III. R ESULTS
IV. C ONCLUSION
Since Bi and Ci is produced in each and every cycles, Zi
will be produced in each cycles. This is the major advantage
of this method compared to the previous method, because in
previous method output bits were not being generated for every
clock cycle. The overall bit length of the sequence is also
increased from approximately 2n−1 to 2n . The overall bit
length is increased compared to the previous method because
output Zi is produced for all clock cycle no matter what the
value of bit Ci is. The overall latency of previous method was
2n−1 clock cycles while the clock latency of this method is
only of that of a single clock cycle.
R EFERENCES
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