Lab7 Intro

Extending Memory Space with BRAM

This material exempt per Department of Commerce license exception TSU

Introduction

The Zynq device supports different types of memory including volatile (e.g. DDR3)
and non-volatile (e.g. QSPI Flash).
There are hard controllers on the Zynq PS providing processor access to these
memories.
The PL portion of the Zynq device has plenty of Block RAM (BRAM) which can be
used by an IP without contending for external resources and creating performance
bottleneck.
This lab guides you through the process of extending the memory space in Zynq-
based platform using available PL based BRAM resource.

Lab7 - 2 © Copyright 2016 Xilinx

1
ARM Cortex-A9 based Embedded System Design
Extending Memory Space with BRAM

DDR3
Memory Memory AXI AXI4
AXI3 Interconnect
Controller M_AXI_GP1 AXI-BRAM Controller BRAM
Block

RS232 UART
PL
ARM
LED
GPIO Cortex-A9
LD9

AXI3 AXI
PS M_AXI_GP0 Interconnect
Block
AXI4-Lite
GPIO LEDs

AXI4-Lite
GPIO Switches

BTN

Lab7 - 3 © Copyright 2016 Xilinx

Procedure

Open the project

Configure the processor to enable M_AXI_GP1 interface
Extend with BRAM
Create wrapper and generate the bitstream
Generate applications in the SDK
Test in hardware

Lab7 - 4 © Copyright 2016 Xilinx

2
Summary

This lab led you through adding BRAM memory in the PL section thereby extending
the total memory space available to the PS.
You verified the functionality by creating an application, targeting the added BRAM,
and executing the application from the added memory.

Lab7 - 5 © Copyright 2016 Xilinx