Lab4 Intro

Creating and Adding Custom IP in PL

Zynq
Vivado 2015.2 Version

This material exempt per Department of Commerce license exception TSU © Copyright 2015 Xilinx
Introduction

This lab guides you through the process of creating and adding a custom IP. You will
create the custom IP using the Manage IP feature of Vivado. Then you will add the
created IP in the hardware design in IP Integrator. You will create a software project in
XSDK and develop a software that will monitor dip switches and write to the LED_IP
device to which LEDs are connected. You will learn the process of writing a basic
software application.

Lab4 Intro 21a- 2 © Copyright 2015 Xilinx

Creating and Adding Custom IP

DDR3 PL
Memory Memory
Controller

RS232 UART

ARM
Cortex-A9

AXI4-Lite
AXI LED_IP LED
AXI3
M_AXI_GP0 Interconnect
Block AXI4-Lite
GPIO Push-Buttons

AXI4-Lite
PS GPIO DIP Switches

Lab4 Intro 21a- 3 © Copyright 2015 Xilinx

Procedure

Open the project in Vivado

Create a Custom IP using Manage IP feature of the Vivado tools
Modify the created IP to include the peripheral functionality
Add the created peripheral into the existing system
Export the design to SDK
Define a device driver interface for each of the peripherals and the processor
Use SDK to define, develop, and integrate the software components of the embedded
system

Lab4 Intro 21a- 4 © Copyright 2015 Xilinx

Summary

Manage IP feature was used to create an AXI4Lite IP. The created IP was modified to
add the desired functionality. Vivado IP packager was used to update the IP and then
the custom IP block was imported into the IP library. The IP block was then added to the
system. Connection automation was run, where available, to speed up the design of the
system by allowing Vivado to automatically make connections between IP. Pin location
constraints were added to the design. The design bitstream was generated.
SDK was used to define, develop, and integrate the software components of the
embedded system. The device driver was assigned to the custom IP. The peripheral-
specific functional software was created and the executable file was generated.

Lab4 Intro 21a- 5 © Copyright 2015 Xilinx