Tanner Manual - Hyd

VLSI LAB Using Tanner Tool
Trident Techlabs Pvt Ltd,

FNo.304, 3-6-369/2, Sanathana Estacy,
Himayath Nagar, Hyderabad.
Ph:+91-40-27632958
Fax:+91-40-27624893
Trident Techlabs
Trident Techlabs Pvt Ltd, headquartered at New Delhi is specialist large sized company, providing
independent Software and Hardware solution to entire Academics.
As you aware, Trident Techlabs Pvt Ltd (ISO 9001:2008) are the academic partner for companies
including Tanner EDA, Mentor Graphics, National Instruments USA and promotes their products for past
10 Years and set up many research labs across the country and also we support all colleges, universities
& research institutes to get the funds from AICTE, DST, TEQUIP, UGC and MHRD for their modernization
of lab and for college revenue generation.
Apart, We are also Indian partners to various software principles who are also part of Anna University –
Coimbatore Syllabus as mentioned below in the tabular column (Like Tanner, Mentor, PTC, Sprut CAM,
Simulation X - CAE, Tata Technologies, PSIM, Power World, Cyme, Techmo, Techtran, Cross Light etc...).
Techlab helps in setting up various research labs of various foreign principles through technical Support,
conducting workshops, building laboratories, revenue generation schemes etc., with your esteemed
institution. This will make students to mould for the Industrial standards.
Trident Techlabs Pvt Ltd is a one source company which offers software & hardware solutions to various
engineering disciplines as per syllabus & research activities.
Tanner EDA Software Tools - Driving Innovation for Analog IC, Mixed Signal,& MEMS
Design
Tanner EDA provides a complete line of software solutions that catalyze innovation for the
design, layout and verification of analog and mixed-signal (A/MS) integrated circuits ( ICs).
Customers are creating breakthrough applications in areas such as power management, displays
and imaging, automotive, consumer electronics, life sciences, and RF devices.
A low learning curve, high interoperability, and a powerful user interface improve design team
productivity and enable a low total cost of ownership (TCO). Capability and performance are
matched by low support requirements and high support capability as well as an ecosystem of
partners that bring advanced capabilities to A/MS designs.
Founded in 1988, Tanner EDA solutions deliver the right mixture of features, functionality and
usability. The company has shipped over 33,000 licenses of its software to more than 5,000
customers in 67 countries.
Tanner EDA provides powerful and most flexible s tool that is available in the market for
design, layout and verification of analog, mixed-signal, RF and MEMS ICs. It consists of fully-
integrated front end and back end tools, from schematic capture, cir cuit simulation, and
waveform probing to physical layout and verification. Its advanced features improve designer
productivity, including foundry-compatible physical verification, Verilog-A simulation,
interactive auto-routing, and device layout automation.
Different Modules in tanner
1. S-Edit
2. TSpice
3. WEdit
4. LEDIT
5. LVS
S-Edit
S-Edit™ is an easy-to-use PC-based design environment for schematic capture. It gives

you the power you need to handle your most complex full custom IC design capture. S-Edit is
tightly integrated with Tanner EDA s T-Spice™ simulation, L-Edit™ layout, and HiPer™
verification tools.
S-Edit helps you meet the demands of today s fast-paced market by optimizing your
productivity and speeding your concepts to silicon. Its efficient design capture process integrates
easily with third-party tools. S-Edit enables you to explore design choices and provides an easy-
to-use view into the consequences of those choices. A faster design cycle gives you more
flexibility in moving to an optimal solution freeing up more time and resources for process
corner validation. The results are less risk downstream, higher yield, and quicker time to market.
Features of S-Edit
• S-Edit brings to front- end design capture the ease-of-use and design productivity for which
Tanner Tools™ are known.
• Bus support speeds the creation of mixed signal designs.
• Advanced array support enables easy creation and editing of memory, imaging, or circuits
with repetitive blocks.
• Rubberband connectivity editing enables faster design modifications.
• S-Edit displays evaluated parameters in real time over the course of the design process.
Parameters with formulas based on other circuit parameters can be displayed or evaluated.
• Auto symbol generation enables you to easily create symbols from schematics, and synchronize
any changes.
• Recordable scripts enable you to automate tasks or expand the tool for application-specific
needs.
• Replayable logs permit recovery if ther e is an unexpected network or hardware failure.
• S-Edit performs net highlighting and keeps the net highlighted as you move through the
hierarchy.
• Cross probe from SPICE netlists and LVS to highlighting nets or devices.
• Schematic ERC enables you to check your design for common errors such as undriven nets,
unconnected pins and multiple output pins connected together. The design checks are
fully configurable, including custom validation scripts.
• Netlists can be exported in flexible, user-configurable formats, including SPICE and CDL
variants, EDIF, structural Verilog, and structur al VHDL.
• Library support in S-Edit maximizes the reuse of IP developed in previous projects.
• CAD managers can control distribution and access rights to the technology or design. The
format allows revision control systems to manage revisions over the course of the design
process.
T-Spice
Tanner T-Spice™ Circuit Simulator puts you in control of simulation jobs with an easy-
to-use graphical interface and a faster, more intuitive design environment. With key features
such as multi-threading support, device state plotting, real-time waveform viewing and analysis,
and a command wizard for simpler SPICE syntax creation, T-Spice saves you time and money
during the simulation phase of your design flow. T-Spice enables more accurate simulations by
supporting the latest transistor models including BSIM4 and the Penn State Philips (PSP)
model.
T-Spice provides extensive support of behavioral models using Verilog-A, expression
controlled sources, and table-mode simulation. Behavioral models give you the flexibility to
create customized models of virtually any device. T-Spice also supports the latest industry
models, including the transistor model recently selected as the next standard for simulating future
CMOS transistors manufactured at 65 nanometers and below the Penn State Philips (PSP)
model. PSP will simplify the exchange of chip design information and support more accurate
digital, analog, and mixed-signal circuit behavior analysis.
Features of Tspice:
T-Spice helps integrate your design flow from schematic capture through
simulation and waveform viewing. An easy-to-use point-and-click environment gives you
complete control over the simulation process for gr eater efficiency and productivity.
• Enables easy creation of syntax-correct SPICE through a command wizard.
• Highlights SPICE Syntax through a text editor.
• Provides Fast, Accurate, and Precise options to enable optimal balance of accuracy and
performance.
• Enables you to link from syntax errors to the SPICE deck by double clicking.
• Supports Verilog- A for analog behavioral modeling, allowing designers to prove system level
designs before doing full device level design.
• Provides “.alter” command for easy what-if simulations with netlist changes.
Perform sophisticated analysis mentioned below:
T-Spice uses superior numerical techniques to achieve convergence for circuits that are often
impossible to simulate with other SPICE programs. The types of circuit analysis it performs
include:
DC and AC analysis.
Transient analysis with Gear or trapezoidal integration.
Enhanced noise analysis.
Monte Carlo analysis over unlimited variables and trials.
Virtual measurements with functions for timing, error, and statistical analysis.
Parameter sweeping using linear, log, discrete value, or external file data sweeps.
Optimize designs with variables and multiple constraints by applying a Levenberg-
Marquardt non-linear optimizer.
Use plot statements that support wildcards.
Use plot statements and parameter definitions that support mathematical expressions
involving C-style math functions.
Use bit and bus logic waveform inputs.
W-Edit
W-Edit is a waveform viewer that provides ease of use, power and speed with a flexible
user interface so you can visualize the complex numerical data resulting from circuit simulation.
In addition, W-Edit provides saved work spaces, scriptable graph construction and trace
calculation, and easy-to-export presentation-quality graphics.
As part of the Tanner EDA tool flow, W-Edit is optimized to display the full performance
and capacity of the T-Spice cir cuit simulator and all advanced functionality in the S-Edit
schematic editor. You can chart data generated by T-Spice and S-Edit directly without
modification of the output data files, with dynamic display updates produced during simulation.
Features of W-Edit
Analysis Platform W-Edit is not only a waveform viewer, but is an analysis platform
featuringbuilt in measurements that can be applied to selected traces. These include
amax, amin, amplitude,average, baseline, compar e, cross, delay, derivative, edge
threshold, error, fall-time, frequency,integral, intersect, maximum, minimum, next-edge,
next-extreme, next-point, overshoot, period,previous-extreme, previous-point, pulse-
width, rise-time, rms, slew-rate, smooth, top-line, undershoot, window, xval, ymax, ymin,
and yval.
Arithmetic Traces W-Edit supports the ability to create new traces from arithmetic
expressions of other traces, using a calculator-style wizard for arguments and syntax.
Newly created arithmetic traces can be saved in the W-Edit chartbook.
Multiple Simulations W-Edit supports concurrent simulation and curve viewing so the
results of multiple simulations can be plotted together for comparison and measurements.
You can load and view multiple simulations from different output files, in one or more
chart windows, and traces can be copied between charts.
Programmable W-Edit is fully programmable with TCL so you can write scripts to
automate, for example, results analysis, trace depiction or complex number arithmetic.
Performance W-Edit performance capability is increased to handle the largest data files
quickly and efficiently. The Trace navigator can display traces in a flat or hierarchical
view, with filters that include wildcards and regular expressions.
Chartbooks All configuration aspects of a chart, as well arithmetic traces, can be saved
to a chartbook for later display and analysis.
Intuitive User Interface All Tanner applications present a clear and intuitive
Windows®1 interface that is easy to learn and use. In W-Edit this includes the a drag-
and-drop feature for placing traces in a chart, full control over curve display aspect such
as color, line weight, visibility or scaling, and multiple cursor types with built-in
measurements.
L-Edit
In today s analog design world, speed is more important than ever. To compete in a high-
efficiency, high-productivity marketplace, you need a toolset that has proven its ability to
accelerate the design cycles of commercially successful projects. Tanner EDA s L-Edit™ meets
your needs by combining the fastest rendering available with powerful features that exceed the
needs of the most demanding user. This leading analog/ mixed signal IC design tool for the PC
platform enables you to get started with minimal training. You can draw and edit quickly, with
fewer keystrokes and mouse clicks than other layout tools.
Using powerful features such as interactive DRC, object snapping, and alignment, you
can work more efficiently to save time and money. Save time by using foundry-provided files
directly, allowing you to avoid having to set up technology information manually. Once you ve
begun using L-Edit, the CAD support burden for your physical design tools will be reduced,
enabling you to focus on other mission critical tasks.
Features of Ledit
Perform complete hierarchical physical layout with all-angle and curved polygons on an
unlimited number of layers.Use orthogonal, 45°, all-angle, and curved drawing modes.
Use a command line interface for run-time automation.
L-Edit DRC features include:

Support for an unlimited number of width, spacing, surround, enclose, extension, overlap,
not exist, and density rules.
High performance all-angle Boolean and Select layer generation.
Flag offgrid vertices, self-intersecting polygons, all-angle edges, and polygons with more
than a specific number of vertices.
Full chip and local region DRC
Seamless integration into the layout environment using the DRC Error Navigator.
You can extract the most common device parameters, including MOSFET width, length,
source/drain area, and perimeter. Areas of diodes, BJTs, MESFETs, and JFETs.
Subcircuit extraction for functional blocks with user parameters.
See the DRC status (pass/fail/needed) of each cell.
Integrated Verification Error Navigator allows you to:
• Navigate instantly down the hierarchy to locate er rors.
• View errors grouped by rule or by cell.
• See rule distance and actual violation distance.
• View errors in the top cell or in the cell where the error occurred.
• Mark or remove errors that have been fixed.
L-Edit schematic driven layout (SDL) provides capabilities that enable you to:
o Read in a netlist and automatically generate parameterized cells and instance them
into your design.
o Display flylines allowing you to place your blocks to minimize routing
congestion.
Navigate efficiently
Efficiently traverse design hierar chy with top-down and bottom-up hierarchical view,
non-instanced cells view, or view cells sorted by their modified date.
Drag and drop cells into layout from library files, other design files, or the current design
database.
View layout details down to any level of the hierarchy.
Lock and unlock cells to protect the design from any changes.
Easily replace instances of one cell with another cell, at the current level or throughout
the design.
Maximize IP reuse or partition your design for multiple designers with L-Edit s multiple
library support (XrefCells).
Layout Vs schematic (LVS)
L-Edit layout versus schematic (LVS) accurately and efficiently compares two SPICE netlists to
determine whether they contain equivalent circuit descriptions. LVS can use topological
information, parametric values, and geometric values to compare netlists according to your
specifications. The program quickly traces element and node mismatches back to their origins,
pinpointing irresolvable nodes and devices using fragmented class reporting.
LVS offers a full range of pre-processing options to optimize netlists for comparison, including:
• Merging of parallel or series devices, where options can be set independently for different
device types and for specific device models.
• Elimination of shorted and disconnected (open) devices.
• Elimination of parasitic resistors and capacitors that exceed user-supplied
min/max thresholds.
• Removal of user-specified device models so that the nodes spanned by their terminals can be
shorted or opened.
• Omission of user-selected device parameters from the compared netlists.
• Checking for soft-connections.
• Supporting asymmetrical MOSFETs with user-defined pin swapping.
• Matching device parameter values, which are crucial for analog design.
• Specif ying pre- and post-iteration matches to speed the comparison process.
LVS reads netlist files in T-Spice, HSPICE, PSpice, or CDL formats, with support for all device
types and key parameters. Input netlists do not need matching formats or hierarchy to be
compared. LVS supports length and width parameters, with accompanying model definitions, in
capacitor (C) and resistor (R) device statements. Zip through LVS with cross-probing from
SPICE and LVS results to layout or schematic and with enhanced navigation of SPICE files.
INVERTER SCHEMATIC
Open S-Edit and choose file New Design. A window pops up.
Give a design name and location where the project has to be saved.
In the Library window click on ADD button Library files can be found at following path:
My Documents\Tanner EDA\Tanner Tools v13.0\Libraries\All\All.tanner.
if it is not found goto help and choose setup examples and tutorials option and follow the procedure.
Goto cell and choose new cell. And complete the circuit.
Goto setup tab and choose spice simulation.
Choose general and library .
Lib file can be found at
My Documents\Tanner EDA\Tanner Tools v15.1\ Process\ Generic_250nm\ Generic_250nm_Tech\

Generic_250nm.lib.
After this add tt. So it looks like
My Documents\Tanner EDA\Tanner Tools v15.1\ Process\ Generic_250nm\ Generic_250nm_Tech\

Generic_250nm.lib tt
Choose transient analysis and give parameters.
Goto tools and click on start simulation

Tspice pops up automatically and it is followed by waveform editor.
Simulation Report:
T-Spice - Tanner SPICE
Version 15.10
Standalone hardware lock
Product Release ID: T-Spice Win32 15.10.20101227.10:43:55
Copyright © 1988-2010 Tanner EDA
Parsing "C:\DOCUME~1\ramesh\LOCALS~1\Temp\Cell0.sp"
Reading library entry "tt" from "C:\Documents and Settings\ramesh\My Documents\Tanner

EDA\Tanner Tools v15.1\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib"
Reading library entry "GEN" from "C:\Documents and Settings\ramesh\My Documents\Tanner

Reading library entry "RES_CAP_GEN" from "C:\Documents and Settings\ramesh\My
Documents\Tanner EDA\Tanner Tools
v15.1\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib"
Reading library entry "RES_CAP_TYP" from "C:\Documents and Settings\ramesh\My

Reading library entry "SIM_SUBCIRCUITS" from "C:\Documents and Settings\ramesh\My

Reading library entry "RES_CAP_SUBCIRCUITS" from "C:\Documents and Settings\ramesh\My

Reading library entry "TT_NMOS_PARAMETERS" from "C:\Documents and Settings\ramesh\My

Reading library entry "TT_PMOS_PARAMETERS" from "C:\Documents and Settings\ramesh\My

Reading library entry "MOS_MODEL" from "C: \Documents and Settings\ramesh\My

Loaded BSIM3v33 model library, Berkeley BSIM3 v3.3.0
Loaded BSIM3v31 model library, Berkeley BSIM3 VERSION 3.1 with extensions
Opening simulation database "C:\DOCUME~1\ramesh\LOCALS~1\Temp\Cell0.tsim"
General options:
threads = 1
Device and node counts:

MOSFETs - 2
MOSFET geometries - 2
Voltage sources - 2
Subcircuits - 0
Model Definitions - 5
Computed Models - 2
Independent nodes - 1
Boundary nodes - 3
Total nodes - 4
Parsing 0.27 seconds
Setup 0.89 seconds
DC operating point 0.02 seconds
Transient Analysis 0.83 seconds
Overhead 2.20 seconds
-----------------------------------------
Total 4.20 seconds
Simulation completed
To view spice netlist of the circuit click on file-> export spice.

In Export window browse the location where the netlist has to be saved and click export.
Netlist opens in T spice as below.
Following is the netlist we have for the inverter.
********* Simulation Settings - General Section *********
.lib "C:\Documents and Settings\ramesh\My Documents\Tanner EDA\Tanner Tools

+ tt
*-------- Devices With SPICE.ORDER > 0.0 --------
***** Top Level *****
MMn1 Out In Gnd 0 NMOS25 W=1.5u L=250n M=1 AS=975f PS=4.3u AD=975f PD=4.3u $ $x=7093
+$y=2300 $w=414 $h=600
MMp1 Out In Vdd Vdd PMOS25 W=1.5u L=250n M=1 AS=975f PS=4.3u AD=975f PD=4.3u $
+$x=7093 $y=3100 $w=414 $h=600

VVoltageSource_1 Vdd Gnd DC 5 $ $x=4900 $y=2900 $w=400 $h=600
VVoltageSource_2 In Gnd PULSE(0 5 0 5n 5n 95n 200n) $ $x=6600 $y=2200 $w=400 $h=600
.PRINT TRAN V(In) $ $x=5950 $y=2850 $w=1500 $h=300 $r=180
.PRINT TRAN V(Out) $ $x=8350 $y=2550 $w=1500 $h=300
********* Simulation Settings - Analysis Section *********
.tran 5n 1u start=0
********* Simulation Settings - Additional SPICE Commands *********
.end
INVERTER LAYOUT
Given Below is the step by step for drawing an Inverter Layout.
Goto start->All programs->Tanner EDA->Tanner tools v15.xx-> LEDIT v15.xx 32 bit.
LEdit opens as below. In L-Edit Click on file->new. A window pops up

In this window layout is highlighted and there is a browse button. Click on it. And browse to the
following path.
“My Documents\Tanner EDA\Tanner Tools v15.1\ Process\ Generic_250nm\ Generic_250nm_Tech\

Generic_250nm_TechSetup.tdb” and click ok.
Use + and – keys in num pad to zoom in and zoom out.
Tap twice on + key to have the grids visible.
Goto -> view->display->Major grids. Now major grids will be visible.
Goto -> setup->design
A window with design parameters will pop up.
Click on grid button and we get to see the distance between the 2 grid points as 0.250 Microns.
In this manual the distance between 2 grid points is called as lambda for our convenience.
First draw an active contact and click on the square box and draw a square for 1x1 lambda.
Click on metal and choose square box . Metal around any contact is 3x3 lambda.
Red Poly 1X X. Spacing between Poly & contact is 1 Lambda.
Place 2 other metal and contact combination near poly as below.
Distance between 2 (metal and contact) combination is 3 lambda.
Active region should cover metal region by 1 Lambda as shown above.

Pselect should cover metal, poly, metal combination by 1 lambda as below. Pselect defines the
transistor as pmos.
n-select to coveractive region by 11 lambda as below.
Pmos is grown in n-well. Distance between (p/nselect or p/n implant) is 3 lambda.

Pmos is now completed. Run DRC to check for any error
Rectify the errors and clear DRC.
Errors poly density error and metal density errors can be ignored.
For Creating Nmos Copy & paste Pmos
Change p-implant/select to n-implant/select and vice versa.
Procedure for changing p-select to n-select is giv en below.
Click on the border of Pselect (goto Edit Tab-> Edit objects-> Change to Nselect in the Drop down
menu.)
Now We have our Nmos.
Complete the connections and label the ports using Switch to drawing port which looks like A.
Run DRC once again to check for any error.
For extraction goto tools-> extract setup and make a tick on Generic_250.ext. go to options and uncheck
anything under hyper verify option.
Now click on extract button to get the netlist for the layout. The following is the extracted netlist
********************************************************************************
* SPICE netlist generated by HiPer Verify's NetList Extractor
* Extract Date/Time: Mon Apr 04 17:52:49 2011
* L-Edit Version: L-Edit Win32 15.10.20101227.13:21:06
* Rule Set Name:
* TDB File Name: C:\Documents and Settings\ramesh\My Documents\Tanner

EDA\Work\10bit\INVERTER.tdb
* Command File: C:\Documents and Settings\ramesh\My Documents\Tanner EDA\Tanner

Tools v15.1\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.ext
* Cell Name: Cell0
* Write Flat: NO
********************************************************************************
****************************************
M1 Out In Gnd Gnd NMOS25 l=2.75e-007 w=1.2e-006 ad=1.44e-012 as=1.56e-012 pd=4.8e-006 ps=5e-
006 $ (13.25 16.775 13.525 17.975)
M2 Out In Vdd Vdd PMOS25 l=2.75e-007 w=1.2e-006 ad=1.47e-012 as=1.53e-012 pd=4.85e-006

ps=4.95e-006 $ (13.25 21.825 13.525 23.025)
* Top level device count
* M(NMOS25) 1
* M(PMOS25) 1
* Number of devices: 2
* Number of nodes: 4
In the above extraction we have spice code for pmos and nmos. Open the netlist in tspice and click on
insert command icon
Expand files icon and click on library and browse to generic 250.lib the path is as below
“My Documents\Tanner EDA\Tanner Tools v15.1\ Process\ Generic_250nm\ Generic_250nm_Tech\

Generic_250nm.lib”
In library section give “tt” and click on insert command to insert the command in tspice.
Similarly inser the following command using insert command options or copy them from schematic
netlist.
.tran 5n 1u start=0
.end
Final netlist is as below.
* SPICE netlist generated by HiPer Verify's NetList Extractor
* Extract Date/Time: Mon Apr 04 17:52:49 2011
* L-Edit Version: L-Edit Win32 15.10.20101227.13:21:06
* Rule Set Name:
* TDB File Name: C:\Documents and Settings\ramesh\My Documents\Tanner

EDA\Work\10bit\INVERTER.tdb
* Command File: C:\Documents and Settings\ramesh\My Documents\Tanner EDA\Tanner

Tools v15.1\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.ext
* Cell Name: Cell0
* Write Flat: NO

v15.1\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" tt
****************************************
M1 Out In Gnd Gnd NMOS25 l=2.75e-007 w=1.2e-006 ad=1.44e-012 as=1.56e-012 pd=4.8e-006 ps=5e-
006 $ (13.25 16.775 13.525 17.975)
M2 Out In Vdd Vdd PMOS25 l=2.75e-007 w=1.2e-006 ad=1.47e-012 as=1.53e-012 pd=4.85e-006

ps=4.95e-006 $ (13.25 21.825 13.525 23.025)
.tran 5n 1u start=0
.end
* Top level device count
* M(NMOS25) 1
* M(PMOS25) 1
* Number of devices: 2
* Number of nodes: 4
Click on run simulation button to get the post extraction simulation
The following is the Simulation report

Version 15.10
Parsing "C:\DOCUME~1\ramesh\MYDOCU~1\TANNER~1\Work\iNVERTER\INV250.spc"
Reading library entry "tt" from "C:\Documents and Settings\ramesh\My Documents\Tanner

Reading library entry "GEN" from "C:\Documents and Settings\ramesh\My Documents\Tanner

Reading library entry "RES_CAP_GEN" from "C:\Documents and Settings\ramesh\My

Reading library entry "RES_CAP_TYP" from "C:\Documents and Settings\ramesh\My

Reading library entry "SIM_SUBCIRCUITS" from "C:\Documents and Settings\ramesh\My

Reading library entry "RES_CAP_SUBCIRCUITS" from "C:\Documents and Settings\ramesh\My

Reading library entry "TT_NMOS_PARAMETERS" from "C:\Documents and Settings\ramesh\My

Reading library entry "TT_PMOS_PARAMETERS" from "C:\Documents and Settings\ramesh\My

Reading library entry "MOS_MODEL" from "C: \Documents and Settings\ramesh\My
Opening simulation database

"C:\DOCUME~1\ramesh\MYDOCU~1\TANNER~1\Work\iNVERTER\INV250.tsim"
General options:
threads = 1
MOSFETs - 2
Voltage sources - 2
Subcircuits - 0
Computed Models - 2
Boundary nodes - 3
Total nodes - 4
Setup 0.09 seconds

-----------------------------------------
Total 5.19 seconds
And the output wave form is

CMOS Differential Amplifier.
Complete the circuit as below
1. Take 2 pmos and 3 nmos and complete the circuit as shown in the diagram.
2. Use 4 power supply to complete the diagram.
3. To get AC power source follow the below steps.
Click on a dc power supply.
On the right side there is property window.
There choose masterinterface and and choose ac.
From spice commnd library click on print voltage -> instance .
Now instance window pops up.
Goto interface column choose ac phase and place it on output port. choose ac
magnitude in db .
Choose ac gain and ac_measure_gain product bandwidth and connect them to output
port.
The simulation setup is as below
After completing ckt diagram goto setup -> spice simulation.
Choose ac analysis and give the following values .
Start frequency =10
Stop frequency=10meg
No of frequency=25
Sweep type = dec.
Click on general type and give path to Generic_250nm.lib.
And run simulation to get output.
For differential mode choose one of the ac source and change the phase to 180 in the property window.
Spice Code
.lib "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools

*-------- Devices With SPICE.ORDER == 0.0 --------
***** Top Level *****
MNMOS_2_5v_1 N_1 In1 N_2 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=2693
$y=2800 $w=414 $h=600
MNMOS_2_5v_2 Out In2 N_2 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5707
$y=2800 $w=414 $h=600 $m
MNMOS_2_5v_3 N_2 bias Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $
$x=3993 $y=1600 $w=414 $h=600
MPMOS_2_5v_1 N_1 N_1 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=3107 $y=4400 $w=414 $h=600 $m
MPMOS_2_5v_2 Out N_1 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=5293 $y=4400 $w=414 $h=600
VVoltageSource_2 bias Gnd DC 700m $ $x=3400 $y=1100 $w=400 $h=600
VVoltageSource_3 In1 Gnd DC 0 AC 1 0 $ $x=1800 $y=2400 $w=400 $h=600
.PRINT AC Vdb(Out) $ $x=7250 $y=3650 $w=1500 $h=300
.PRINT AC Vp(Out) $ $x=5550 $y=3950 $w=1500 $h=300 $r=180
.MEASURE AC AC_Measure_Gain_1 MAX vdb(Out) ON $ $x=7950 $y=4400 $w=1500 $h=200
.MEASURE AC AC_Measure_GainBandwidthProduct_1_Gain MAX vdb(Out) OFF
.MEASURE AC AC_Measure_GainBandwidthProduct_1_UGFreq WHEN Vdb(Out)=0 OFF
.MEASURE AC AC_Measure_GainBandwidthProduct_1
PARAM='AC_Measure_GainBandwidthProduct_1_Gain*AC_Measure_GainBandwidthProduct_1_UGFre
q' ON $ $x=7850 $y=3100 $w=1500 $h=200
.ac dec 25 10 10X
.end
Then simulate the design
Version 15.02

Parsing "C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\Cell0.sp"
Reading library entry "tt" from "C:\Documents and Settings\Administrator\My

Reading library entry "TT_NMOS_PARAMETERS" from "Generic_250nm.lib"
Reading library entry "TT_PMOS_PARAMETERS" from "Generic_250nm.lib"
Reading library entry "MOS_BIN_MODEL" from "Generic_250nm.lib"
Reading library entry "Typ" from "Generic_250nm.lib"
Reading library entry "RES_CAP" from "Generic_250nm.lib"
Opening simulation database "C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\Cell0.tsim"
General options:
threads = 2
MOSFETs - 5 MOSFET geometries - 2
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0
Inductors - 0 Mutual inductors - 0

Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 4 Current sources - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V-control switch - 0 I-control switch - 0
Macro devices - 0 Verilog-A devices - 0
Subcircuits - 0 Subcircuit instances - 0
Model Definitions - 2 Computed Models - 2
Independent nodes - 3 Boundary nodes - 5
Total nodes - 8
Measurement result summary
AC_Measure_Gain_1 = 1.7293
At = 10.0000k
AC_Measure_GainBandwidthProduct_1 = 3.5177k
Setup 0.01 seconds
AC Analysis 0.30 seconds
-----------------------------------------
Total 3.06 seconds

The output waveform
For Differential Mode change the phase of a source by 180

Spice simulation
.lib "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools

*-------- Devices With SPICE.ORDER == 0.0 --------
***** Top Level *****
MNMOS_2_5v_1 N_1 In1 N_2 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=2693
$y=2800 $w=414 $h=600
MNMOS_2_5v_2 Out In2 N_2 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5707
$y=2800 $w=414 $h=600 $m
MNMOS_2_5v_3 N_2 bias Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $
$x=3993 $y=1600 $w=414 $h=600
MPMOS_2_5v_1 N_1 N_1 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=3107 $y=4400 $w=414 $h=600 $m
MPMOS_2_5v_2 Out N_1 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=5293 $y=4400 $w=414 $h=600
VVoltageSource_2 bias Gnd DC 700m $ $x=3400 $y=1100 $w=400 $h=600
.PRINT AC Vdb(Out) $ $x=7250 $y=3650 $w=1500 $h=300
.PRINT AC Vp(Out) $ $x=5550 $y=3950 $w=1500 $h=300 $r=180
.MEASURE AC AC_Measure_Gain_1 MAX vdb(Out) ON $ $x=7950 $y=4400 $w=1500 $h=200
.MEASURE AC AC_Measure_GainBandwidthProduct_1_Gain MAX vdb(Out) OFF
.MEASURE AC AC_Measure_GainBandwidthProduct_1_UGFreq WHEN Vdb(Out)=0 OFF
.MEASURE AC AC_Measure_GainBandwidthProduct_1
PARAM='AC_Measure_GainBandwidthProduct_1_Gain*AC_Measure_GainBandwidthProduct_1_UGFre
q' ON $ $x=7850 $y=3100 $w=1500 $h=200
.ac dec 25 10 10X
.end
The simulation Report
Version 15.02

Parsing "C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\Cell0.sp"
Reading library entry "tt" from "C:\Documents and Settings\Administrator\My

Reading library entry "TT_NMOS_PARAMETERS" from "Generic_250nm.lib"
Reading library entry "TT_PMOS_PARAMETERS" from "Generic_250nm.lib"
Reading library entry "MOS_BIN_MODEL" from "Generic_250nm.lib"
Reading library entry "Typ" from "Generic_250nm.lib"
Reading library entry "RES_CAP" from "Generic_250nm.lib"
Opening simulation database "C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\Cell0.tsim"
General options:
threads = 2
MOSFETs - 5 MOSFET geometries - 2
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0
Inductors - 0 Mutual inductors - 0

Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 4 Current sources - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V-control switch - 0 I-control switch - 0
Macro devices - 0 Verilog-A devices - 0
Subcircuits - 0 Subcircuit instances - 0
Model Definitions - 2 Computed Models - 2
Independent nodes - 3 Boundary nodes - 5
Total nodes - 8
Measurement result summary
AC_Measure_Gain_1 = 27.3656
At = 10.0000
AC_Measure_GainBandwidthProduct_1 = 1.6359X
Setup 0.03 seconds
AC Analysis 0.25 seconds
-----------------------------------------
Total 2.98 seconds

CMRR = Diff Mode/Common Mode
=27.3656/1.7293
=15.8246
10 Bit number controlled oscillator
Following the procedure discussed under inverter schematic complete the following diagram in
sedit.
Simulation Setup
Simulation report
Version 15.10
Parsing "C:\DOCUME~1\ramesh\LOCALS~1\Temp\Cell0.sp"
Reading library entr y "tt" from "C:\Documents and Settings\ramesh\My
Reading library entr y "GEN" from "C:\Documents and Settings\ramesh\My
Reading library entr y "RES_CAP_GEN" from "C:\Documents and Settings\ramesh\My
Reading library entr y "RES_CAP_TYP" from "C:\Documents and Settings\ramesh\My
Reading library entr y "SIM_SUBCIRCUITS" from "C:\Documents and
Settings\ramesh\My Documents\Tanner EDA\Tanner Tools
Reading library entr y "RES_CAP_SUBCIRCUITS" from "C:\Documents and
Reading library entr y "TT_NMOS_PARAMETERS" from "C:\Documents and
Reading library entr y "TT_PMOS_PARAMETERS" from "C:\Documents and
Reading library entr y "MOS_MODEL" from "C:\Documents and Settings\ramesh\My
Opening simulation database "C:\DOCUME~1\ramesh\LOCALS~1\Temp\Cell0.tsim"

Warning : Node D1 is only attached to FET gate terminals; voltage is undefined
Warning : Disabling printout of duplicate warning messages.

: Use '.options maxmsg=0' to view all warnings,
: or increase maxmsg from 5 to view more messages.
General options:
threads = 1

MOSFETs - 24
Voltage sources - 2
Subcircuits - 0
Computed Models - 2
Boundary nodes - 3
Total nodes - 16
*** 6 WARNING MESSAGES GENERATED DURING SETUP
Warning : Newton solver has failed due to extremely large node voltages.
: If the circuit has very high gain and extremely large voltages (>1000V) are expected,
: then you may use '.option vmax=0' to disable this check.
Conventional DC operating point computation failed.
Gmin stepping succeeded
Final gmin value = 1e-012, dcstep = 0

Setup 0.58 seconds
-----------------------------------------
Total 4.36 seconds
Simulation completed with 7 Warnings

Spice Code
* SPICE export by: S-Edit 15.10
* Export time: Mon Apr 04 18:31:33 2011
* Design: 10 bit
* Cell: Cell0
* Interface: view0
* View: view0
* View type: connectivity
* Export as: top-level cell
* Export mode: hierarchical
* Exclude empty cells: yes
* Exclude .model: no
* Exclude .end: no
* Exclude simulator commands: no
* Expand paths: yes
* Wrap lines: no
* Root path: C:\Documents and Settings\ramesh\My Documents\Tanner EDA\Work\10 bit
* Exclude global pins: no
* Exclude instance locations: no
* Control property name: SPICE
********* Simulation Settings - General Section *********


***** Top Level *****
MMn1 Out In N_2 0 NMOS25 W=1.5u L=250n M=1 AS=975f PS=4.3u AD=975f PD=4.3u $
$x=1893 $y=3500 $w=414 $h=600
MMp13 N_2 Vdd Gnd 0 NMOS25 W=1.5u L=250n M=1 AS=975f PS=4.3u AD=975f
PD=4.3u $ $x=1893 $y=2700 $w=414 $h=600
MMp14 N_2 D1 Gnd 0 NMOS25 W=1.5u L=250n M=1 AS=975f PS=4.3u AD=975f PD=4.3u
$ $x=2893 $y=2700 $w=414 $h=600
$ $x=3393 $y=2700 $w=414 $h=600
$ $x=3893 $y=2700 $w=414 $h=600
$ $x=4393 $y=2700 $w=414 $h=600
$ $x=4893 $y=2700 $w=414 $h=600
$ $x=5493 $y=2700 $w=414 $h=600
$ $x=6093 $y=2700 $w=414 $h=600
$ $x=6693 $y=2700 $w=414 $h=600
$ $x=7293 $y=2700 $w=414 $h=600
MMp23 N_2 D10 Gnd 0 NMOS25 W=1.5u L=250n M=1 AS=975f PS=4.3u AD=975f
PD=4.3u $ $x=7893 $y=2700 $w=414 $h=600
MMp1 N_1 Gnd Vdd Vdd PMOS25 W=1.5u L=250n M=1 AS=975f PS=4.3u AD=975f
PD=4.3u $ $x=1893 $y=5500 $w=414 $h=600
MMp2 N_1 D1 Vdd Vdd PMOS25 W=1.5u L=250n M=1 AS=975f PS=4.3u AD=975f
PD=4.3u $ $x=2893 $y=5500 $w=414 $h=600
PD=4.3u $ $x=3393 $y=5500 $w=414 $h=600
PD=4.3u $ $x=3893 $y=5500 $w=414 $h=600
PD=4.3u $ $x=4393 $y=5500 $w=414 $h=600
PD=4.3u $ $x=4893 $y=5500 $w=414 $h=600
PD=4.3u $ $x=5493 $y=5500 $w=414 $h=600
PD=4.3u $ $x=6093 $y=5500 $w=414 $h=600
PD=4.3u $ $x=6693 $y=5500 $w=414 $h=600
PD=4.3u $ $x=7293 $y=5500 $w=414 $h=600
PD=4.3u $ $x=7893 $y=5500 $w=414 $h=600
MMp12 Out In N_1 Vdd PMOS25 W=1.5u L=250n M=1 AS=975f PS=4.3u AD=975f PD=4.3u
$ $x=1893 $y=4400 $w=414 $h=600

.tran 5n 1u start=0
********* Simulation Settings - Additional SPICE Commands *********
.end
Output
SDL FOR 10 BIT NUMBER CONTROLLED OSCILLACTOR(NCO)
Following are the steps for Schematic Driven Layout:
Open the 10 bit NCO s spice netlist(extracted from schematic)
Change NMOS25 to NMOS and PMOS25 to PMOS
Delete the line that has the path to library.
Open RingVCO „s layout in L-Edit. It is located at “My Documents-> Tanner EDA-
>tanner tools-> Design->ringvco->ringvco.tdb”
In L-Edit we get the layout of ringvco. Goto cell->new view->Show SDL Navigator
SDL Navigator Window pops up. Click on folder icon to load netlist.
Browse to location where 10 bit NCO s netlist is available and load it.
We will get a message “0 warnings and 24 instances added. And go to windows and
choose cell0.
Now all the ports will get listed in sdl navigator window. Choose a port and click
on blue flyline button to make show connections.
Follow the fly-lines and complete the connections.
Routed layout will be as below
Give the path of generic 250.ext in tools->extract setup.and extract

Netlist for the layout.
MMn1 Out In N_1 0 NMOS25 W=1.5u L=250n M=1 AS=975f PS=4.3u AD=975f
PD=4.3u $ $x=1193
+$y=3400 $w=414 $h=600
MMn2 N_1 Vdd Gnd 0 NMOS25 W=1.5u L=250n M=1 AS=975f PS=4.3u AD=975f
PD=4.3u $ $x=1193
+$y=2500 $w=414 $h=600
MMn3 N_1 D0 Gnd 0 NMOS25 W=1.5u L=250n M=1 AS=975f PS=4.3u AD=975f
PD=4.3u $ $x=1893
+$y=2500 $w=414 $h=600
PD=4.3u $ $x=2493
+$y=2500 $w=414 $h=600
PD=4.3u $ $x=3093
+$y=2500 $w=414 $h=600
PD=4.3u $ $x=3793
+$y=2500 $w=414 $h=600
PD=4.3u $ $x=4493
+$y=2500 $w=414 $h=600
PD=4.3u $ $x=5093
+$y=2500 $w=414 $h=600
PD=4.3u $ $x=5793
+$y=2500 $w=414 $h=600
PD=4.3u $ $x=6593
+$y=2500 $w=414 $h=600
PD=4.3u $ $x=7293
+$y=2500 $w=414 $h=600
PD=4.3u $ $x=8093
+$y=2500 $w=414 $h=600
MMp1 N_2 Gnd Vdd Vdd PMOS25 W=1.5u L=250n M=1 AS=975f PS=4.3u
AD=975f PD=4.3u $
+$x=1193 $y=5400 $w=414 $h=600
MMp2 N_2 D0 Vdd Vdd PMOS25 W=1.5u L=250n M=1 AS=975f PS=4.3u
AD=975f PD=4.3u $
+$x=1893 $y=5400 $w=414 $h=600
AD=975f PD=4.3u $
+$x=2493 $y=5400 $w=414 $h=600
AD=975f PD=4.3u $
+$x=3093 $y=5400 $w=414 $h=600
AD=975f PD=4.3u $
+$x=3793 $y=5400 $w=414 $h=600
AD=975f PD=4.3u $
+$x=4493 $y=5400 $w=414 $h=600
AD=975f PD=4.3u $
+$x=5093 $y=5400 $w=414 $h=600
AD=975f PD=4.3u $
+$x=5793 $y=5400 $w=414 $h=600
AD=975f PD=4.3u $
+$x=6593 $y=5400 $w=414 $h=600
AD=975f PD=4.3u $
+$x=7293 $y=5400 $w=414 $h=600
AD=975f PD=4.3u $
+$x=8093 $y=5400 $w=414 $h=600
MMp12 Out In N_2 Vdd PMOS25 W=1.5u L=250n M=1 AS=975f PS=4.3u
AD=975f PD=4.3u $
+$x=1193 $y=4400 $w=414 $h=600
VVoltageSource_2 In Gnd PULSE(0 5 0 5n 5n 95n 200n) $ $x=800
$y=3600 $w=400 $h=600
Getting output is similar to inverter layout.

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VLSI LAB Using Tanner Tool

Trident Techlabs Pvt Ltd,

S-Edit™ is an easy-to-use PC-based design environment for schematic capture. It gives

L-Edit DRC features include:

My Documents\Tanner EDA\Tanner Tools v13.0\Libraries\All\All.tanner.

Lib file can be found at

My Documents\Tanner EDA\Tanner Tools v15.1\ Process\ Generic_250nm\ Generic_250nm_Tech\

After this add tt. So it looks like

My Documents\Tanner EDA\Tanner Tools v15.1\ Process\ Generic_250nm\ Generic_250nm_Tech\

Choose transient analysis and give parameters.

Goto tools and click on start simulation

T-Spice - Tanner SPICE

Standalone hardware lock

Product Release ID: T-Spice Win32 15.10.20101227.10:43:55

Copyright © 1988-2010 Tanner EDA

Reading library entry "tt" from "C:\Documents and Settings\ramesh\My Documents\Tanner

Reading library entry "GEN" from "C:\Documents and Settings\ramesh\My Documents\Tanner

Reading library entry "RES_CAP_TYP" from "C:\Documents and Settings\ramesh\My

Reading library entry "SIM_SUBCIRCUITS" from "C:\Documents and Settings\ramesh\My

Reading library entry "RES_CAP_SUBCIRCUITS" from "C:\Documents and Settings\ramesh\My

Reading library entry "TT_NMOS_PARAMETERS" from "C:\Documents and Settings\ramesh\My

Reading library entry "TT_PMOS_PARAMETERS" from "C:\Documents and Settings\ramesh\My

Reading library entry "MOS_MODEL" from "C: \Documents and Settings\ramesh\My

Loaded BSIM3v33 model library, Berkeley BSIM3 v3.3.0

Opening simulation database "C:\DOCUME~1\ramesh\LOCALS~1\Temp\Cell0.tsim"

Device and node counts:

Parsing 0.27 seconds

Setup 0.89 seconds

DC operating point 0.02 seconds

Transient Analysis 0.83 seconds

Overhead 2.20 seconds

Total 4.20 seconds

To view spice netlist of the circuit click on file-> export spice.

Following is the netlist we have for the inverter.

********* Simulation Settings - General Section *********

.lib "C:\Documents and Settings\ramesh\My Documents\Tanner EDA\Tanner Tools

*-------- Devices With SPICE.ORDER > 0.0 --------

***** Top Level *****

+$y=2300 $w=414 $h=600

+$x=7093 $y=3100 $w=414 $h=600

VVoltageSource_2 In Gnd PULSE(0 5 0 5n 5n 95n 200n) $ $x=6600 $y=2200 $w=400 $h=600

.PRINT TRAN V(In) $ $x=5950 $y=2850 $w=1500 $h=300 $r=180

.PRINT TRAN V(Out) $ $x=8350 $y=2550 $w=1500 $h=300

********* Simulation Settings - Analysis Section *********

********* Simulation Settings - Additional SPICE Commands *********

Given Below is the step by step for drawing an Inverter Layout.

Goto start->All programs->Tanner EDA->Tanner tools v15.xx-> LEDIT v15.xx 32 bit.

LEdit opens as below. In L-Edit Click on file->new. A window pops up

“My Documents\Tanner EDA\Tanner Tools v15.1\ Process\ Generic_250nm\ Generic_250nm_Tech\

Use + and – keys in num pad to zoom in and zoom out.

Tap twice on + key to have the grids visible.

Goto -> view->display->Major grids. Now major grids will be visible.

Goto -> setup->design

A window with design parameters will pop up.

Red Poly 1X X. Spacing between Poly & contact is 1 Lambda.

Place 2 other metal and contact combination near poly as below.

Distance between 2 (metal and contact) combination is 3 lambda.

Active region should cover metal region by 1 Lambda as shown above.

Pmos is grown in n-well. Distance between (p/nselect or p/n implant) is 3 lambda.

Rectify the errors and clear DRC.

For Creating Nmos Copy & paste Pmos

Change p-implant/select to n-implant/select and vice versa.

Procedure for changing p-select to n-select is giv en below.

* Simulation Settings - General Section *

* Top Level *

* Simulation Settings - Analysis Section *

* Simulation Settings - Additional SPICE Commands *

* Simulation Settings - Analysis Section *

* Simulation Settings - Analysis Section *

* Top Level *