Sir Syed University of Engineering & Technology

ANSWER SCRIPT

Date: 14/03/2021
Roll Number: 2020-SE-150
Section: D
Name: Muhammad Areesh
Course Name: Computer Organization & Architecture
Degree Program: BSSE
Total number of pages
5
being submitted:

Question 1 Explain Computer Organization and Computer Architecture in your own words.
Answer 1
Computer Organization:

It refers to the operational units and their interconnections that realize the architectural specifications.
Computer organization helps optimize performance-based products. For example, software engineers
need to know the processing power of processors.
Computer Architecture:
5
Question 2 What are the basic reasons of switching from one generation to another. Compare the
Second and Third generations of computer.
Answer 2
Each generation is defined by a significant technological development that changes fundamentally
how computers operate leading to more compact, less expensive, but more powerful, efficient and
robust machines.
The Basic Reasons of switching from one generation to another are as below:
 Size
 Speed
 Memory

Comparison of Second and Third Generation:

 The Second Generation computers are used transistors whereas the Third Generation
Computers are used integrated chip.
 The Third Generation computers are faster as compared to Second Generation Computers.
 The Second Generation computers are costly as compared to Third Generation Computer.
 The Third Generation computers produced less heat whereas the Second Generation
Computers used less energy and were heated.
 The Second Generation computers had less memory capacity and Third Generation computers
had greater memory capacity.
 The Third Generation computers smaller in size as compared to Second Generation
Computers.

Question 3 List general categories of functions that are specified by computer instructions?

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Answer 3
In general terms, there are only four basic functions that a computer can perform: All computer
functions are:
• Data processing
• Data storage
• Data movement
• Control

Question 4 Given following 16-bit hypothetical machine working on hexadecimal numbers has
following Instructions:
0001 = Load AC from memory
0010 = Store AC to memory
0011 = Load AC from I/O
0100 = Store AC to I/O
0101 = Add to AC from memory or I/O

In this case, the 12-bit address of Instruction format identifies a particular Memory
address or I/O device. Show the program execution for the following Program:
1. Load AC from device 05.
2. Add contents of memory location 940.
3. Store AC to device 06.

Assume that the next value retrieved from device 05 is 0003 and the location 940
contains a value of 0002.

Memory CPU Registers

300 PC
301 AC
302 IR

940
941
I/O Devices
Device 5
Device 6

Device 10

16-bit Hexadecimal Hypothetical Machine

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Question 5 Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of
two fields: the first four bits contains the opcode and the remainder the immediate operand or an
operand address.

a. What is the maximum directly addressable memory capacity (in bytes)?

b. Discuss the impact on the system speed if the microprocessor bus has:
1. 16-bit local address bus and a 16-bit local data bus, or
2. 32-bit local address bus and a 16-bit local data bus.
3. 08-bit local address bus and a 32-bit local data bus.
c. How many bits are needed for the program counter and the instruction register?

Answer 5

(5a)

2^(32-4)=2^28= 268,435,456bytes.

(5b) 1.

16-bit local address bus and a 16-bit local data bus. Instruction and data transfers would take four bus
cycles each, two for the address and two for the data. It will have the processor perform two
transmissions in order to send to memory the whole 32-bit address; this will require more
complex memory interface control to latch the two halves of the address before it performs
an access to it

(5a) 2.

32-bit local address bus and a 16-bit local data bus. Instruction and data transfers would take three bus
cycles each, one for the address and two for the data. Since If the address bus is 32 bits, the
whole address can be transferred to memory at once and decoded there; however, since the data bus is
only 16 bits, it will require 2 bus cycles (accesses to memory) to fetch the 32 bit instruction or
operand.

(5b) 3.

It would take 5 bus cycles total for data and instruction transfer. 4 cycles for the address bus(8 bits)
and 1 cycle for the data bus(32 bits). Since the microprocessor is 32 bits therefore, address will be
transferred to 8 bits address bus in 4 cycles. Instructions will be fetched by data bus in 1 cycle.

(5c)

PC needs 24 bits (24-bit addresses), and the IR needs 32 bits (32-bit addresses).

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