THE SOFTWARE VIEW OF THE 80386 MICROPROCESSOR

2.0 Outcomes

At the end of this chapter, you should be able to:

1. Describe the software view of the 80386 microprocessor in real mode

2. List and describe the function of the 80386 registers and flags

3. Describe the memory management used by the 80386 in real mode

2.1 The 80386 Microprocessor Family

The 80386 family contains several microprocessors to satisfy the needs of different types of

users. The most common family members are the 80386DX and the 80386SX. Table 2.1 lists

the specification for the data and address buses of the SX and DX versions of the 80386

microprocessor. Both the SX and the DX versions of the 80386 can operate in either real mode

or protected mode. In the real mode the 80386 microprocessor operates like a powerful 80286

(16-bit microprocessor) and thus can address only 1 MB of memory. In the protected mode the

80386 can access the entire memory space. In this book only the real mode will be discussed.

Table 2. 1 The 80386 Family of Microprocessors

80386 DX 80386 SX

• 32-bit data bus. Thus 32 bit •
data transfer is possible
• 32-bit address bus. Thus, can •
address up to 4 Gigabyte of
memory
16-bit data bus. Thus, only up to
16 bit data transfer is possible
24-bit address bus. Thus, can
address up to 16 megabyte of
memory
2.2 Real Mode Model
To enable a programmer to write assembly programs for the 80386 family of microprocessors, a

software model of the internal architecture of the microprocessor is needed. The model

basically describes the registers and flags available for the programmer use.

2.2.1 Registers
A register is a place where data can be stored and manipulated. The registers of 80386

microprocessors can broadly classified into two groups: General-purpose registers, and special

purpose registers

2.2.1.1 GENERAL PURPOSE REGISTERS

The general-purpose registers can also be divided into two groups: Data registers, and index

and pointers registers.

2.2.1.1.1 Data Registers

There are 4 data registers that can be used to store data temporarily during the execution of

program instructions. These can be used as the destination or the source for any data

movement instruction. These registers can be used as 8-bit (for example AL or AH) so that

programs written on Intel 8-bit microprocessors can be executed on the 80386 in real mode.

They can also be used as 16-bit (for example AX) to allow 80286 codes to run by the 80386.

These registers also allow 32-bit operations (for example EAX).

Although, these registers are called general purpose, there are certain operations that only

possible on a given register. Table 2.1 lists the 4 general-purpose data registers and the

operations specific to each of them.

Table 2. 2 Data Registers

REGISTER ABBREVIATION USAGE

NAME 8 8 16 32
Accumulator AL AH AX EAX Arithmetic operations like addition, subtraction,
 division and multiplication, data conversion between
byte, word, double word, and quadruple word.
Input/output operations and memory addressing
Base Index BL BH BX EBX Memory addressing
Count CL CH CX ECX Looping and repeating string operations, reading
and writing data to disk files
Data DL DH DX EDX Input/output operations with external devices,
multiplication and division operations (in
conjunction with accumulator), and string
operations

2.2.1.1.2 Index and Pointer Registers

The 4 registers in this group can be used either as 16-bit or 32-bit registers. These registers are

used to hold the offset of the address of the data held in memory. The other part of the

address, the segment address, is normally held by a segment registers. Table 2.2 describes the

usage of these registers.

Table 2. 3 Index and Pointer Registers

Register Name Abbreviation Usage

16 32
Base Pointer BP EBP Used to hold the offset address of the stack as well as the
memory
Destination DI EDI Used to hold the offset address of a destination operand
Index
Source Index SI ESI Used to hold the offset address of a source operand

Stack Pointer SP ESP Used to hold the offset address of the stack

2.2.1.2 SPECIAL PURPOSE REGISTERS

The 80386 microprocessor has 4 types of special purpose registers. These are the segment

registers, the flags register, the instruction pointer, and control registers.
2.2.1.2.1 The Segment Registers

The six segment registers are 16 bits wide. Each segment register holds the base memory

address for a 64K-memory segment. Table 2.4 briefly describes the usage of the segment

registers.

Table 2. 4 Segment Registers

REGISTER NAME ABBREVIATION USAGE

Stack Segment SS Holds the Base address of the stack memory
Code Segment CS Holds the Base address of the code memory
Data Segment DS Holds the Base address of the data memory
Extra Segment ES Holds the Base address of the extra memory
Additional GS and FS Hold the Base address for two additional segments of
Segments memory

2.2.1.2.2 The Instruction Pointer

The instruction pointer (EIP) is a 32-bit register. This register is used with the code segment

register (CS) to hold the address of the next instruction to be fetched from the code segment of

the memory.

2.2.1.2.3 Control Register

Although, the 80386 microprocessor has several control registers, only one of them control

register zero is active in real-mode. The five least-significant digits are called the machine status

word (MSW). In real-mode, only bit 0 of the control register zero is active. This bit is called the

protection enable and is used to switch between real-mode and protected-mode.

2.2.2 The Flags

The 80386 microprocessor has a 32-bit flag register called EFLAGS. However, in real-mode only

the first nine bits are used. These are the same as those for the 80286 microprocessor. The first

six are called status flags because their states (set or reset) change as a result of executing
certain instructions. The last three flags are control flags used to control the operations of the

80386 microprocessor. The name and usage of these flags are summarised in Table 2.5

Table 2. 5 The Flags

NAME ABBREVIATION USAGE

Carry C This flag is set (1) if there is a carry out or a borrow from the
most significant bit of an arithmetic instruction such as Add.
Otherwise, it is reset (0)
Parity P If the result of an instruction has an even number of 1's (even
Parity) then this flag is set. Otherwise, it is reset
Auxiliary A This flag is set if there is a carryout from the low nibble to the
Carry high nibble or a borrow-from the high nibble to the low nibble
during BCD addition and subtraction. Otherwise, it is reset
Zero Z This flag is set if the result of an instruction is 0 otherwise, it is
reset
Sign S This flag is set if the result of logic or an arithmetic operation is
negative. Otherwise, it is reset.
Overflow O This flag is set when an overflow occurs during signed number
arithmetic
Trap T Used to enable trapping errors during program debugging. If
this flag is set, the single-step mode of the 80386 is enabled
Interrupt I If set to 1 interrupt is enabled otherwise interrupt is disabled
Direction D If set to 1 the DI and SI registers are automatically
decremented otherwise they are automatically incremented
2.2.3 Memory Management
When talking about memory management it is important to distinguish between physical and

virtual (logical) memory and how the virtual memory is mapped into the physical memory

2.2.3.1 Physical Memory Address

The memory chips on the computer motherboard where data and program are stored are called

physical memory. Each memory location has an address. These addresses are linearly ordered

from 0 to M. The value of M indicates the maximum storage capacity of the computer memory.

Figure 2.1 shows a graphical representation of physical memory addresses.

Address M Content

Address 0 Content

Figure 2.1

2.2.3.2 Logical Memory Address

Logical or virtual memory address is the address generated by a process that is currently being

executed by the processor. This address needs to be translated into a physical address to

access the data stored in the memory. This translation can be done by the processor itself or by

a dedicated memory management unit.

2.2.3.3 Mapping of Logical Memory into Physical Memory
There are two basic schemes where the logical memory is mapped into the physical memory.

These are: Flat addressing and segmented (paging) addressing.

2.2.3.3.1 Flat Addressing

The memory architecture in which any memory location (physical address) can be selected from

a single contiguous block by a single integer offset (logical address) is called flat addressing.

Thus, in this addressing mode there is a one to one correspondence between logical addresses

and physical addresses. A flat address space greatly simplifies programming because of the

simple correspondence between addresses (pointers) and integers.

2.2.3.3.2 Segment Addressing

Memory segmentation is the division of computer's primary memory into segments or sections.

In a computer system using segmentation, a reference to a memory location (physical address)

includes a value that identifies a segment and an offset within that segment. Thus, the logical

address is made of two components: A segment and an offset. Different segments may be

created for different program modules, or for different classes of memory usage such as code

and data segments. Certain segments may even be shared between programs.

2.2.3.4 Real Mode Memory Addressing

As stated in Table 2.1, the address bus of the SX and DX versions of the 80386 is 24 and 32

bits wide respectively. Thus, the maximum addressable memory space is 224 bytes and 232 bytes

for the SX and DX respectively. However, in real mode, only 20 bits are used for memory

addressing thus, the maximum addressable memory is 220 = 1048576 bytes which is equivalent

to 1 Mbytes. The logical address generated by the process being executed by the 80386 is

always made up of two components: A segment address stored in one the segment registers
and an offset address stored in one of the index and pointer registers. Thus, the logical address

is 32 bits but the physical address is only 20 bits. The memory management unit in the

microprocessor translates the 32 bits logical address into a 20 bits physical address as shown in

Figure 2.2.

Logical Address

Segment Address (16 bits) Offset Address (16 bits)

Segment Address (16 bits) 0000

Adder

Physical Address (20 bits)

Figure 2.2

Table 2.6 shows few examples of this mapping. As can be seen from Table 2.6 it is possible

that more than one logical address produce the same physical address. In fact any given

physical address can be generated from 4096 possible logical addresses.

Table 2. 6 Mapping Logical addresses to Physical Addresses

Segment Offset Logical Address Physical Address

1000H 1234H 1000:1234H 10000H +1234H =11234H

23FBH FAB3H 23FB:FAB3H 23FB0H + FAB3H = 33A63H

0FF1H 1324H 0FF1:1324H 0FF10H + 1324H = 11234H

2.2.3.5 Segments Register and their Default Offset Registers

As mentioned earlier, the logical address is formed from a segment address held in a segment

register and an offset address. The offset address is obtained from one of the general purpose

or special purpose registers or from a combination of both depending on the type of access to

be performed by the microprocessor. Each segment register has a default offset register as

shown in Table 2.7. This default segment-offset relationship can be overridden for certain

operations by specifying the name of the segment to be used in front of the offset register.

Table 2. 7 Segment Registers and their Default Offset Registers

Type of operation Default Offset Comment

Segment
Instruction CS EIP Cannot be changed

Stack SS ESP, EBP Default offset register is ESP

Data DS EBX, EDX, Other data segment registers such as GS and

ESI, EDI FS can be used
Destination String ES EDI Cannot be changed

String Source DS ESI Cannot be changed

The number of segments for instructions (code), data and stack depends on the model

selected. In TASM, the .model directive specifies one of several models. The number and type

of segments that each model type specifies are given in Table 2.8

Table 2. 8

Model Type Segment Type Description

Code Data Stack

Tiny 1 Run only under MS-DOS. All code and data in a

single segment (code segment)
Small 1 1 1 All data and code are near by default

Medium Multiple 1 1

Compact 1 Multiple 1

Large Multiple Multiple 1 All data and code are far by default.

2.3 Review Questions

1) The registers of the 80386 microprocessor can be classified into:
a) General-purpose and special-purpose
b) General-purpose, data, index and pointer registers
c) Special-purpose, data, index and pointer registers
d) None of the above
2) The number of data registers in the 80386DX microprocessor is?
a) 6
b) 4
c) 8
3) The data registers in the 80386 microprocessor allows:
a) 8-bit access
b) 16-bit access
c) 32-bit access
d) All the above
4) Which of the following operations can be performed on the accumulator?
a) Arithmetic operation
b) Input/output operation
c) Data conversion
d) All the above
5) The number of index registers in the 80386DX microprocessor is?
a) 6
b) 4
c) 2
d) None of the above
6) Which two of the index and pointer registers can be used to hold the offset for the stack
segment?
a) SP and SI
b) BP and DI
c) SP and BP
d) All the above
7) The special-purpose registers of the 80386 microprocessor are:
a) Segment registers, Instruction pointer, and Control register
b) Segment registers, Flags register, Instruction pointer, and Control register
c) Segment registers and Flags register
8) The 80386 microprocessor uses:
a) Flat addressing techniques
b) Segment addressing techniques
c) All of the above
9) What is the total active memory that can be accessed by the 80386DX microprocessor
in real-mode?
a) 256K-byte
b) 384K-byte
c) 1M-byte
d) None of the above
10) What is the physical address for the logical address 1234:FFB3?
a) 222F3H
 b) 22F23H
c) None of the above
11) Which pair of registers is used to hold the address of instructions in memory?
a) CS:IP
b) CS: BP
c) DS:IP
d) None of the above
12) List the 4 data registers and briefly explain their usage
13) List the 4 index and pointer registers and briefly explain their usage
14) List the 6 segment registers and briefly explain their usage
15) Explain the usage of the Carry flag.
16) Describe the usage of the sign flag