AM QUESTION BANK SOLUTION

Q.14 - Q.18 - Q.33 - Q.36 - Q.40 NOT FOUND

1. Draw the block diagram of 8086 and explain each block.

8086 provides the programmer with 14 internal registers, each of 16 bits or 2

bytes wide. The main advantage of the 8086 microprocessor is that it supports
Pipelining. The internal architecture of Intel 8086 is divided into 2 units: The Bus
Interface Unit (BIU), and The Execution Unit (EU).

The BIU of 8086 microprocessor has the following functional parts:

⮚ Instruction Queue:
o The Bus Interface Unit of the 8086 microprocessor contains an
instruction queue.
o BIU gets up to six bytes of the next instructions and stores them in
the instruction queue.
 o When the Execution unit executes an instruction and is ready for the
next instruction, it simply reads the instruction from the instruction
queue resulting in increased execution speed.
o Pipelining is the process of fetching the next instruction cycle when
the current instruction is being executed.

⮚ Segment Register:
o The BIU of 8086 microprocessor has 4 segment buses i.e. CS, DS, SS &
ES. Ts holds the address of instructions and data in the memory
which are used by the processor to access memory locations. It also
contains one pointer register IP.

▪ Code Segment Register (CS): The base of the current code

segment is contained by the code segment register of the 8086
microprocessors. It finds its application in addressing a
memory location in the code segment of the memory where
the executable program is stored.

▪ Data Segment Register (DS): The data segment contains the

starting address of the program’s data segment. It is accessed
in the data segment by an offset address or the content of the
other register that holds the offset address.

▪ Stack Segment Register (SS): The stack segment register of the

8086 microprocessor contains the starting address of a
program’s stack segment. The current word in the stack that is
addressed is indicated by the segment address plus an offset
value in the stack pointer.

▪ Extra Segment Register (ES): The ES of the 8086

microprocessor is an additional data segment used by some
strings to hold extra data. The string instructions always use
the ES and destination index (DI) to determine the 20-bit
physical address.
 ▪ Instruction Pointer Register (IP): The Instruction Pointer is a
16-bit register. IP is responsible for holding the distance or
offset from this address to the next instruction byte to be
fetched.

The EU of 8086 microprocessor has the following functional parts:

The execution unit of the 8086 gives instructions to the bus interface unit stating
from where to fetch the instructions or data from, decode the instructions, and
execute those instructions.
The main function of the EU of the 8086 microprocessor is to control operations
on data using an instruction decoder and ALU. It has no direct connection with
the system and performs over data through BIU.
The EU includes an arithmetic and logic unit (ALU), a control unit, and a set of
registers.
⮚ ALU: The arithmetic and logic unit perform all the arithmetic and logical
operations like add, subtract, OR, AND, NOT in the 8086 microprocessors.

⮚ General-Purpose Registers: The 8086 microprocessor has 8 registers AH,

AL, BH, BL, CH, CL, DH, DL. Individually, these registers can store 8-bit data,
and in pairs, they can store 16-bit data. The valid register pairs are AHAL,
BHBL, CHCL, DHDL. They can be represented as AX, BX, CX, and DX.

o AX Register: The AX register is called a 16-bit accumulator and AL is

called the 8-bit accumulator. For inputting/outputting data from or
to I/O ports, the I/O (IN or OUT) instructions often use AX or AL.

o BX Register: The BX register of the 8086 microprocessor is known as

the base register. It is used to store the starting base address of the
memory field within the data section. It is also used as an index to
extend addressing. BX can also be used as a foundation register in
conjunction with DI or SI for special addressing.
 o CX Register: The contents of the CX register of the 8086
microprocessors are used as a counter in certain instructions such as
SHIFT, ROTATE, and LOOP.

o DX Register: The DX register of the 8086 microprocessor is known as

the data register. It is used to hold the I/O port address during the
I/O instructions.

⮚ Stack Pointer Register (SP) and Base Pointer Register (BP): Both the SP
and BP registers in the 8086 microprocessors are used to access data in the
stack segment. During the execution of instructions, the SP is used as an
offset from the current stack section. The contents of SP are automatically
updated (increment/decrement) during the execution of a POP and PUSH
instruction. The offset address in the current stack section is stored in the
BP. Instructions that use the based addressing mode make use of this
offset.

⮚ Index Register: The two index registers SI (source index) and DI (destination
index) o the 8086 microprocessors are used in indexed addressing. The
instructions that process data strings use the SI and DI index registers, along
with DS and ES, to differentiate between the source and destination
address.

⮚ Flag Register: The flag register of the 8086 microprocessor is also known as
the status register. It is a 16-bit register that can be used as a flipflop as its
status changes according to the result. The control bit in the flag register
can be set or reset by the programmer. It has 9 flags and they are divided
into two groups: Conditional flags and Control flags.

o Conditional Flags: These flags reflect the outcome of the most recent
arithmetic or logical instruction. Following is the list of conditional
flags of the 8086 microprocessors:
 ▪ Carry Flag(C): This flag is set in an 8086 microprocessor when
there is a carry out of MSB in addition or borrow in
subtraction.

▪ Parity Flag (P): This flag is set to 1 if the lower byte of the
result contains an even number of 1’s otherwise reset.

▪ Auxiliary Carry Flag (A): This is set if there is carry from the
lowest nibble during addition or borrow from the lowest bibble
during subtraction in an 8086 microprocessor.

▪ Zero Flag (Z): If the product of arithmetic or logical operations

is zero, this flag is set to 1, otherwise, it is set to 0.

▪ Sign Flag (S): This flag bears the result’s symbol. i.e. when the
result of the operation is negative, the sign flag is set to 1 else
it is set 0.

▪ Overflow Flag (O): This flag indicates what happens when the
system’s capability is surpassed.

o Control Flags: Control flags govern the execution unit’s activities.

They are:

▪ Trap Flag (T): This flag is used for single-step monitoring and
helps the user to debug by executing one instruction at a time.
If it is set, then the program can run in a single-step mode.

▪ Interrupt Flag (I): It is an interrupt enable/disable flag i.e. It is

used to authorize or prevent program interruption. It is set 1
for interrupt enabled condition and set 0 for interrupt disabled
condition.

▪ Direction Flag (D): This flag is used for string manipulation

instructions. If this parameter is set to 0, the string is
 processed from the lowest to the highest address. i.e. the
string is processed from the highest address to the lowest
address unless the auto-incrementing mode is used i.e. auto
decrementing mode.

2. Discuss the addressing modes provided by 8086 and explain with

examples.
Addressing Mode can be defined as method of accessing data from memory or
Registers. The following are the types of Addressing Modes:
⮚ Register Addressing Mode: Transfers a copy of a byte or word from the
source register or memory location to the destination register or memory
location. Source and destination registers must have the same size.

MOV BX, DX ; copy the contents of DX into BX

MOV ES,AX ; copy the contents of AX into ES
ADD AL,BH ; add the contents of BH to contents of AL

⮚ Immediate Addressing Mode: Transfers the source, an immediate byte or

word of data, into the destination register or memory location.
The source operand is a constant.
Immediate addressing mode can be used to load information into any of
the registers except the segment registers and flag registers.

MOV AX,2550H ; move 2550H into AX

MOV CX,625 ; load the decimal value 625 into CX
MOV BL, 40H ; load 40H into BL
MOV AX,2550H
MOV DS, AX
MOV DS, 0123H ; illegal instruction!
⮚ Direct Addressing Mode: Moves a byte or word between a memory
location and a register. This address is the offset address.

MOV AX, [2400] ; move contents of DS:2400H into AX

The physical address is calculated by combining the contents of offset

location 2400 with DS.

⮚ Register Indirect Addressing Mode: Instruction specifies an address where

data is located. This addressing mode works with SI,DI,BX,BP registers.

Example1 : Write value 0065h at the address pointed by DS:BX

MOV BX,1200h
MOV [BX],65H

⮚ Based-Relative Addressing Mode: This addressing mode uses a base

register either BX or BP and a displacement value to calculate physical
address.

MOV [BX+5], DX

⮚ Indexed Relative Addressing Mode: This addressing mode is same as the

based relative addressing mode. The only difference is it uses DI and SI
registers instead of BX and BP registers. For example:

Given that DS=704, SI = 2B2, DI= 145

MOV [DI]+12, AL
This instruction on execution will copy the content of AL at memory
address 7197 (7040 + 145 + 12)

MOV BX, [SI]+10

⮚ Based-indexed relative Addressing Mode: The based indexed addressing
mode is actually a combination of based relative addressing mode and
indexed relative addressing mode. It uses one base register (BX, BP) and
one index register (SI, DI). For example:

MOV AX, [BX+SI+20]

The above instruction can also be written as:

MOV AX, [SI+BX+20]

3. Draw interfacing diagram of 8086 maximum mode.

4. Explain memory organization of 8086 microprocessor.
The 8086 processor provides a 16-bit data bus. So, it is capable of transferring
16 bits in one cycle but each memory location is only of a byte (8 bits),
therefore we need two cycles to access 16 bits (8 bit each) from two different
memory locations. The solution to this problem is Memory Banking. Through
Memory banking, our goal is to access two consecutive memory locations in
one cycle (transfer 16 bits). The memory chip is equally divided into two
parts(banks). One of the banks contains even addresses called Even bank and
the other contains odd addresses called Odd Bank. Even bank always gives
lower byte, also called Lower Bank (LB) and Odd bank is also called Higher
Bank (HB). This banking scheme allows to access two aligned memory
locations from both banks simultaneously and process 16-bit data transfer.
Memory banking doesn’t make it compulsory to transfer 16 bits, it facilitates
the 16-bit data transfer. The choice between 8 bit and 16-bit transfer depends
on the instructions given by the programmer.
 5. Discuss about Multiplexing in 8086 microprocessors.
Multiplexing is the process of combining multiple signals into one signal, over a
shared medium.
In 8086 the address lines are not dedicated to carry the address but are time
multiplexed with the data bus and the status signals. This multiplexing is done to
keep the number of pins as minimum as possible. These lines are demultiplexed
to generate the independent address, status as well as the data bus.
During the T1 state of every machine cycle the multiplexed lines carry the address
part. In this T1 state, ALE signal is also high to indicate that these lines carry a
valid address. After T1 state, the microprocessor 8086 will remove the address
contents from these lines and use these lines as the data lines and status signals
for next three clock cycles. The demultiplexing of these lines is done by using the
three 8-bit D-latch IC along with the ALE signals. When ALE is high it will trigger
the D-FF’s through the STB terminal of the latch. The address signals will get
latched in the 8-bit latches and the output of latch will provide A0-A19 address
contents and BHE.
6. Discuss how procedures are defined and involved in assembly language
programming.
Procedures or subroutines are very important in assembly language, as the
assembly language programs tend to be large in size. Procedures are identified
by a name. Following this name, the body of the procedure is described which
performs a well-defined job. End of the procedure is indicated by a return
statement. Following is the syntax to define a procedure −
proc_name:
procedure body
...
ret
The procedure is called from another function by using the CALL instruction.
The CALL instruction should have the name of the called procedure as an
argument as shown below −
 CALL proc_name

[NOTE: NOT SURE IF THIS IS THE RIGHT ANSWER OR NOT]

7. Explain all the features in 8284.
8284 is an 18-pin chip which is designed to provide the clock frequency, Ready
and Reset signals to 8088/86 microprocessors. The READY and RESET signals are
applied to the clock generator and it synchronizes the READY and RESET signals
with clock and then apply them to the microprocessor. The following are the
features in 8284:
(NOTE: NOT SURE IF THE BELOW POINTS ARE WRITE OR WRONG)
o It provides a stable clock to the processor.
o In the case of a multiprocessor system, it facilitates synchronization
of multiple clock signals.
o Provides resetting to the processor along with the clock signal.

8. Bring out the differences between 8086 and 8088 processors.

8086 Processor
The data bus is of 16 bits.
It has 3 available clock speeds (5 MHz,
8 MHz (8086-2) and 10 MHz (8086-1)).
The memory capacity is 512 kB.
It has memory control pin (M/IO)
signal.
It has Bus High Enable (BHE) signal.
It can read or write either 8-bit or 16-
bit word at once.
It has 6-byte instruction queue.
8088 Processor
The data bus is of 8 bits.
It has 2 available clock speeds (5 MHz,
8 MHz)
The memory capacity is implemented
as a single 1 MX 8 memory banks.
It has complemented memory control
pin (IO/M) signal of 8086.
It has System Status Output (SSO)
signal.
It can read only 8-bit word at once.
It has 4-byte instruction queue as it
can fetch only 1 byte at a time.
9. Why and when wait states are required. How do you insert wait states1 in
8086 processor.
The WAIT instruction suspends the microprocessor execution, and the
processor enters into the wait state. The processor will remain in wait state
until a signal (TEST) is received which indicates that the coprocessor has
finished a simultaneous operation. This instruction is used when the
microprocessor is used in maximum mode configuration and specifically when
a math coprocessor is present in the multiprocessing environment system. This
instruction prevents the math coprocessor instruction from modifying a
memory location that is being modified at the same time by a processor
instruction. FWAIT is an equivalent instruction in the math coprocessor's
instruction set.
If after sending an address out, the microprocessor does not receive a READY
input from memory, it enters a wait state for as long as the READY line is in 0
state. When the memory access is completed the READY goes high to indicate
that the memory is ready for specified transfer.
10. How do you configure 8086 into minimum and maximum modes.
a) Minimum Mode Configuration:
When the MN/MX- pin of the 8086 is wired to a +5 volt power supply,
the processor operates in minimum mode. This mode is intended for
small- and medium-sized systems employing only a single processor.
All the control signals are generated by the 8086 processor itself. It
consists of:
▪ Three 8-bit Latches: The latches are D-type flip-flops whose
outputs are generally buffered. The ALE signal controls the D-
FF in the latches.

▪ Two 8-bit Transceivers: The transceivers are used to separate

the data bus from the multiplexed address/data bus.

▪ One Control Signal Generator: The control signal generator is

used to generate the four control signals.
 ▪ One Clock Generator: The clock generator is responsible for
the generation of the required clock frequency and to
synchronize the READY and RESET signals.

b) Maximum Mode Configuration:

In the maximum mode of operation of 8086, more than one
processor is present in the system, i.e. another processor is
interfaced with 8086. The other processor may be either a
numeric coprocessor 8087 or any other independent processor
like 8086 or 8088. All the resources like memory, address bus,
data buses are shared between the two processors. It consists of:

▪ Three 8-bit Latches (IC 8282): The latches are used to

demultiplex the multiplexed address/data lines and also
address/ status signals.
 ▪ Two 8-bit Transceivers (IC 8286): The transceivers are used to
enable the data flow and direction of the data flow.

▪ One Clock Generator (8284): The clock generator is used to

generate the clock and also synchronize the READY and RESET
signals.

▪ Bus Controller 8288: It provides the control and timing signals.

11.Describe software interrupt of 8086 microprocessor. Also discussed the

sequence of interrupt execution in 8086.
Microprocessor 8086 has two mnemonics INTn and INTO. These two are the
software interrupts of 8086. The INTn in fact represents 256 different interrupt
instructions, e.g. INTO, INTI, INT255, etc. INTO is the interrupt on overflow
instruction. Hence, 8086 has 256 unconditional software interrupts and one
conditional software interrupt. The INTn instruction can be used to generate
any hardware or dedicated interrupt. For example, INT2 will generate the type
 2 or NMI interrupt and INT4 can be used to generate INTO interrupt. Similarly
INTO can generate the divide by zero interrupt. The IP value for any interrupt
type is always at an address four times the interrupt type.
In response to the INTn instruction microprocessor go through the same
sequence of events, i.c. push the flags register on the top of stack, clear TF and
IF flags and push the CS and IP values of the next instruction on the stack. It
will then get the CS and IP values for the start of the ISR. In 8086 the interrupts
are serviced as per the following priority order:
o Internal Interrupts and Exceptions
o Software Interrupt
o Non-Maskable Interrupt
o INTR
o Single Step

12.Under what conditions type 0 interrupt is initiated? List out the

instructions that may cause type 0 interrupt?

TYPE 0 INTERRUPT:-
- 8086 supports division (unsigned/signed) instruction. 8086 will automatically do a
type 0 interrupt if the result of DIV or IDIV operation is too large to fit in destination
register.
- Type 0 is automatic and cannot be disabled i.e. non mask-able.
- Users have to account it in the program where he/she uses DIV/IDIV instruction.
- Normally user will write an interrupt service procedure which takes desired action
when an invalid division occurs.
- To avoid this interrupt, user can check before division that divisor is not zero.

INSTRUCTIONS:
→ When type 0 interrupt is internally generated, microprocessor will
- Push flag register.
- Reset TF and IF.
- Push CS and IP (i.e. return address).
- Get NEW CS and NEW IP.
- NEW CS and NEW IP will be loaded into the CS and IP register. Thus we get branching
to ISR routine.
- After returning from ISR, microprocessor will pop CS and IP (OLD CS/OLD IP).
- Microprocessor will also pop flag register.
-
 13.What is memory segmentation? Describe physical memory organization.
How to calculate the physical memory address.
Segmentation is the process in which the main memory of the computer is
logically divided into different segments and each segment has its own base
address. It is basically used to enhance the speed of execution of the computer
system, so that the processor is able to fetch and execute the data from the
memory easily and fast. The main advantages of segmentation are as follows:
o It provides a powerful memory management mechanism.
o Data related or stack related operations can be performed in
different segments.
o Code related operation can be done in separate code segments.
o It allows to process to easily share data.
o It allows to extend the address ability of the processor, i.e.,
segmentation allows the use of 16-bit registers to give an addressing
capability of 1 Megabytes. Without segmentation, it would require
20-bit registers.
Here is the way to calculate the physical memory address:

14.What is function of ready pin in 8086. Draw the circuit diagram for wait state
generation between 0 and 7 wait status and draw the corresponding timing
diagram.

READY PIN:-
- It is an active high signal.
- When it is high, it indicates that the device is ready to transfer data.
- When it is low, it indicates wait state.
- It is available at pin 21 and is used to restart the execution….QS1 and QS0.

15. Write an assembly language program to add two 16 bit numbers.

DATA SEGMENT
NUM DW 1234H, 0F234H
SUM DW 2 DUP(0)
DATA ENDS
CODE SEGMENT
ASSUME CS: CODE, DS:DATA
START: MOV AX,DATA
MOV DS,AX

MOV AX,NUM ; First number loaded into AX

MOV BX,0H ; For carry BX register is cleared
ADD AX,NUM+2 ; Second number added with AX
JNC DOWN ; Check for carry
INC BX ; If carry generated increment the BX
DOWN: MOV SUM,AX ; Storing the sum value
MOV SUM+2,BX ; Storing the carry value
MOV AH,4CH
INT 21H CODE
ENDS END
START

16. Write an assembly language program to sub two 16 bit numbers.

17.Write an assembly language program to Multiplication two 16 bit

numbers.
DATA SEGMENT
NUM DW 1234H,1234H
PROD DW 2 DUP(0)
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE,DS:DATA
START: MOV AX,DATA MOV
DS,AX
LEA SI, NUM ; SI pointed to the Multiplicand

MOV AX,[SI] ; Multiplicand has to be in AX register

MOV BX,[SI+2] ; SI+2 pointed to the Multiplier and move it to BX
MUL BX ; Perform the multiplication
MOV PROD,AX ; 32 bit product stored in DX-AX registers
MOV PROD+2,DX
MOV AH,4CH
INT 21H
CODE ENDS
END START

18.Write a program to count negative number from array of 5 data bytes.

ERROR 404: ANSWER NOT FOUND!
19.Write a program to transfer string of data bytes.

20. Draw 80186 block diagrams and describe in detail.

Functional parts of 80186 Microprocessor: -
a) The Bus Interface Unit (BIU): The 80186 has the same bus interface unit
(BIU) and execution unit (EU) as the 8086. We can see this under the
heading. The 8086 Microprocessor- Internal Architecture. The 80186 is
68 pins lead-less package, so it has enough pins to send out both the
minimum mode type signals RD and WR and the S0 – S3 status signals
which can be connected to external bus controller ICs for maximum
mode systems. It does not have a pin labelled MN/MX for switching the
minimum mode through the maximum mode.

b) Execution Unit (EU)

c) Clock Generator: The 80186 has a built-in clock generator so that we can
add external crystal. This reduces the component count in a system. It
has three-pin connections: X1, X2, and CLK OUT. The X1 and X2 pins are
connected to a crystal that resonates twice the operating frequency of
the microprocessor. The CLK OUT pin provides a system clock signal that
is one-half the crystal frequency. In addition to external pins, the clock
generator provides the internal timing for synchronizing the READY input
pin.

d) Programmable Interrupt Controller: The programmable interrupt

controller has four interrupt inputs: INT0, INT1, INT2/INTA0, and
INT3/INTA1 as well as one non-maskable interrupt NMI input. These
inputs operate with two modes: internal mode and external mode. In
internal mode, if the four INT inputs are programmed, then a signal is
applied to one of them to push the return address on the stack and
vector directly to the start of the interrupt service procedure for that
interrupt. In external mode, the INT2/INTA1 pins can be programmed to
be used as interrupt inputs or they can be programmed to function as an
interrupt acknowledge outputs. This mode is used to interface with
external 8259As. When the 8259A is externally attached to 80186, the
80186 microprocessors work as the master, and the 8259A works as the
slave.

e) Programmable Chip Select Unit (CSU): This built-in address decoder unit
can be programmed to produce an active low chip select signal when
the memory or port address in a specified range is sent out. This built-in
decoder is to select major blocks of memory. six memory address chip
select signals are available: lower chip selects lines LCS, upper chip
selects lines UCS, and middle chip select lines MCS 0-3 The boundary of
the lower chip select signal begin at location 00000H and the boundary
of the upper chip select signal is ends at location FFFFFH. The sizes of
the memory areas are programmable by some bits put in a control word
and wait states (0-3 waits) can be automatically inserted with the
selection of an area of memory.
 In addition to producing memory chip select signals, the 80186 can be
programmed to produce up to seven peripheral chip select signals on its
PCS0 -PCS4, PCS5/A1, and PCS6 /A2 pins. The programmable I/O area
starts at a base I/O address programmed by the user, and all seven 128-
byte blocks are contiguous.

f) Programmable DMA Unit: The DMA unit has two DMA request inputs,
DRQ0 and DRQ1. These inputs allow external devices such as disk
controllers, CRT controllers, etc. to request the use of one of the DMA
channels. For each DMA channel, the 80186 has a full 20-bit register to
hold the source address, a 20-bit register to hold the destination
address, and a 16-bit counter to keep track of how many words or bytes
have been transferred. DMA transfers can be from memory to memory,
I/O to I/O, or between I/O and memory.

g) Programmable Counter/Timers: The timer section contains three fully

programmable 16-bit timers. Timers 0 and 1 generate waveforms for
external use and are driven by either the master clock of 80186 or by an
external clock. They are also used to count external events. The third
timer, timer 2, is internally connected to the processor clock. The output
of timer 2 generates an interrupt after a specified number of clocks and
can provide a clock to the other timers.

21.Discussed the multitasking and multiprogramming terminology of

microprocessor.
Multiprocessing is the use of two or more processors working within a system.
The term also refers to the ability of a system to support more than one processor
and/or the ability to allocate tasks between them. Whereas multiprogramming is
a form of parallel processing in which several programs are run at the same time
on a uniprocessor. Since there is only one processor, there can be no true
simultaneous execution of different programs. Instead, the operating system
executes part of one program, then part of another, and so on. To the user it
appears that all programs are executing at the same time.
Multitasking refers to a system's ability to execute more than one process at a
time.
Benefits of Multiprocessing are:
a) Enhanced Synchronize: Providing a high-speed interconnect between these
multiple processors, also provides the ability to achieve better coordination
and faster interaction between related tasks.

b) Fast Operations: Depending on the type of application and tools available,

a single large job can be decomposed into several smaller tasks that can run
simultaneously for faster application time-to-completion.

c) Reduced Cost: Multiple processors share the same resources. Separate

power supply or mother board for each chip is not required. This reduces
the cost.

d) Increased Reliability: The reliability of system is also increased. The failure

of one processor does not affect the other processors though it will slow
down the machine.

e) Increased Throughput: An increase in the number of processes completes

the work in less time. It is important to note that doubling the number of
processors does not halve the time to complete the job.

22.Explain the protected virtual address mode of 80286 and show how 24 bit
physical address is generated.

PROTECTED VIRTUAL ADDRESS:-

→ The 80286 executes a fully upward-compatible superset of the 8086 instruction set in
protected virtual address mode.
→ PVAM operation of the 80286 processor provides memory management and protection
mechanisms and associated instructions.
→ The 80286 enters into protected virtual address mode from real address mode when the
PE (Protection Enable) bit of the machines status word is set with the execution of LMSW
(Load Machine Status Word) instruction
→ 80286 provides a 1-gigabyte virtual address space per task mapped into a 16-megabyte
physical address space defined by the address pin A23-A0 and B̅H̅E̅.
→ The virtual memory address space must be larger than the physical address space since
any use of an address that does not map to a physical memory location will cause a
restartable exception.
→ The protected mode uses a 32-bit pointer which consists of 16-bit selector and 16-bit
offset components.
→ The 24-bit base address of the desired segment can be obtained from the tables in
memory. The 16-bit offset will be added to the segment base address to form the physical
address.

23.How many local and global descriptors can be defined in 80286 and
explain how to access them?

GLOBAL DESCRIPTOR TABLE:-

→ GDT is abbreviation for Global Descriptor Table.
→ The GDT can hold things other than segment descriptors as well.
→ Every 8-byte entry in the GDT is a descriptor, but these descriptors can
be references not only to memory segments but also to Task State Segment
(TSS), Local Descriptor Table (LDT), or Call Gate structures in memory.
→ Multiple LDTs can be defined in the GDT, but only one is current at any
one time: usually associated with the current Task
→ While the LDT contains memory segments which are private to a specific
program, the GDT contains global segments
→ Loading a selector into a segment register automatically reads the GDT
or the LDT and stores the properties of the segment inside the processor
itself.

LOCAL DESCRIPTOR TABLE:-

→ A Local Descriptor Table (LDT) is a memory table used in the x86
architecture in protected mode and containing memory segment
descriptors, just like the GDT.
→ The address start in linear memory, size, executability, writability, access
privilege, actual presence in memory, etc.
→ LDTs are the siblings of the Global Descriptor Table (GDT)
→ Each define up to 8192 memory segments accessible to programs
→ Unlike the GDT, the zeroeth entry is a valid entry, and can be used like
any other LDT entry.
→ Also note that unlike the GDT, the LDT cannot be used to store certain
system entries: TSSs or LDTs. Call Gates and Task Gates are fine, however.

24. Bring out the architectural differences between 80386 and

Pentium processors.

80836 MICROPROCESSOR:-
→ A 32-bit microprocessor introduced by Intel in 1985.
→ The chip of 80386 contains 132 pins.
→ It has total 129 instructions.
→ It has 32 bit data bus 32 bit address bus.
→ The execution of the instructions is highly pipelined and the processor is
designed to operate in a multiuser and multitasking.
→ The address bus is capable of addressing over 4 gigabytes of physical
memory.
→ Virtual addressing pushing this over 64 terabytes of storage.
→ 80387 coprocessor is used.
→ 80386 processor is available in 2 different
versions.
 - 386DX
- 386SX

PENTIUM PROCESSOR:-
→ The name Pentium is originally derived from the Greek word pente
meaning 'five' as the series was Intel's 5th generation microarchitecture.
→ Upward compatibility has been maintained.
→ It can run all programs written for any 80x86 line, but does so at a
double the speed of fastest 80486.
→ Pentium is mixture of both CISC and RISC technologies.
→ All the prior 80x86 processor are considered as CISC processor.
→ The addition of RISC aspects lead to additional performance
improvement.
→ It uses 64 bit data bus to address memory organized in 8 banks, each
bank contains 512 MB of data.
→ Each bank can store a byte of data.
→ All these bank enable signals are active low.

25.Discuss memory management of virtual 8086 mode in 80386.

VIRTUAL 8086:-
→ In the 80386 microprocessor, virtual 8086 mode (also called virtual real mode) allows the
execution of real mode applications that are incapable of running directly in protected mode
while the processor is running a protected mode operating system.
→ It is a hardware virtualization technique that allowed multiple 8086 processors to be
emulated by the 386 chip.
→ It emerged from the painful experiences with the 80286 protected mode, which by itself
was not suitable to run concurrent real-mode applications well
→ VM86 mode uses a segmentation scheme identical to that of real mode (for compatibility
reasons), which creates 20-bit linear addresses in the same manner as 20-bit physical
addresses are created in real mode, but are subject to protected mode's memory paging
mechanism.
→ To use virtual 8086 mode, an operating system sets up a virtual 8086 mode monitor,
which is a program that manages the real-mode program and emulates or filters access to
system hardware and software resources. The monitor must run at privilege level 0 and in
protected mode
26. Draw memory read and write cycle minimum mode timing diagram of
8086.
 27. Explain 80486 architecture in detail with a suitable diagram.

80486 is a 32-bit microprocessor. It is the upgraded version of 80386. One of the

most obvious features included in 80486 is a built-in math coprocessor. This
coprocessor is essentially the same as the 80387-processor used with an 80386
but being integrated on the chip allows it to execute math instructions about
three times as fast as an 80386/387 combination. 80486 is an 8 KB code and data
cache.

The 80486 processor integrated the floating-point unit (FPU) on chip, thus
eliminating overhead of the communication protocol that resulted from using a
coprocessor. The on chip FPU substantially increased the performance in the
80486 processor. The FPU's microarchitecture was based on a partial multiplier
array and a shift-and-add data path controlled by microcode. Floating point
operations could not be pipelined with any other floating-point operations; that
is, once a floating-point instruction is invoked, all other floating-point instructions
freeze until its completion.
 28. Described the register details of 80386 microprocessor.
It consists of the following registers:

o Eight 32-bit General Purpose Registers: The 80386 has eight 32-bit
general purpose registers which can also be used as either 8-bit or
16-bit registers. These 32-bit general purpose registers are known as
extended registers and are represented by the register name with
prefix E. These registers are EAX, EBX, ECX, EDX, ESI, EDI, EBP, and
EBP. AX, BX, CX, and DX represent the lower 16-bit of the 32-bit
registers EAX, EBX, ECX, and EDX whereas BP, SP, SI, and DI represent
the lower 16-bit of their 32-bit counterparts and can be used as
independent 16-bit registers.

o One 32-bit Flag Register: The flag register of 80386 is a 32-bit

register. Out of the 32 bits, Intel has reserved bits D18 to Dai, Ds and
D3, while D, is always set at 1. Two extra new flags are added to the
80286 flag to derive the flag register of 80386. They are VM (Virtual
Mode Flag) and RF (Resume Flag) flags.

o Six Segment Register: These registers are not available for

programmers; rather they are internally used to store the descriptor
information, such as attributes, limit and base addresses of
segments. The six- segment registers have corresponding six 73-bit
descriptor registers. Each of them contains 32-bit base address, 32-
bit base limit and 9-bit attributes. These are automatically loaded
when the corresponding segments are loaded with selectors.

o Four Control Register: The 80386 has three 32-bit control registers,
CRO, CR2, and CR3 to hold global machine status independent of the
executed task. Load and store instructions are available to access
these registers.
 o Four Memory Management Register: Four special registers are
defined to refer to the descriptor tables supported by 80386. The
80386 supports four types of descriptor table, viz. Global Descriptor
Table (GDT), Interrupt Descriptor Table (IDT), Local Descriptor Table
(LDT) and Task State Segment Descriptor (TSS).

o Eight Debug Register: Intel has provided a set of 8 debug registers for
hardware debugging. Out of these eight registers, DR, to DR7, two
registers DR, and DR, are Intel reserved. The initial four registers DR,
to DR3 store four program controllable breakpoint addresses, while
DR, and DR, respectively hold breakpoint status and breakpoint
control information. Two more test registers are provided by 80386
for page caching, namely test control and test status register.

29. Explain the 80286-microprocessor pin function.

Microprocessor 80286 consists of 68 pins which are packaged in PLCC. Most of

these pins are the same as that of 8086 and that of 80186. In this microprocessor
the address and the data bus are not multiplexed. The following section discusses
the new signals introduced in 80286.
⮚ S₁, S0 (Status signals): These two signals along with the M/IO are decoded
by an external hardware (82288 bus controller) to produce the control
signals read, write and the interrupt acknowledge. This is the same as the
maximum mode of 8086.

⮚ PEREQ (Processor Extension Request): This is an input signal which tells the
microprocessor to perform a data transfer operation either from memory
or from IO for the requesting coprocessor like 80287.

⮚ PEACK- (Processor Extension Acknowledge): This is an active low output

signal which is generated in response to the PEREQ signal to the
coprocessor. Microprocessor 80286 sends this signal to the coprocessor,
when it is ready to perform the data transfer operation.
 ⮚ BUSY-: This signal is the same as that of TEST signal of 8086. It is an active
low input signal to the processor. When the 80286 executes a WAIT
instruction, it will remain in wait state until it finds the BUSY signal high. So
it gives the information to the processor that up to when it has to be in the
wait state.

⮚ ERROR-: It is an active low input signal to the processor. It is asserted by the

coprocessor when the coprocessor comes across some error while
executing some operation. In response to the ERROR signal, microprocessor
do a type 16H interrupt. The interrupt service routine will then handle that
error.

30. Mentioned local, global and interrupt descriptor table registers

instruction.

INTERRUPT DESCRIPTOR TABLE:-

→ The Interrupt Descriptor Table (IDT) is a data structure used by the x86 architecture to
implement an interrupt vector table
→ The IDT is used by the processor to determine the correct response to interrupts and
exceptions.
→ Use of the IDT is triggered by three types of events: hardware interrupts, software
interrupts, and processor exceptions, which together are referred to as interrupts
→ The IDT consists of 256 interrupt vectors–the first 32 (0–31 or 0x00–0x1F) of which are
used for processor exceptions
SAME AS Q.23

31. Explain pipeline and paging unit concept of 80386.

PAGING UNIT:-
→ The paging unit operates only in protected mode and it changes the linear address into a
physical address.
→ The segmentation unit controls the action of the paging unit, as the segmentation unit
has the ability to convert the logical address into the linear address at the time of executing
an instruction.
→ Basically, it changes the overall task map into pages and each page has a size of 4K.
→ This allows the handling of tasks in the form of pages rather than segments.
→ The paging unit supports multitasking. This is so because the physical memory is not
required to hold the whole segment of any task.
→ Despite this, only that part of the segment which is needed to be currently executed must
be stored in that memory whose physical address is calculated by the paging unit
→ This resultantly reduces the memory requirement and hence this frees the memory for
other tasks.

PIPELINE:-
→ The process of fetching the next instruction when the present instruction is being
executed is called as pipelining
→ Pipelining has become possible due to the use of queue. BIU (Bus Interfacing Unit) fills in
the queue until the entire queue is full
→ The Pipeline has three stages fetch, decode and execute.
→ In this stage the ARM processor fetches the instruction from the memory. In the third
cycle the processor fetches instruction 3 from memory, decodes instruction 2 and executes
instruction 1.

32. Describe main features of 80186, 80286, 80386, 80486 and Pentium processor.

FEATURES OF 80186:-
→ The 80186 contains 16 – bit data bus
→ The internal register structure of 80186 is virtually identical to the 8086
→ About the only difference is that the 80186 contain additional reserved interrupt vectors
and some very powerful built-in I/O features
→ The internal clock generator replaces the external 8284A clock generator
→ The timer section contains three fully programmable 16-bit timers
→ The programmable DMA unit contains two DMA channels, or four DMA channels in some
models
→ The chip selection is a built-in programmable memory and I/O decoder
→ The power save feature allows the system clock to be divided by 4, 8, or 16 to reduce
power consumption

FEATURES OF 80286:-
→ The 80286 microprocessor is an advanced version of the 8086 microprocessor that is
designed for multi user and multitasking environments
→ The 80286 addresses 16 M Byte of physical memory and 1G Bytes of virtual memory by
using its memory-management system
→ The 80286 doesn’t incorporate internal peripherals; instead it contains a memory
management unit (MMU)
→ The 80286 operates in both the real and protected modes
→ In the real mode, the 80286 addresses a 1MByte memory address space and is virtually
identical to 8086
→ In the protected mode, the 80286 addresses a 16MByte memory space
→ The clock is provided by the 82284 clock generator, and the system control signals are
provided by the 82288 system bus controller

FEATURES OF 80386:-
→ The 80386 microprocessor is an enhanced version of the 80286 microprocessor and
includes a memory-management unit is enhanced to provide memory paging
→ The 80386 also includes 32-bit extended registers and a 32-bit address and data bus
→ The 80386 has a physical memory size of 4GBytes that can be addressed as a virtual
memory with up to 64TBytes
→ The 80386 is operated in the pipelined mode, it sends the address of the next instruction
or memory data to the memory system prior to completing the execution of the current
instruction
→ Interrupts, in the 80386 microprocessor, have been expanded to include additional
predefined interrupts in the interrupt vector table
→ The 80386 is also capable of paging
→ The instruction set of the 80386 is enhanced to include instructions that address the
32-bit extended register set

FEATURES OF 80486:-
→ The 80486 microprocessor is an improved version of the 80386 microprocessor that
contains an 8K-byte cache and an 80387 arithmetic co processor; it executes many
instructions in one clocking period
→ The 80486 microprocessor executes a few new instructions that control the internal
cache memory
→ A new feature found in the 80486 in the BIST (builtin self-test) that tests the
microprocessor, coprocessor, and cache at reset time
→ Additional test registers are added to the 80486 to allow the cache memory to be tested
→ These new test registers are TR3 (cache data), TR4 (cache status), and TR5 (cache control)

FEATURES OF PENTIUM PROCESSOR:-

→ The Pentium microprocessor is almost identical to the earlier 80386 and 80486
microprocessors
→ The main difference is that the Pentium has been modified internally to contain a dual
cache (instruction and data) and a dual integer unit
→ The Pentium also operates at a higher clock speed of 66 MHz
→ The data bus on the Pentium is 64 – bits wide and contains eight byte-wide memory
banks selected with bank enable signals
→ Allows 4MByte memory pages instead of the 4KByte pages
→ Memory access time, without wait states, is only about 18 ns in the 66 MHz Pentium

33. Describe the control word,tag word and status word structure of microprocessor
80386.
34. Discussed virtual and real mode of 80x86 microprocessors

VIRTUAL MODE:-
SAME AS Q.25
REAL MODE:-
 35. Explain pipelining and paging concept of 80386 microprocessor
SAME AS Q.31
36. Discussed operating modes of 80486 microprocessors
37.Describe features of Pentium processor
SAME FROM Q.32
38.Discuss the branch prediction logic of Pentium processor?

BRANCH PREDICTION LOGIC:-

→ Pentium uses a scheme called Dynamic Branch Prediction. In this scheme, a prediction is
made for the branch instruction currently in the pipeline.
→ The prediction will either be taken or not taken.
→ If the prediction is true then the pipeline will not be flushed and no clock cycles will be
lost.
→ If the prediction is false then the pipeline is flushed and starts over with the current
instruction.
→ It is implemented using 4 way set associated cache with 256 entries. This is called Branch
Target Buffer (BTB).

Working of Branch Prediction:

a) BTB is a lookaside cache that sits to the side of Decode Instruction(DI) stage of 2
pipelines and monitors for branch instructions.
b) The first time that a branch instruction enters the pipeline, the BTB uses its source
memory to perform a lookup in the cache.
c) Since the instruction was never seen before, it is BTB miss. It predicts that the branch
will not be taken even though it is unconditional jump instruction.
d) When the instruction reaches the EU(execution unit), the branch will either be taken
or not taken. If taken, the next instruction to be executed will be fetched from the
branch target address. If not taken, there will be a sequential fetch of instructions.
e) When a branch is taken for the first time, the execution unit provides feedback to the
branch prediction. The branch target address is sent back which is recorded in BTB.
f) A directory entry is made containing the source memory address and history bit is set
as strongly taken.

39.Explain the integer pipeline stages for Pentium processor.

PIPELINE STAGES:-
→ Pentium uses a 5 stage pipeline with the following stages in the pipeline.
a) Prefetch stage:
- Pentium instructions are variable length and are stored in a prefetch buffer.
There is a 256 bit path from instruction cache to the prefetch buffer.
b) Decode 1 stage:
- In this stage the processor decodes the instruction and finds the opcode and
addressing information, check which instructions can be paired for
simultaneous execution and participates in branch address prediction.
c) Decode 2 stage:
- Addresses for memory reference are found in this stage.
d) Execute stage:
- Data cache fetch or ALU or FPU operation is carried out. Two operations can be
carried out at this stage.
e) Write back stage:
- In this stage the registers and flags are updated on the basis of the results of
execution

40.Different between Pentium processor versions, Pentium; Pentium pro; Pentium P6.