Chapter 5

Combinational Circuits
Combinational Circuits

2
Binary Adder
Remember

Half adder

full adder

3
Binary Half Adder
x y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

4
 Binary Full Adder
A B Cin Cout S
0 0 0 0 0 S:
0 0 1 0 1 Cin 0 1
0 1 0 0 1 AB
00
0 1 1 1 0 1
1 0 0 0 1 01 1
1 0 1 1 0
1 1 0 1 0 11 1
1 1 1 1 1
10 1
Maps for the Full Adder Outputs
S = A‘B‘Cin + A‘BC’in+ AB‘Cin' + ABCin
= A  B  Cin
5
 Binary Full Adder
A B Cin Cout S
C:
0 0 0 0 0 Cin 0 1
0 0 1 0 1 AB
0 1 0 0 1 00

0 1 1 1 0 01 1
1 0 0 0 1
1 0 1 1 0 11 1 1
1 1 0 1 0
1 1 1 1 1 10 1

Maps for the Full Adder Outputs

C = AB+ACin +BCin = A‘BCin +AB‘Cin +ABCin’+ABCin

= (A‘B+AB')Cin +AB(Cin +Cin’) = AB + (A  B)Cin

6
 Exclusive OR Gate
a
ab
b
F = (a  b)  c
c Remember

a
G = a (b  c)
b bc
c

F = (a  b)  c
Similarly:
= (a'b + ab')  c
G = a (b  c)
= (a'b + ab')'c + (a'b + ab')c' = a'b'c + a'bc' +
= (a'b)'(ab')'c + (a'b + ab')c' ab'c' + abc
= (a + b')(a' + b)c + (a'b + ab')c'
= abc + a'b'c + a'bc' + ab'c'
7
 Binary Full Adder

Implementations of Full Adder in Sum of Products

8
 Binary Full Adder
Cin

A S = (A  B)Cin
AB
B
(A  B)Cin
AB Cout

Implementations of Full Cout = AB + (A  B)Cin

Adder with:
2 Half Adders and an
OR Gate

9
 Binary Adder
 Binary adder that produces the arithmetic
sum of binary numbers can be constructed
with full adders connected in cascade, with
the output carry from each full adder
connected to the input carry of the next full
adder in the chain
 Note that the input carry C0 in the least
significant position must be 0. (Except
when add with carry is needed)
10
 4 bit Binary Adder

Carry:1 1 1 1
The output carry (C4) is not ready
until it propagates through all of A 0 1 1 1
the full adders. This is called +
B 1 1 0 1
ripple carry, delaying the addition
process.
S 1 1 0 0 11
12
 Carry Look Ahead
A3 B3 A2 B2 A1 B1 A0 B0

C0
A B Cin A B Cin A B Cin A B Cin

Cout S Cout S Cout S Cout S

C4 C3 C2 C1
S3 S2 S1 S0

Recall from Slide 6 that: Cout = AB + (A  B)Cin = G + PCin

i.e. Ci+1 = AiBi + (Ai  Bi)Ci = Gi + PiCin
generate
Thus: propagate

C1 = A0B0+ (A0  B0)C0 = G0 + P0C0

C2 = G1 + P1C1 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0
C3 = G2 + P2C2 = G2 + P2(G1 + P1G0 + P1P0C0)
= G2 + P2G1 + P2P1G0 + P2P1P0C0
C4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0 13 13
Logic Diagram of Carry lookahead Generator

14
G=AB
P= AB
and
C4 = G3 + P3G2 +
P3P2G1 + P3P2P1G0
+ P3P2P1P0C0

Note that C4 doesn't

depend on C1, C2, C3

4 Bit Adder with Carry lookahead Generator 15

 Binary Subtractor
 The subtraction: A – B can be done by
taking the 2’s complement of B and adding
it to A because A - B = A + (-B)
= A + 2B
= A + 1B + 1
 It means if we use inverters to get 1’s
complement of B (connecting each Bi to an
inverter) and then add 1 to the least
significant bit (by setting carry in C0 to 1) of
the binary adder, then we can make a binary
subtractor. 16
4 bit 2’s complement Subtractor

17
 Adder Subtractor
 The addition and subtraction can be
combined into one circuit with one common
binary adder (see next slide).
 The mode M controls the operation. When
M = 0 the circuit is an adder when M = 1 the
circuit is a subtractor. It can be done by
using an exclusive-OR for each Bi.
 Note that 1 ⊕ x = x'
and 0 ⊕ x = x
18
Adder Subtractor

4-Bit Adder Subtractor

19
 Checking Overflow
 Note that in the previous slide if the numbers
considered to be added are signed, V detects
overflow. V = 0 means no overflow and V = 1
means the result is wrong because of overflow
 Overflow can happen when adding two numbers
of the same sign (both negative or both positive)
and result can not fit within the available bits. It
can be detected by observing the carry into the
sign bit and carry out of the sign bit position. If
these two carries are not equal an overflow has
occurred. That is why these two carries are
applied to an exclusive-OR gate to generate V.
20
 BCD Addition
 Just like binary addition but with an
extra step, if the result is greater than 9:
 we generate a carry
 and add 6 to skip the unused numbers
 Example:
0111 + 0101 = 1100
1100 + 0110 = 10010
i.e. C = 1, and S = 0010
21
 BCD Addition
Remember

so BCD addition
is done by adding
0110 to Binary
addition

1 0000
1 0001
1 0010
1 0011
1 0100
1 0110
22
BCD Addition

23
 BCD Addition

It can be seen that a 4-bit binary adder is used

initially to add two BCD digits (each digit expressed
using 4 bits) with a carry-input.

An overflow detection circuit is used (to check if the

‘Sum’ of the BCD digit has exceeded 9) which is
designed using two 2-input AND gates and a 3-input
OR gate.

Finally, another 4-bit binary adder is used as a

correction stage, which comes in the path of final
Sum computation.

24
BCD Addition

25
 correction stage,

BCD Adder
26
 Magnitude Comparator
 It is a combinational circuit that compares two
numbers and determines their relative magnitude
 The output of comparator is usually 3 binary
variables indicating:
A>B
A=B
A<B
 It is simple to design a one bit comparator:

27
 Magnitude Comparator
A B E(A=B) LT(A<B) GT(A>B)
0 0 1 0 0
0 1 0 1 0
1 0 0 0 1
1 1 1 0 0

LT = A<B = A’B
GT = A>B = AB’

28
 1-Bit Comparator
A’B
A LT A < B

E A=B

B
AB’ GT A > B

A 4-bit comparator can be built using 4 1-bit

comparators with additional logic

29
 4 Bit Comparator
 A is equal to B if all 4 bits are equal.
 A is greater than B if:
 The MSB of A is greater then the MSB of B
 Or the MSBs of A and B are equal and the
second MSB of A is greater then the
second MSB of B
 Etc…

30
 4 Bit Comparator
 Assume Ei =1if Ai = Bi
 Remember A>B if AB’
 GT = A3 B3’ + E3A2 B2 ‘ + E3 E2A1 B1‘ +
E3E2E1A0B0‘
 Remember A<B if A’B
 LT = B3 A3‘+ E3B2 A2‘+ E3 E2B1 A1‘+
E3E2E1B0A0‘

31
4 Bit
Comparator 32
 Encoder
 encoder Generates a unique binary code for the
active line from several input lines.
 Generally encoders produce 2-bit code (for 4
inputs), 3-bit code (for 8 inputs). An n bit encoder
has 2n input lines

D3 D2 D1 D0 A B
D0
B 0 0 0 1 0 0
D1 0 0 1 0 0 1
D2 0 1 0 0 1 0
A
D3
1 0 0 0 1 1
33
 2-bit Priority Encoder
 If one of the four input lines is active the encoder produces
the binary code corresponding to that line
 If more than one of the input lines is active the encoder
produces the binary code corresponding to the higher line.
 The Truth table of a 2-bit priority encoder is given below.
This time a validity output is provided to take care of the
case when none of the inputs is active, V = D0+D1+D2+D3
y D3 D2 D1 D0 x y V
D0
0 0 0 0 x x 0
D1 0 0 0 1 0 0 1
x
D2 0 0 1 x 0 1 1
D3 V 0 1 x x 1 0 1
1 x x x 1 1 1
34
 D1 D0 D1 D0
00 01 11 10 00 01 11 10
D3 D2 D3 D2
00 x 00 x 1 1

1 1 1 1
01 01
1 1 1 1 1 1
11 1 1
11
1 1 1 1 1 1 1 1
10 10

x = D3 + D2 and y = D3 + D1D’2

K-Maps for the 2-bit priority Encoder

35
4-Input Priority Encoder 36
Decimal to Binary or BCD Encoder

0 A
1
2 Decimal
B
- to BCD
- Encoder C
-
D
9

37
Decimal to Binary or BCD Encoder
Decimal A3 A2 A1 A0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

A3=8+9 A2=4+5+6+7
A1=2+3+6+7 A0=1+3+5+7+9 38
Decimal to Binary or BCD Encoder

Why no zero?
39
 Decoder
 Decoder performs the inverse function of Encoder.
 Decoder is a combinational circuit that converts
binary information from n input lines to a maximum
of 2n unique output lines For example if the number
of input n = 3 the number of output lines can be m
=23 = 8. The diagram below shows a 3X8 decoder:

3X8
Decoder

40
 Decoder Truth Table
x y z D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 1 0 0

0 1 1 0 0 0 0 1 0 0 0

1 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 1 0 0 0 0 0

1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0

41
 From Minterms

3-to-8-Line Decoder 42
 Decoder with Enable Line
 Decoders usually have an enable line.
 If enable = 0 , decoder is off. It means all output
lines are zero
 If enable = 1, decoder is on and depending on
input, the corresponding output line is 1, all other
lines are 0
D0=EX’Y’ E X Y D3 D2 D1 D0
2X4 0 x x 0 0 0 0
D1=EX’Y
Y Decoder 1 0 0 0 0 0 1
D2=EXY’ 1 0 1 0 0 1 0
X 1 1 0 0 1 0 0
D3=EXY
1 1 1 1 0 0 0

E 2X4 Decoder with Enable

43
2X4 Decoder with Enable (Active low)
44
 Major applications of Decoder
 To activate one out of many.
 To implement any combinational function ( F) For
example the expressions for a full adder are:
S(x,y,z) = ∑ (1,2,4,7) and
C(x,y,z) = ∑ (3,5,6,7).
A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1 45
 Multiplexers
 A multiplexer is a combinational circuit that
selects binary information from the input lines
and directs it to the output line (data selector)

N input data line Single output

MUX

selectors 46
 MultiplexerS
 Usually there are 2n input lines and n
selection lines whose bit combinations
determine which input line is selected
 For example for 2-to-1 multiplexer if selection
S is zero then I0 has the path to output and if
S is one I1 has the path to output (see the
next slide)
 Types of MUX
2x1 Mux, 4x1 MUX, 8x1 Mux, 16x1, 32x1

47
 2-to-1 multiplexer

0
I0
2X1 Y
I1 MUX
1

Logic Diagram Block Diagram

S Y
0 I0
Y= I0 S’+ I1 S1
1 I1
48
 I0
0
I1 Y
1
4X1
I2
2 MUX
I3 3

S1 S0

4X1 Multiplexer and its Truth Table

Y=s0’s1’I0+s0 s1’ I1+s0’s1I2+s0s1 I3 49
 MUX, Functionally Complete!

NOT gate using MUX

X F
0 1
1 0

50
 MUX, Functionally Complete!

AND gate using MUX

X Y F
0 0 0
0 1 0
1 0 0
1 1 1

Note: if you want to get F=x.y put z=1

51
 MUX, Functionally Complete!

OR gate using MUX

X Y F
0 0 Z
0 1 1
1 0 1
1 1 1

Note: if you want to get F=x+y put z=0

52
 Boolean function Implementation

 Another method for implementing Boolean

functions is using multiplexers
 For implementing a Boolean function that has
n variables with a single multiplexer, we have
to use a multiplexer with n-1 selection lines.
 The first n-1 variables of the function are
used for data input selection.
 The remaining single variable is used for data
input. Each data input can then be that
variable, its complement, 1, or 0.

53
Example 1 Implement the following function
using single MUX

F(x,y,z) = ∑(1,2,6,7)

•F(x,y,z) = ∑(1,2,6,7)
•No of variables =3.
•Then number of selection lines=n-1=2
• X, Y are the selectors
• Then use MUX 4x1

54
F(x,y,z) = ∑(1,2,6,7)

55
Example 2 Implement the following function
using single MUX

F(A,B,C,D) = ∑(1,3,4,11,12,13,14,15)

No of variables =4.
Then number of selection lines=n-1=3
Selectors A,B,C
Then use MUX 8x1

56
F(A,B,C,D) = ∑(1,3,4,11,12,13,14,15)

57
 Demultiplexers (DEMUX)
A demultiplexer (DEMUX) reverses the multiplexing function. It
takes digital information from one line and distributes it to a given
number of output lines.
For this reason, the demultiplexer is also known as a data distributor.

DEMUX
D0

I D1

D2

D3

A l-line-to-4-line
demultiplexer:
S1 S0 58 58
 Demultiplexers (DEMUX)
S1 S0 D3 D2 D1 D0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0

For the above Figure:

D0 = S1S0I
D1 = S1S0I
D2 = S1S0I
D3 = S1S0I

59 59
 Demultiplexers (DEMUX)
Data
I
Input D0

D1 Data
S0 Output
Select Lines
D2
Lines
S1
D3

Compare the above with outputs of a decoder with enable of slide 26:
D0 = EX'Y'
D1 = EX'Y
D2 = EXY'
D3 = EXY
Thus a DEMUX is a decoder with an enable 60 60
 Three-State Gates
 Three state gates exhibit three states instead
of two states. The three states are:
 high : 1
 Low : 0
 High impedance : In this state the output is
disconnected, i.e. an open circuit. In other words
in this state the circuit has no logic significance.
We can have AND or NAND tri-state gates but
the most common is tri-state buffer gate
 Note that a buffer is a transfer device and
can be used for power amplification. Tri-state
buffer has an extra input control line.
61
 Three-state buffer

C A Y
0 X Z
1 0 0
1 1 1

Truth table and diagram of a tristate buffer

62
Tri-state buffers can be used to Build:
implement a multiplexer

2X1 Multiplexer with Tri-state Buffers

63
Implement 4x1 MUX using decoder and Tri-state buffer

4X1 Multiplexer with Tri-state Buffers 64