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Nahin Ul Sadad
Lecturer
CSE, RUET
Adder Overview
Half Adder
X Y C S
0 0 0 0 X
Y S
X S 0 1 0 1
HA
Y C 1 0 0 1 C
1 1 1 0
S = X Y + X Y = X Y
C = X Y
Adder Overview
Full Adder
X Y Z C S
0 0 0 0 0
X S 0 0 1 0 1
Y FA S = X Y Z +X Y Z +X Y Z +X Y Z
Z C 0 1 0 0 1
C = X Y +X Z +Y Z
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Adder Overview
Adder circuit simplification
Adder Overview
Adder circuit simplification
X
Y S
C
Z
S = X Y Z
C = X Y + (X Y ) Z
X
S
Adder Overview Y
Full Adder C
Z
X Y Z C S
0 0 0 0 0
X S 0 0 1 0 1 S = X Y Z +X Y Z +X Y Z +X Y Z
Y FA C = X Y +X Z +Y Z
C 0 1 0 0 1
Z
0 1 1 1 0 S = X Y Z
1 0 0 0 1 C = X Y + (X Y ) Z
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Adder Overview
Full Adder
X S A S
Y FA B FA
Z C C1 C2
C5 S4 S3 S2 S1 B3 A3 B2 A2 B1 A1 B0 A0
FA FA FA FA C0
C4 C3 C2 C1
S3 S2 S1 S0
4-bit Parallel Adder!
Unsigned Subtraction
Q: How can we build 2-bit/4-bit/…32-bit subtractor
(unsigned)?
D= A B + A B = A B
C = A B
Full Subtractor
A B Bin D Bout
0 0 0 0 0
A D D = A B Bin + A B Bin + A B Bin + A B Bin
0 0 1 1 1
B FS Bout = A B Bin + A B Bin + A B Bin + A B Bin
Bin Bout 0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Full Subtractor
D = A’B’Bin + A’BBin’ + AB’Bin’ + ABBin
= Bin(A’B’ + AB) + Bin’(AB’ + A’B)
= Bin( A XNOR B) + Bin’(A XOR B)
= Bin (A XOR B)’ + Bin’(A XOR B)
= Bin XOR (A XOR B)
= (A XOR B) XOR Bin
A B Bin D Bout
0 0 0 0 0
A D D = A B Bin + A B Bin + A B Bin + A B Bin
0 0 1 1 1
B FS Bout = A B Bin + A B Bin + A B Bin + A B Bin
Bin Bout 0 1 0 1 1
0 1 1 0 1 D = A B Bin
1 0 0 1 0 Bout = Bin (AB) + A B
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Q: How can we build 2-bit/4-bit/…32-bit unsigned
subtractor?
A:
B3 A3 B2 A2 B1 A1 B0 A0
FS FS FS FS BR0
BR4 BR3 BR2 BR1
D3 D2 D1 D0
Signed Subtraction
Q: What are the limitations of Unsigned subtractor (built using
half-subtractor and full-subtractor)?
A:
1. It cannot calculate signed subtraction like -4-2 etc. (For adders,
there is no difference between signed and unsigned adders.)
When MSB = 0,
No of positive values = 𝟐𝒏−𝟏
Rage of positive values = 𝟐𝒏−𝟏 to 𝟎
When MSB = 1,
No of negative values = 𝟐𝒏−𝟏
Rage of negative values = −𝟐𝒏−𝟏 to −𝟏
A:
1. Calculate binary representation of its positive number:
4 10 = 0100 2
2. Calculate 1’s complement: It means flipping/inverting its bits
0100 → 1011 (Flipping its bits)
3. Calculate 2’s complement: It means adding 1 to its 1’s complement
result
1011
+1
1100
Q: How can to calculate equivalent decimal value (For example :
1100) using 2’s complement?
A: Just Perform 2’s complement operation!
2.
0100
1101
0001
Carry = 1 (Ignore It)
2.
1100
0011
1111
2.
1100
1011
0111
Carry = 1
2.
0100
0101
1001
Carry = 1
𝟎 A
𝟎 S 𝟏
𝟏 B FA
𝟏 C1 C2 𝟎
FA FA FA FA C0=1
C4 C3 C2 C1
S3 S2 S1 S0
Q: How can we combine addition and subtraction in
same Adder circuit?
A: Using XOR gate!
XOR is also called Programmable Inverter!
If 𝐴 = 0, 𝑍 = 𝐵
If 𝐴 = 1, 𝑍 = ~𝐵
4-bit Parallel Adder/Subtractor
4-bit Parallel Adder/Subtractor
=0
𝑴 ⊕ 𝑩𝒏
B3 B2 B1 B0 ഥ 𝑩𝒏
= 𝑴. 𝑩𝒏 + 𝑴.
ഥ 𝒏
= 𝟎. 𝑩𝒏 + 𝟎𝑩
= 𝑩𝒏
4-bit Parallel Adder/Subtractor
=1
𝑴 ⊕ 𝑩𝒏
~B3 ~B2 ~B1 ~B0 ഥ 𝑩𝒏
= 𝑴. 𝑩𝒏 + 𝑴.
ഥ 𝒏
= 𝟏. 𝑩𝒏 + 𝟏𝑩
= 𝑩𝒏
Q: What are the limitations of parallel adder/subtractor?
A: Parallel adder/subtractor is very slow. Because:
4th FA has to wait for 3rd FA has to wait for 2nd FA has to wait for
3rd FA to get value of C3 2nd FA to get value of C2 1st FA to get value of C1
Which is waiting for Which is waiting for
2nd FA to get value of C2 1st FA to get value of C1
Which is waiting for
3rd FA to get value of C1 So, Parallel Adder/Subtractor is slower!
Q: How can we solve this problem?
A: We can use another variant of Parallel
adder which is called
Carry Look Ahead Adder!
A: First consider simple 2-bit Parallel Adder
B1 A1 B0 A0
FA FA C0
C2 C1
S1 S0
An
Bn S S = An Bn Cn-1
Cn Cn = An Bn + ( An Bn) Cn-1
Cn-1
Let,
Gn = An Bn
CLA
Pn = An Bn
Cn = Gn + Pn Cn-1
B1 A1 B0 A0
FA FA C0
C2
Gn = An Bn
P1 G1 S1 C1 P0 G0 S0 Pn = An Bn
C2 2-bit Carry Look Ahead C0 Cn = Gn + Pn Cn-1
Generator
A: Similarly 2-bit Parallel Adder/Subtractor
B1 A1 B0 A0
XOR XOR
FA FA C0
C2
Gn = An Bn
P1 G1 S1 C1 P0 G0 S0 Pn = An Bn
C2 2-bit Carry Look Ahead C0 Cn = Gn + Pn Cn-1
Generator
Similarly, Create 4-bit Carry Look Ahead
Adder/Subtractor!
Example: Adder
Question: Design a 4 bit signed adder (normal) and show output of each circuit in when X = 1001 and Y= 1111.
Answer:
X Y
X Y Z C S
0 0 0 0 0 X
0 0 1 0 1 S
Y X Y
0 1 0 0 1
0 1 1 1 0 C C FA Z Z
1 0 0 0 1 C S
1 0 1 1 0
1 1 0 1 0 Z
1 1 1 1 1 Figure: 1-bit Full Adder Circuit S
Figure: 1-bit Full Adder Chip
S = X Y Z +X Y Z +X Y Z +X Y Z
C = X Y +X Z +Y Z
S = X Y Z
C = X Y + (X Y ) Z
Example: Adder
1 1 0 1 0 1 1 1
X3 Y3 X2 Y2 X1 Y1 X0 Y0
X Y X Y X Y X Y
1 1 1
1 C FA Z C FA Z C FA Z C FA Z C0
C4 C3 C2 C1 0
S S S S
S3 S2 S1 S0
1 0 0 0
Figure: 4-bit Full Adder Circuit with output when X=1001 and Y=1111
Exercises
1. Consider
X = 11011/1111/110/11 (5-bit/4-bit/3-bit/2-bit)
Y = 11011/1111/110/11 (5-bit/4-bit/3-bit/2-bit)
i. Calculate X+Y (Unsigned/Signed)
ii. Calculate X-Y (Unsigned/Signed)