Linear block codes

and cyclic codes

Chapter-2
(Part-3)

Dr. Anjaneyulu Pattem

 Cyclic codes

2.11 Hamming codes

2.12 Shortened cyclic code
2.13 Error trapping decoding
2.14 Improved error trapping decoding
2.15 Golay code

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 2.11 Hamming codes

For any positive integer, m , m ≥3, there exists

Hamming codes with the following properties:
of length, n = 2m -1,
information symbols, k = 2m –m-1
Number of parity check symbols, n-k = m
Error correcting capability, t =1 (dmin =3)

The algebraic structure of parity check matrix, H in

systematic form is given as :
Let H = [ Im Q ], where Im is an identity matrix, and Q is [m
x (2m –m-1)].

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 Hamming codes

For example, for m=3, for linear (7,4) Hamming code, H is

given as

H= [ 1001011
0101110
0010111 ]
With reference to parity check matrix, H, generator matrix ,
G can be obtained as detailed in the linear block codes.
Also the error detection, syndrome computation, and error
corrections are as detailed in the linear block codes.
Perfect single error correcting Hamming codes can be
obtained using the algebraic structure of these codes.
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 shortened Hamming codes

For example using standard arry and decoding tables, perfect

single error correcting procedure is described in the earlier
sections.
Some number of columns can be deleted in H, and the
resultant code is called as shortened Hamming code of
minimum distance, 4.
For example if we delete, all the columns of even weight, we
can obtain a Hamming matrix, H’, from which shortened
Hamming code can be obtained.
Eventhough minimum distance is 4, these codes are
applicable for single error correction and double error
detection.

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 shortened Hamming codes

Based on the algebraic structure of these shortened Hamming

codes with minimum distance , 4, these codes can be used
for correcting all error patterns of single error, and
simultaneously detecting all error patterns of double
errors.
Based on the error pattern, occurred in the transmission, the
following decoding procedure can be used:
1. If syndrome, s, is zero, no error is occurred
2. If , s is non zero, and it contains , odd number of 1s, it
can be assumed that single error is occurred and
corresponding error correction can be applied.
3. If , s is non zero, and it contains , even number of 1s, it
can be assumed that uncorrectable error pattern has been
detected.
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 2.15 Shortened cyclic code

When l leading higher order digit positions are zeros, then

following encoding and decoding there is a wastage of
shifts in l positions. Shortening of cyclic code is required in
these situations.
There exists 2 k-l, code vectors in (n,k) cyclic code.
If the l-zero information digits are deleted from each of these
vectors, we obtain a set of 2 k-l, vectors of length (n-l).
These shortened vectors form (n-l,k-l) linear code. This
code is called as shortened cyclic code, which is not cyclic
code. This code is having atleast the same error correcting
capability as the code from which it is derived.

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 Shortened cyclic code

In the decoding if normal procedure is followed, it requires l

cyclic shifts to generate the proper syndrome, for decoding
the first received digit r n-l-1 . For large l, these shifts are
undesirable.
The normal decoder is modified for these shortend code. The
procedure is given in the following:
It can be shown that
xn-k+l r(x) = a1(x) g(x) + sn-k+l (x)
And ρ (x) = xn-k+l + a2(x) g(x)
from the above two, it can be obtained as
ρ (x) r(x) = [a1(x) + a2(x) r(x) ] g(x) + sn-k+l (x)

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Figure-21:decoder for shortened cyclic code

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 Shortened cyclic code

If sn-k+l (x) is computed in this way, then the extra l shifts can
be avoided. Simultaneous multiplication and division for
the above equation can be implemented in the following
circuit.

Example:
For m=5, there exists (31, 26) cyclic Hamming code,
generated by generator polynomial, g(x) = 1+ x2 + x5.
Suppose that it is shortened by 3 digits, the resultant
shortened code is (28,23). The normal decoding for (31,26)
code is shown in the following figure.

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Figure-22:decoder for (31,26) cyclic code

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 Shortened cyclic code

This circuit can be modified to decode (28, 23) shortened

code.
ρ (x) = 1+x+ x2, can be obtained from the division of xn-k+3 =
x8, by g(x)= 1+ x2 + x5.
The modified circuit is shown in the following figure.

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Figure-23:decoder for (28,23) shortened cyclic code

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 Shortened cyclic code

The extra l shifts can also be eliminated by modifying the

error pattern detector circuit, for the decoder of the
original cyclic code circuit.
The error pattern detection circuit is to be modified such that
syndrome in the register corresponds to a correctable error
pattern e(x) with an error at location xn-l-1 (i.e. e n-l-1 =1).
When the received digit, r n-l-1 is corrected, the effect of the
error digit, e n-l-1 on the syndrome should be removed.
The modified circuit with the above considerations for the
following details of (28,23) shortened code, is shown in the
following figure.

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Figure-24: Modified decoder for (28,23) shortened
cyclic code

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 Shortened cyclic code

Shortened cyclic code = (28,23)

R(x) is entered into the syndrome register from the right end.
If single error occurs at x27 (i.e. e (x) = x27 )
Then syndrome is (0 1 0 0 0 ) from the division of x5 e(x) =x32 ,
by g(x) = 1+ x2 + x5 . The error pattern detection circuit is
modified to check whether the syndrome is (0 1 0 0 0) . A
decoder with the above modifications is shown in the figure
above.

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 2.12 Error trapping decoding

When the received vector is corrupted, it has been shown that

the syndrome is given as
e(x) = a(x) g(x) + s(x), where g(x) is generator
polynomial and s(x) is syndrome of r(x).
If the errors are confined to (n-k) higher order positions, then
the error pattern is given as
e(x) = e k Xk + e k+1 Xk+1 +…… e n-1 Xn-1
Then it can be shown by cyclically shifting r(x)
Xk Sn-k = e(x) = e k Xk + e k+1 Xk+1 +…… e n-1 Xn-1 ,
This implies that if errors are confined to (n-k) highest order
positions of the received polynomial r(x), the error pattern
is identical to Xk Sn-k , where Sn-k is the syndrome of rn-k ,
which is (n-k) times cyclically shifted r(x).

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 Error trapping decoding

When this event occurs, it is to compute Sn-k , and add Xk Sn-k

to r(x) to obtain the transmitted code word.
If the errors are not confined to (n-k) higher order positions,
After r(x) has been entered into the syndrome register, the
register must be shifted must be shifted a certain number
of times, before its contents are identical to error digits.
This shifting of syndrome register until its contents are
contents identical to error digits is called as error trapping.
Once error trapping is detected for a correctable error
pattern, then the contents of the syndrome register are
added to the relevant (n-k) positions of the received vector
to obtain, corrected word.

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 Error trapping decoding

The desired error pattern is tested for the weight of the

syndrome register.
Suppose that t-error correcting cyclic code is used. Then it
can be shown that if the number of errors of r(x), and they
are confined to (n-k) consecutive positions of r(x), then the
errors are trapped in the syndrome register only when the
weight of the syndrome register is t or less.

Based on the above factors, an error trapping decoder can be

implemented as shown in Figure.

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Figure-18:Error trapping decoder

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 Error trapping decoding

Operation of the decoder:

1) The received vector is shifted into the syndrome register
and buffer register (but in buffer only k received digits are
entered).
2) The weight of the syndrome register is tested by the
threshold gate, whose output is 1, when t or fewer of its
inputs are 1, otherwise, it is 0.
a) if the weight of the syndrome is t or less, the syndrome
digits in the register are identical to the error digits at the
(n-k) high order positions. Now gates 2 and 4 are turned
on and other gates are turned off. The received vector is
read out of the buffer one digit at a time and is corrected
by the error digits shifted out from the syndrome register.
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 Error trapping decoding

b) if the weight of the syndrome is greater than t, the errors

are not confined to (n-k) high order positions, and they
have not been trapped, then go to step 3.
3) Cyclically shift the syndrome register once with gate 3 is
turned on and other gates are turned off. The weight of the
new syndrome is tested.
a) if the weight is t or less, the error digits are confined to the
locations Xk -1 to Xn-2 of r(x) , then first digit, r n-1 is read
out of the buffer, gate 4 is turned on and gate 3 is turned
off. The contents in the syndrome register are shifted out
and are used to correct next (n-k) digits to come out from
the buffer register.

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 Error trapping decoding

b) if the weight of the syndrome is greater than t, shift the

syndrome register once more with gate 3 is turned on.
4) The syndrome register is continuously shifted until the
weight of its contents go to t or less at the end of the ith
shift for i is from 1 to k, the first i received digits r n-I to r
n-1 in the buffer register are error free and the contents in
the syndrome register are at the locations x k-I to x n-i-1.
As soon as the I error free received digits have been read
out of the buffer, the contents of the syndrome register are
shifted out and are used to correct next (n-k) digits to come
out from the buffer register. When k received information
digits have been read out of the buffer and have been
corrected, gate 2 will be turned off.
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 Error trapping decoding

5) If the weight of the syndrome never goes down to t or less,

by the time of syndrome register is shifted k times, then
either error pattern of (n-k) consecutive end around
positions, or undetectable errors have occurred.

Another alternative (fast rate detectable) error decoder is as

shown in the following figure:

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Figure-19:Error trapping decoder

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 2.13 Improved error trapping decoding

When most errors are confined to (n-k) consecutive positions

and fewer errors are outside of (n-k) digit span, an
improvement in the previous decoding is required.
The error pattern e(x) can be divided into two parts as:
e(x) = e 0 + e 1 X1 +…… e n-1 Xn-1
e p(x) = e 0 + e 1 X1 +…… e n-k-1 Xn-k-1
e i(x) = e n-k Xn-k + e n-k +1 Xn-k+1 +…… e n-1 Xn-1
In the above e p(x) is the errors in the parity part, and e i(x) is
the errors in the message part in error pattern e(x).
Dividing e i(x) by the generator polynomial g(x), it can be
obtained as

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 Improved error trapping decoding

e i(x) = q(x) g(x) + ρ (x)

Where ρ (x) is the remainder in the division and is of degree
(n-k-1) or less.
Adding e p(x) to both sides
e(x) = e p(x) + e i(x) = e p(x) + q(x) g(x) + ρ (x)
It implies e p(x) + ρ (x) is the remainder in the division of e(x)
by g(x).
s(x) = e p(x) + ρ (x)
Rearranging it as
e p(x) = s(x) + ρ (x)
If e i(x) is known then the error pattern e p(x) can be
determined.
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 Kassami error decoding

Kassami error decoding procedure is consisting of

determining set of covering polynomials
[φj (x)] j=1 to N
Of degree (k-1) or less.
These polynomials satisfy that there exists one polynomial of
φj (x), matches the message section of e(x) or message
section of cyclic shift of e(x) .
Let ρj(x) be the remainder in the division of φj (x) Xn-k by
g(x).
The decoding procedure is given in the following steps:
1) After entering r(x) into the syndrome register, and from
the syndrome, s(x), calculate the weight of sum of [s(x) +
ρj(x)] for each j = 1 to N.

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 Kassami error decoding

2) If for some l, wt [s(x) + ρl(x)] ≤ t - wt [φl (x)],

then φl (x) Xn-k matches message section of e(x), and s(x) +
ρl(x), matches parity section of e(x). Correction is applied
as r(x) + e(x) with e(x) = s(x) + ρl(x) + φl (x) Xn-k
3) If for some l, wt [s(x) + ρl(x)] > t - wt [φl (x)], for all j = 1 to
N, both syndrome and buffer registers are shifted once.
Then the new syndrome, s1(x) is the syndrome corresponding
to r1(x) .
4) If for some l, wt [s1(x) + ρl(x)] ≤ t - wt [φl (x)],
then φl (x) Xn-k matches message section of e1(x), and s1(x) +
ρl(x), matches parity section of e1(x). Correction is applied
as r1 (x) + e1 (x) with e1 (x) = s1 (x) + ρl(x) + φl (x) Xn-k
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 Kassami error decoding

If for some l, wt [s(x) + ρl(x)] > t - wt [φj (x)], for all j = 1 to N,

both syndrome and buffer registers are shifted once again.
5) both syndrome and buffer registers are continuously
shifted until si(x), satisfies for some l,
wt [si(x) + ρl(x)] ≤ t - wt [φl (x)],
Where ei (x) = si (x) + ρl(x) + φl (x) Xn-k .
If the above condition is not satisfied for all j, by the time the
syndrome and buffer registers are shifted (n-1) times, it
indicates an undetectable error has occurred.

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 2.14 Golay code

Goley code is either generated by

g1(x) = ( 1 +x2 + x4 +x5 + x6+x10 + x11 )
Or by
g 2(x) = ( 1 +x + x5 + x6+x7 + x9 + x11)
Both g1(x) and g 2(x) satisfy
(x23 +1 ) = (1+x) g1(x) g 2(x)
The encoding can be done based on either of the generator
polynomials.
Two decoding procedures are given in the following to decode
(23, 12) Goley code.

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 Kassami decoder:

Kassami decoder:
This decoder follows improved error trapping technique as
described in the earlier section.
The set of polynomials chosen are
φl (x) = 0, φ2 (x) = x5 , φ3 (x) = x6,
Let g1(x) = ( 1 +x2 + x4 +x5 + x6+x10 + x11 ) be the generator
polynomial. Dividing φj (x) X11 by g1(x) for j=1,2,3, it can
be obtained the following remainder polynomials:
ρ1(x) = 0
ρ2(x) = x+x2 + x5 + x6+x8 + x9
ρ3(x) = x ρ2(x) = x2 +x3+ x6 + x7+x9 + x10

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 Kassami decoder

Let the received vector r(x) is given as

r(x) = r 0 + r 1 X1 +…… r 22 X22 and it is shifted into the
syndrome register from the right side, this is equivalent to
preshifting the received vector 11 times cyclically.
Then the syndrome in the register is corresponding to r 11 (x).
In this case the error is confined to the first 11 high order
positions, X11 to X22 of r(x), the syndrome matches the
errors in those positions.
The error correction decoder using the Kassami decoder is
shown in the following:

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Figure-20:Kassami decoder

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 Systematic search decoder:

Systematic search decoder:

The decoder is specified in the following steps:
1) Compute the syndrome from the received vector.
2) Shift the syndrome and the received vector 23 times,
checking whether wt(s(x)) falls ever to 3 or less. If it does,
the syndrome matches the correctable error pattern and
correction can be made.
3) If it does not, the first received digit is inverted, and step 2
is repeated, checking for syndrome weight of 2 or less. If
one is found, the first received information digit was
incorrect, and the other two errors are specified by
syndrome. This completes decoding.

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 Systematic search decoder:

4) If no syndrome of weight 2 or less is found in step-3, the

first information digit was originally correct. In this case,
this bit must be inverted.
5) Repeat step-3, by inverting the second, third, ……twelfth
information digits. Since not all the errors are in the parity
check section, an error must be corrected in this manner.
In every pattern of 3 or fewer errors, there is atleast one error
which, if corrected, will leave the remaining errors or
errors with in 11 successive positions. When the digit
corresponding to this error is inverted, the remaining
errors are corrected as in ordinary error trapping method.
Kassami decoder is faster operation than the systematic
search decoder.
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37