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LECTURE NINE 8086 MICROPROCESSOR MEMORY AND I/O INTERFACING

Presentation · March 2020

DOI: 10.13140/RG.2.2.36406.86085

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 University of Technology
Department of Electrical Engineering
Microprocessor Engineering
Third Class

LECTURE NINE
8086 MICROPROCESSOR
MEMORY AND I/O INTERFACING

ASSIST. PROF. D. HADEEL NASRAT ABDULLAH

 Memory and I/O Interfacing
Interface is the path for communication between two components. Interfacing
is of two types, memory interfacing and I/O interfacing.
Memory Interfacing
When we are executing any instruction, we need the microprocessor to
access the memory for reading instruction codes and the data stored in the
memory. For this, both the memory and the microprocessor requires some
signals to read from and write to registers.
The interfacing process includes some key factors to match with the memory
requirements and microprocessor signals. The interfacing circuit therefore
should be designed in such a way that it matches the memory signal
requirements with the signals of the microprocessor.

I/O Interfacing
There are various communication devices like the keyboard, mouse, printer,
etc. So, we need to interface the keyboard and other devices with the
microprocessor by using latches and buffers. This type of interfacing is known
as I/O interfacing.

Lecture 9/8086 Memory and I/O Interfacing

Assist. Prof. Dr. Hadeel N. Abdullah
 Memory and I/O Interfacing

In memory interfacing:
8 bit data line, 16 bit address line , control signals are connected to
corresponding lines of memory IC.
In I/O device interfacing:
8 bit data line, only 8 bit address line , control signals are connected to
corresponding lines of I/O devices.

LECTURE 9/8086 MEMORY AND I/O INTERFACING ASSIST. PROF. DR. HADEEL N.
ABDULLAH
 MEMORY DEVICES
 Simple or complex, every microprocessor based system has a
Memory system.
 Almost all systems contain four common types of memory:
 Read only memory (ROM)
 Flash memory (EEPROM)
 Static Random access memory (SARAM)
 Dynamic Random access memory (DRAM).

 Before attempting to interface memory to the microprocessor, it is

essential to understand the operation of memory components.

Homework: What are the differences between

1. RAM and ROM.
2. Static RAM and Dynamic RAM.

LECTURE 9/8086 MEMORY AND I/O INTERFACING

ASSIST. PROF. DR. HADEEL N. ABDULLAH
 MEMORY DEVICES
 A general form diagram of ROM and RAM show in figure below. Pin connections
common to all memory devices are:
 Address connections: All memory devices have address inputs that select a
memory location within the memory device. Address inputs are labeled (A0 –An)
 Data connections: All memory devices have a set of data outputs or
input/outputs. Today many of them have bi-directional common I/O pins.
 Selection connections: Each memory device has an input that selects or
enables the memory device. This kind of input is most often called a chip select
(CS) , chip enable (CE) or simply select (S) input

 Control connections:
The control input most
often found on the
ROM is the output
enable (OE) or gate (G)
this allows data to flow
out of the output data
pins of the ROM.

LECTURE 9/8086 MEMORY AND I/O INTERFACING

ASSIST. PROF. DR. HADEEL N. ABDULLAH
Minimum mode Memory and I/O Interfacing

Memory
and
I/O
Interfaci
ng

Block Diagram of Minimum mode Memory and I/O Interfacing

in 8086 microprocessor
 Address bus & Data bus are multiplexed on same lines (AD0 to AD15).
 During first clock cycle, it serves as a memory/ IO address bus.
 For second and third clock cycles it acts as data bus and carries data.
 Demultiplexing refers to separating Address & Data signals for read/write
operations.
LECTURE 9/8086 MEMORY AND I/O INTERFACING
ASSIST. PROF. DR. HADEEL N. ABDULLAH
 8086 Memory Organization
 The memory address space of the 8086-based microcomputers has different
logical and physical organizations.
 Logically, memory is implemented as a single 1M × 8 memory bank. The
byte-wide storage locations are assigned consecutive addresses over the
range from 00000H through FFFFFH
 Physically, memory is implemented as two independent 512 Kbyte banks: the
low (even) bank and the high (odd) bank.

(a) Logical memory organization, and (b) Physical memory organization (high and low
memory banks) of the 8086 microprocessor.
 8086 Memory Organization
 To distinguish between odd and even bytes, the CPU provides a signal called
BHE (bus high enable).
 BHE and A0 are used to select the odd and even byte, as shown in the table
below.

BHE A0 Function
0 0 Choose both odd and even memory bank
0 1 Choose only odd memory bank
1 0 Choose only even memory bank
1 1 None is chosen

Homework:
Why 8086 can read 16-bit data from an even address and 8-bit
from odd address? Explain with a block diagram and table.

LECTURE 9/8086 MEMORY AND I/O INTERFACING

ASSIST. PROF. DR. HADEEL N. ABDULLAH
 Memory expansion
 In many applications, the microcomputer system requirement for memory is
greater than what is available in a single device. There are two basic
reasons for expanding memory capacity:
1. The byte-wide length is not large enough
2. The total storage capacity is not enough bytes.
 Both of these expansion needs can be satisfied by interconnecting a number
of ICs.
Example 1: show how to implement 32K×16 EPROM using 32K×8 EPROM?
32 K X 8 bits = 215 x 8  (A0 – A14)
32K X 16 bit = 215 x 16  (A0 – A14)

LECTURE 9/8086 MEMORY AND I/O INTERFACING

ASSIST. PROF. DR. HADEEL N. ABDULLAH
Example 2:
If the memory chip size is 1024 X 4 bits, how many chips are
required to make up 2K bytes of memory?

1024 X 4 bits = 1K X 8bit = 210 x 4  (A0 – A9)

2K bytes = 2K X 8bit = 211 x 8  (A0 – A10)

LECTURE 9/8086 MEMORY AND I/O INTERFACING

ASSIST. PROF. DR. HADEEL N. ABDULLAH
Example 3:
Show how to implement 64K× 16 EPROM using 32K×8 EPROM?
32 K X 8 bits = 215 x 8 ==== (A0 – A14)
64K X 16 bit = 216 x 16 ==== (A0 – A15)

LECTURE 9/8086 MEMORY AND I/O INTERFACING

ASSIST. PROF. DR. HADEEL N. ABDULLAH
 Homework's
Q1: Design 8086’s memory system consisting of 512K bytes of RAM memory
and 128K bytes of ROM use the devices in figure below. RAM memory is to
reside over the address range 00000H through 7FFFFH and the address range
of the ROM is to be A0000H through BFFFFH

Q2: Design 8086’s memory system consisting of 64K bytes of ROM memory,
make use of the devices in figure below. The memory is to reside over the
address range 60000H through 6FFFFH

LECTURE 9/8086 MEMORY AND I/O INTERFACING

ASSIST. PROF. DR. HADEEL N. ABDULLAH
 Interfacing I/O Devices
 Using I/O devices data can be transferred between the
microprocessor and the outside world.
 This can be done in groups of 8 bits using the entire data bus. This is
called parallel I/O.
 The other method is serial I/O where one bit is transferred at a time
using the SID and SOD pins on the Microprocessor.
 8088/8086 architecture implements independent memory and
input/output address spaces
 Memory address space- 1,048,576 bytes long (1M-byte): 00000H-
FFFFFH
 Input/output address space- 65,536 bytes long (64K-bytes):0000H-
FFFFH
 I/O devices can be interfaced in two ways
 Isolated mapped I/O
 Memory mapped I/O
LECTURE 9/8086 MEMORY AND I/O INTERFACING
ASSIST. PROF. DR. HADEEL N. ABDULLAH
Isolated Input/output
 It treats them separately from memory.
 I/O devices are assigned a “port number” within the 8-bit address range
of 00H to FFH.
 The user in this case would access these devices using the IN and OUT
instructions only.
 Advantages of isolated I/O
1. Complete memory address space available for
use by memory
2. Special instructions have been provided in the
instruction set of the 8086 to perform isolated
I/O operation. This instructions tailored to
maximize performance

 Disadvantage of Isolated I/O

All inputs/outputs must take place between
an I/O port and accumulator (AL or AX)
register

LECTURE 9/8086 MEMORY AND I/O INTERFACING

ASSIST. PROF. D. HADEEL N. ABDULLAH
Memory-mapped Input/output
 It considers them like any other memory location.
 They are assigned a 16-bit address within the address range of the
8086.
 The exchange of data with these devices follows the transfer of
data with memory. The user uses the same instructions used for
memory.
 Advantages of isolated I/O
1. Complete memory address space available for
use by memory
2. Special instructions have been provided in the
instruction set of the 8086 to perform isolated
I/O operation. This instructions tailored to
maximize performance

 Disadvantage of Isolated I/O

All inputs/outputs must take place between
an I/O port and accumulator (AL or AX)
register

LECTURE 9/8086 MEMORY AND I/O INTERFACING

ASSIST. PROF. D. HADEEL N. ABDULLAH
Differences between Isolated I/O and Memory Mapped I/O

Isolated I/O No. Memory Mapped I/O

Isolated I/O uses separate memory Memory mapped I/O uses memory
01
space. from the main memory.

Limited instructions can be used. Any instruction which references to

Those are IN, OUT, INS, OUTS. 02 memory can be used. (MOV, AND
XCHG, SUB …….)

Faster because I/O instructions is Slower because memory instructions

specifically designed to run faster than 03 execute slower than the special I/O
memory instructions instructions

The memory address space is not Part of the memory address space is
04
affected lost

The addresses for Isolated I/O devices Memory mapped I/O devices are
are called ports. 05 treated as memory locations on the
memory map

LECTURE 9/8086 MEMORY AND I/O INTERFACING

ASSIST. PROF. DR. HADEEL N. ABDULLAH
 IN and OUT Instruction
There are two different forms of IN and OUT instructions: the direct I/O
instructions and variable I/O instructions. Either of these two types of
instructions can be used to transfer a byte or a word of data. All data
transfers take place between an I/O device and the MPU’s accumulator
register. The general form of this instruction is as shown below:
Mnemonic Meaning Format Operation Flags Effected

Input direct IN Acc, Port (Acc)  (Port)

IN none
Input variable IN Acc, DX (Acc)  (DX)
Output direct OUT Port, Acc (Port)  (Acc)
OUT none
Output variable OUT DX , Acc (DX)  (Acc)

Example:
IN AL,0C8H ;Input a byte from port 0C8H to AL
IN AX, 34H ;Input a word (two byte) from port 34H, 35H to AX
OUT 3BH, AL ;Copy the contents of the AL to port 3Bh
OUT 2CH,AX ;Copy the contents of the AX to port 2CH, 2DH
MOV DX, 0FF78H ;Initialize DX point to port
IN AL, DX ;Input a byte from a 8 bit port 0FF78H to AL
IN AX, DX ;Input a word from 16 bit port to 0FF78H,0FF79H to AX.

LECTURE 9/8086 MEMORY AND I/O INTERFACING

ASSIST. PROF. DR. HADEEL N. ABDULLAH
 The interfacing of Output Devices
 Output devices are usually slow. Also, the output is usually expected to continue
appearing on the output device for a long period of time.
 Given that the data will only be present on the data lines for a very short period
(microseconds), it has to be latched externally.
 To do this the external latch should be enabled when the port’s address is
present on the address bus, the IO/M signal is set high and WR is set low.
 The resulting signal would be active when the output device is being accessed
by the microprocessor.
 Decoding the address bus (for memory-mapped devices) follows the same
techniques discussed in interfacing memory.

LECTURE 9/8086 MEMORY AND I/O INTERFACING

ASSIST. PROF. DR. HADEEL N. ABDULLAH
 The interfacing of Input Devices
 The basic concepts are similar to interfacing of output devices.
 The address lines are decoded to generate a signal that is active when the
particular port is being accessed.
 An IORD signal is generated by combining the IO/M and the RD signals from
the microprocessor.
 A tri-state buffer is used to connect the input device to the data bus.
 The control (Enable) for these buffers is connected to the result of combining
the address signal and the signal IORD.

LECTURE 9/8086 MEMORY AND I/O INTERFACING

ASSIST. PROF. DR. HADEEL N. ABDULLAH
Demultiplexing Address/Data Lines
 8086 identifies a memory location with its 16 address lines, (AD0 to AD15)
 8086 performs data transfer using its data lines, AD0 to AD7
 address bus & Data bus are multiplexed on same lines i.e. AD0 to AD15.
 Demultiplexing refers to separating Address & Data signals for read/write operations.

LECTURE 9/8086 MEMORY AND I/O INTERFACING ASSIST. PROF. DR. HADEEL N.
ABDULLAH
 Demultiplexing Address/Data Lines
 Two 74F373 octal latches are used to form a 16-bit address latch. These devices
latch the address A0 through A15 synchronously with the ALE pulse. The latched
address outputs are labeled AoL through A15L.
 Remember that address lines A16 through A19 are not involved in the I/O interface.
 Data bus transceiver buffer in 8086 system is implemented using 74F245 octal
bus IC’s, where the control inputs DIR and G is used to control the data flow (An
 Bn) or (Bn An).

LECTURE 9/8086 MEMORY AND I/O INTERFACING ASSIST. PROF. DR. HADEEL N.
ABDULLAH
View publication stats

Homework
Q1: Draw a circuit to show how a common cathode 7-segment display can be
connected on an output port and four switches on an input port both occupying the
address range 860H to 86FH.
Q2: What do you mean by Demultiplexing? How it is done in 8086 microprocessor for
address and data bus? Explain with neat diagram.
Q3: Explain how 8086 microprocessor uses a single bus for both data and address?
Q4: Design the hardware required to interface 8 bit LED at port address 5AH
Q5: What are the two types of input/output address spaces that can be take place for
an 8086 microcomputer system, what are the advantages and disadvantages of each
type?

LECTURE 9/8086 MEMORY AND I/O INTERFACING

ASSIST. PROF. DR. HADEEL N. ABDULLAH