Спецификация AUO A015AN05-V1

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UA
CUSTOMER APPROVAL SHEET
Company Name
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MODEL A015AN05 V1
CUSTOMER Title :
APPROVED Name :
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□ APPROVAL FOR SPECIFICATIONS ONLY (Spec. Ver. )
□ APPROVAL FOR SPECIFICATIONS AND ES SAMPLE (Spec. Ver. )
APPROVAL FOR SPECIFICATIONS AND CS SAMPLE (Spec. Ver. )
□
□ CUSTOMER REMARK :
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P/N : ______________________________
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ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PRPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED
TO ANY OTHER FORMS WITHOUT PERMISSION FROM AU OPTRONICS CORP.
Studio Technology Co. Ltd. ( www.yslcd.com.tw )

Shown by LCD-SCREEN.COM.UA
Doc. Vers i o n: 0.1

Tota l Page s : 31
Date : 2009.0 3.16
Product Specifications
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1.5〞
〞 COLOR TFT-LCD MODULE
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d .co < > Prel im inary Speci ficat ion
< > Final Specification
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Note: T h e co n te nt of th i s sp ec ificat i o n i s © 200 9 AU Optro n ic s

s ubject to c h a ng e wi t ho ut n ot ice. All Ri g hts R e ser ve d

A015AN05 V1 Product Spec Version 0.1
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Record of Revision
Version Revise Date Page Content
0.0 2009/03/02 First draft
30 Add [LED life time data]

0.1 2009/03/16
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ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PRPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO
ANY OTHER FORMS WITHOUT PERMISSION FROM AU OPTRONICS CORP.

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Table of contents
A. Physical Specifications ........................................................................................................................................ 2
B. Electrical Specifications........................................................................................................................................ 3
C. Optical Specifications......................................................................................................................................... 15
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E. Packing Form..................................................................................................................................................... 19
F. Outline drawing ................................................................................................................................................... 20
G. Appendix............................................................................................................................................................. 21
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H. Suggested Application Note.............................................................................................................................. 23
I. Appendix – LED life time data ............................................................................................................................. 30

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ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PRPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO
ANY OTHER FORMS WITHOUT PERMISSION FROM AU OPTRONICS CORP.

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A. Physical Specifications
No. Item Specification Remark

1 Display resolution (dot) 280 (W) ×220 (H)
2 Active area (mm) 29.96 (W) ×22.66 (H)
3 Screen size (inch) 1.48 (Diagonal)
4 Dot pitch (mm) 0.107 (W) ×0.103 (H)
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5 Color configuration R. G. B. delta
6 Overall dimension (mm) 37.06 (W) ×34 (H) ×3.04 (D) Note 1
7 Weight (g) 6 (Typical)
8 Panel surface treatment Hard coating (3H)
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Note 1: Refer to Fig. 5
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B. Electrical Specifications
1. Pin assignment (Note1)
Pin no. Symbol I/O Description Remark

1 VCOM I Common electrode driving signal
2 VGH C Positive power for scan driver
3 V1 C Power setting capacitor connect pin
5 Vgoff_H C Negative power supply (High) for G1~G240 outputs
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6 Vgoff_L C Negative power supply (Low) for G1~G240 outputs
9 AVDD1 C FRP level supply
10 FRP O Frame polarity output for panel Vcom
11 GND P Ground pin for digital circuits
12 DRV O Power transistor gate signal for the boost converter
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13 LED Anode P LED Anode and power supply for charge pump
14 FB I/P LED cathode and main boost regulator feedback input
15 VCC P Power supply for digital circuits
16 AGND P Ground pin for analog circuits
17
18
19
20
21
22
AVDD
HSYNC
VSYNC
DCLK
DD5
DD4
P
I
I
I
I
I
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Power supply for analog circuits
Horizontal sync input. Negative polarity
Vertical sync input. Negative polarity
Clock signal; latch data onto line latches at the rising edge
Data input: MSB
Data input
23 DD3 I Data input
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24 DD2 I Data input
25 DD1 I Data input
26 DD0 I Data input: LSB
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27 V5 C Power setting capacitor connect pin Note2
28 GRB I Global reset pin
29 CSB I Serial communication chip select Note3
30 SDA I Serial communication data input Note3
31 SCL I Serial communication clock input Note3
32 VCC P Power supply for digital circuits
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33 GND P Ground pin for digital circuits

I: input; O: output, P: power
Note 1: For definition of scanning direction, please refer to figure as follows:
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Note 2:The capacitor of V5(pin27) is needed.

Note 3: Please refer to application note for 3-wire serial communication setting.

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2. Equivalent circuit of I/O
Pin no. & Pin name Schematics
12.DRV
14.FB
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18.HSYNC
19.VSYNC
20.DCLK
21.DD5
22.DD4
23.DD3
24.DD2
25.DD1
26.DD0
29.CSB
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30.SDA
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31.SCL
28.GRB
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3. Absolute maximum ratings
Item Symbol Condition Min. Max. Unit Remark
VCC GND=0V -0.5 5 V
Supply Voltage
AVDD AGND=0V -0.5 5.5 V
VGH AGND=GND=0V 0 16 V
TFT-LCD Power
Voltage Vgoff_H AGND=GND=0V -10 0 V
Vgoff_L AGND=GND=0V -16 0 V
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CS,SDA,SCL,Vsync,
Input Signal Voltage AGND=GND=0V -0.5 5 V
Hsync,DCLK,D0~D7
VCOM AC Output
FRP AGND=GND=0V 0 8 V
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Voltage
VCOM AC Power
VCAC AGND=GND=0V 0 8 V
Voltage
VCOM DC Output
COMDC AGND=GND=0V 0 5 V
Voltage
VCOM Input Voltage
d VCOM
V1
V2
V3
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AGND=GND=0V
AGND=GND=0V
AGND=GND=0V
AGND=GND=0V
-2.9
0
0
0
5.6
16
8
16
V
V
V
V
V4 AGND=GND=0V -16 0 V
Storage Ambient
Tstg - -25 80
Temperature temperature
℃
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Operating Ambient
Topa - 0 60
Temperature temperature
℃
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4. Electrical characteristics
a. Typical operating conditions (GND = AGND = 0V)

Item Symbol Min. Typ. Max. Unit Remark
VCC 3.0 3.3 3.6 V

Power supply
AVDD 3.0 3.3 3.6 V
Output H Level VOH Vcc-0.4
Signal
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voltage L Level VOL GND GND+0.4
Input H Level VIH 0.7VCC - VCC V
Signal
voltage L Level VIL GND - 0.3VCC V
Output H Level IOH 10 uA
current
L Level IOL -10 uA
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Analog stand by Ist 200 uA DCLK is stopped
current
VCAC 4.4 5.6 5.8 V
VCOM Voltage
VCDC 0.30 0.45 0.60 V
Positive Power
Supply
Negative Power
supply
(Low)
VGH
VGoff_L
12
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-14
13
-13
14
-12
V
Negative Power
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supply VGoff_H -8.4 -7.4 -6.4 V
(High)
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b. Recommended Capacitance Values of External Capacitor
The recommended capacitance values of the external capacitor are shown below. These values
should be finally determined only after performing sufficient evaluation on the module.
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Operating value of Withstanding

Pin name
capacitors (µF) voltage (V)
V5 4.7 to 10 6.3(Note)
VCC 1 to 10 6.3
AVDD 1 to 10 6.3
AVDD1 1 to 10 10
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VGH 1 to 10 16
Vgoff_H, Vgoff_L 1 to 10 16
V1, V2 1 to 10 16
V3, V4 1 to 10 16
FRP 10 16
LED_Anode 10 16
Note1: The capacitors of V5 (27pin) is needed.
Note2: Typical operating capacitors reference suggested reference application circuit

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c. Current consumption (GND = AGND = 0V)
Parameter Symbol Condition Min. Typ. Max. Unit Remark
ICC VCC = 3.3V - 2 2.5 mA Note1
Current
IDD AVDD = 3.3V - 1.5 2.0 mA Note2
Note1:This power consumption doesn’t include LED power consumption.
Note2:Test condition: 8colorbar+Grayscale pattern, UPS051 mode, DCLK=5.67MHz, frame
rate:60Hz.
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d. LED driving conditions
Parameter Symbol Min. Typ. Max. Unit Remark
I LED 20 25 25.5 mA Note1
LED current
I LED-an ode 22 25 25.5 mA Note2
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LED voltage VL 6.8 7.8 9 V Note3
Note1: Internal LED booster circuit. FB=0.6V

Note2: External LED circuit. FB=0.2V
@ILED=25mA.
5. Input timing AC characteristic

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Note3: V L = LED Anode (PIN 13), LED Max. Voltage: 1pcs/3.6V, LED Min. Voltage: 1pcs/3.0V.
(VCC=3.3V, AVDD=3.3V, AGND=GND=0V, TA=-25℃~85℃)

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Parameter Symbol Min. Typ. Max. Unit Remark
DCLK period time tDCLK 37 - - ns
HSYNC period time Th 60 63.56 67 us
VSYNC setup time Tvst 12 - - ns
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VSYNC hold time Tvhd 12 - - ns

HSYNC setup time Thst 12 - - ns
HSYNC hold time Thhd 12 - - ns
Data setup time Thst 12 - - ns
Data hold time Thhd 12 - - ns
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HSYNC width Thsw 1 1 96 tDCLK

VSYNC width Tvsw 1 tDCLK 1 tDCLK 6Th
DCLK duty cycle Tcwh/Tcwl 40 50 60 %

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6. AC Timing
a. UPS051 Timing conditions
Note1: Horizontal display position:
Parameter Symbol Min. Typ. Max. Unit. Remark
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DCLK Frequency 1/tDCLK 5.62 5.67 12 MHz
Period tH 360 tDCLK
Display period thd 280 tDCLK
HSYNC Back porch
Front porch
Pulse width
thbp
thfp
thsw
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19
1
62
18
25
64
16
56
tDCLK
tDCLK
tDCLK
Note1
Odd
d
Period tV 256 262.5 264 tH
Even
Odd
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Display period tvd 220 tH
Even
Odd 23
VSYNC Back porch tvb tH
Even 23.5
Odd 13 19.5 21
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Front porch tvf tH

Even 12.5 19 20.5
Odd
Pulse width tvsw 1 tDCLK 3 tH 6 tH -
Even
Available display starts from the data of 63 tDCLK when back porch value (thbp) set 62.
Note2: UPS051 support interlacing input format
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Note3: UPS051 support non-interlacing input format. Odd field only or even field only

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UPS051 Input Horizontal Data Sequence
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UPS051 Input Horizontal Timing Chart
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(EVEN)
(ODD)

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b. UPS052 Timing conditions
Parameter Symbol Min. Typ. Max. Unit. Remark

DCLK Frequency 1/tDCLK 23.3 24.54 25.7 MHz
Period tH 1560 tDCLK
Display period thdisp 1280 tDCLK
HSYNC Back porch thbp 248 249 251 tDCLK Note1
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Front porch thfp 32 31 29 tDCLK
Pulse width thsw 1 25 56 tDCLK
Odd
Period tV 256 262.5 264 tH
Even
Odd
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Display period tvdisp 220 tH
Even
Odd 23
VSYNC Back porch tvb tH Note2
Even 23.5
Front porch
Pulse width
d Odd
Even
Odd
Even
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tvf
tvsw
13
12.5
1 tDCLK
19.5
19
3 tH
21
20.5
6 tH
tH
Note1: Horizontal display position:

Available display starts from the data of 266 tDCLK when back porch value (thbp) set 249.
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Note2: UPS052 support interlacing input format
Note3: UPS052 support non-interlacing input format. Odd field only or even field only.
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Invalid data
thfp
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1280
UPS052 Input Horizontal Timing Chart
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tH = thbp + thdisp + thfp
d R0 G0 B0 Dm R1 G1 B1 Dm
thdisp
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thbp
Invalid data
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thsw
HSYNC
DCLK
Data

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Valid Data
tV
V display
t vd
1 field ( EVEN )
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UPS052 Input Vertical Timing Chart
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tvb
1 frame
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tV
V display
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1 field ( ODD )
V blanking
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tvb
t vsw
HSYNC
VSYNC
DATA
7. 3-wire serial communications


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For 3-wire serial communication timing, it is shown in Fig.6. For register setting, please refer to application
note.
8. DC-DC Converter Circuit

A015AN05 contains one high-power step-up DC-DC converter, and a backplane drive circuitry for active
matrix TFT LCDs. The output voltage of the main boost converter can be set from VCC to 13.5V with
external resistors. Also, there are a precision 0.6V reference voltage, a fault detection and a logic shutdown
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included in A015AN05.
a .Boost Converter
A015AN05 main boost converter uses a boost PWM architecture to produce a positive regulated voltage.
Please refer to Fig. 1 for the DC-DC converter block diagram.
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LED_Anod
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AGND AGND
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FB
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AGND
AGND
Fig. 1 Dc-Dc converter block diagram

In the internal architecture of DC-DC converter as shown in Fig. 2, the feedback voltage (VFB) will
connect to the tri-angle waveform comparator, and generates the output signal (CP0) which determines the
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duty cycle for (Fdc).

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Fig. 2 DC CK block diagram
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To reduce the noise affect, CP0 will be processed by De-bounce circuit. State-machine will generate the
duty cycle by CP0 signal. To make sure that VFB can reach default VREF quickly, so that State-machine is
designed as a discrete step by step function, please refer to Fig. 3. If CP0 is low, the duty cycle will work
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from 0% to 75%, and the maximum f that is 75%.
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Fig. 3 PWM Control state diagram
b. Charge Pump Block Diagram

The LED_Anode Voltage is used for internal pump circuit to generate VGH/Vgoff_H/ Vgoff_L/Vcac for gate
and VCOM used.
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Fig. 4 charge pump diagram

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Note1Am
Contrast ratio
Viewing angle
Brightness (25mA)
C
R
1
0

binperatu=25.
C. Optical Specifications
Item
Response time
Top
Bottom
Left
Right
White chromaticity
Note 2 Measured in the dark room

Rise
Fall
S ig n a l( R e la t iv e v a lu e )
100%
90%
10%
0%
Symbol
Tr
Tf
CR
YL
X
"White"
A015AN05 V1 Product Spec
Condition
θ=0°
At optimized
viewing angle
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θ=0°
θ=0°
θ=0°
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Tr
Min.
-
-
60
10
30
40
40
130
(0.26)
(0.28)
Note 3 Measured on the center area of panel with a field angle of 1° by Topcon luminance meter BM-7,
after 10 minutes operation.
Note 4 Definition of response time:
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Output signals of photo detector are measured when the input signals are changed from “black” to
“white” (falling time) and from “white” to “black” (rising time), respectively.
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"Black"
Response time is defined as the time interval between the 10% and 90% of amplitudes. Refer to
the figure as follows.
Typ.
25
30
150
-
-
-
-
170
(0.31)
(0.33)
Version
Max.
50
60
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Page
-
-
-
-
-
(0.36)
(0.38)
Tf
Unit
ms
ms
deg.
cd/m2
"White"
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Remark
Note 4
Note 5, 6
Note 7
Note 8
Note 5 Definition of contrast ratio:

Contrast ratio is calculated with the following formula.
Photo detector output when LCD is at “White” state
Contrast ratio (CR) =
Photo detector output when LCD is at “Black” state
Note 6 White Vi = Vi50 ＋ 1.5V
Black Vi = Vi50 ± 2.0V
“±” means that the analog input signal swings in phase with COM signal.
“ ” means that the analog input signal swings out of phase with COM signal.
Vi50: The analog input voltage when transmission is 50%
100% transmission is defined as the transmission of LCD panel when all the input terminals of
module are electrically opened.
Note 7 Definition of viewing angle:

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Refer to the figure as follows.
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Note 8 Measured at the center area of the panel when all the input terminals of LCD panel are electrically
opened.
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Note 9 Gray level inversion direction: 6 o’clock
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D. Reliability Test Items
No.
1
2
3
4
5
6
9
Heat shock
Test items
High temperature storage
Low temperature storage
High temperature operation
Low temperature operation
High temperature and high humidity
Electrostatic discharge
Vibration (with carton)
Drop (with carton)
Note1 Ta: Ambient temperature.
Note2: ESD Testing Flow as the below,
LCD power on,

Functional check
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Note 3. ESD testing method.
Ambient: 24~26℃, 56~65%RH
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Ta=6~8205.9,%
A015AN05 V1 Product Spec
Ta = -
-
RcyHles2r/
Air-mode : +/- 8kV
Contact-mode : +/- 4kV
Random vibration:
0.015G2/Hz from 5~200Hz
–6dB/Octave from 200~500Hz
Height: 60cm
Conditions
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Version
1 corner, 3 edges, 6 surfaces

Page
240Hrs
240Hrs
240Hrs
240Hrs
240Hrs
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Remark
Operation
Non-operation
Note.2, 3
IEC 68-34
Make sure protection film(s) on top of polarizer or back of LCD module is/are removed before RA test.
Electrostatic
discharge
Functional check
& judge the results
Instruments:NoisekenESS-2000,
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Operation System: “CT30AA-A” and adapter “A015AN04 V5T0”

Test Mode: Operating mode, test pattern: colorbar+8Gray scale
Test Method:
Contact Discharge: 150pF(330Ω) 1sec, 5 points, 10 times/point
Air Discharge: 150pF(330Ω) 1sec, 5 points, 10 times/point
Test point:
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Bezel
1 Display Area 2
4 3
AUO

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The metal casing is connected to power supply ground (0V) at four corners.
All register commands are repeating transfer.
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E. Packing Form
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Palletizing sequence (if necessary)

(1). Box placement on wooden pallet
a. Place max 30 of corrugated boxes on wooden pallet and should not be pushed out of
the pallet. (as showed below)
b. (700 *6) *5 layers: Max 30 boxes / pallet. (21000 pcs modules)
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(2). Apply stretch film. Corner angle and PE band
a. Stretch film should cover around whole pallet.
b. Apply corner angle to 4 top edge and 4 side edge of the pallet.
c. Select corner angle length by height of palletizing.
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d. PE band number is depended on customer requirement and height of palletizing.
(3). Labeling
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a. Apply shipping case label is depended on customer requirement.
b. Apply care mark label at 4 side ( Front / Back / Left / Right )on the pallet.
c. Empty box label is applied if needed.
d. Other package method or label are depended on customer requirement.
d
Top cardboard
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Stretch film
Care mark label
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Case label PE band
Corner angle
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Bottom cardboard
Wooden pallet
Note: Limit of box palletizing=Max 5 layers (ship and stock conditions) for air transport
and marine transit.

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F. Outline drawing
dden.
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G. Appendix
Fig. 6 3-wire programming function timing

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Fig. 7 Panel color Filter Alignment

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H. Suggested Application Note

A015AN05 is designed with smart integration advance (SIA) concept for DSC application. This panel
integrated not only source driver & gate driver, but also built in power generator and embedded serial
communication interface for the function setting.
A015AN05 is supported by two kinds of input timing format: UPS051 and UPS052. Customers can use
3-wire serial port for setting register and select different timing for their own design feature.
In this document, we list essential parameters for configuration. Please follow our recommend setting to
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achieve the best performance. In the last page, we provide application circuit to drive A015AN05.
For A015AN05 driving circuit design, you just need input one set of power 3.3V, because the charge-pump
circuit inside the driver IC produces Vgh & Vgl. The external peripheral is very simple and good for saving
BOM cost for customers.
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1. 3-wire serial communication AC timing
Parameter Symbol Min. Typ. Max. Unit
Serial clock Tsck 320 - ns
SCL pulse duty
Serial data setup time
Serial data hold time
Serial clock high/low
Chip select distinguish
d Tscw
Tist
Tiht
Tssw
Tcd
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120
120
120
1
50
-
-
-
-
60
-
-
-
-
%
ns
ns
ns
us
Time that the CSB to Vsync Tcv 1 - - us
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2. The configuration of serial data at SDA terminal is at below
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Register address DATA
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3. Recommend register table for UPS051 timing
Address
No. Description D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R0 Scan direction 0 0 0 0 0 X X X X X X X X X 0 1
R1 Data setting 0 0 1 0 0 X X X X X X X X X 0 0
R2 Source IC
0 1 0 0 0 X X X X X X X 1 1 0 0
setting
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R3 Timing select 0 1 1 0 0 X X X X X X X X 0 0 0
R4 VCAC level
1 0 0 0 0 X X X X X X X X 1 1 0
setting
R5 HBLK setting 1 0 1 0 0 X X X X X X X X X 0 0
T0 DRV setting 0 0 0 1 0 X X X X 0 1 1 0 0 0 0
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No. Description D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
“X” =>Don’t care
4. Recommend register table for UPS052 timing
No. Description
Address
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D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R0 Scan direction 0 0 0 0 0 X X X X X X X X X 0 1
R1 Data setting 0 0 1 0 0 X X X X X X X X X 0 1
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R2 Source IC
0 1 0 0 0 X X X X X X X 1 1 0 0
setting
R3 Timing select 0 1 1 0 0 X X X X X X X X 0 0 1
R4 VCAC level
1 0 0 0 0 X X X X X X X X 1 1 0
setting
R5 HBLK setting
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1 0 1 0 0 X X X X X X X X X 0 0
T0 DRV setting 0 0 0 1 0 X X X X 0 1 1 0 0 0 0
“X”=>Don’t care
5. Register detail description

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a. Register R0
Bit Function
D0 Up/down scan direction: “0” => Down to up
“1” => Up to down
D1 Left/Right scan direction: “0” => Left to right
“1” =>Right to left
b. Register R1
Bit Function
D0 “0” =>When UPS051 mode selected
“1” =>When UPS052 mode selected
D1 Always fixed at “0”

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c. Register R2
Bit Function
D2 Standby mode setting: “0” => Turn off driver & DCDC
“1” => Normal operating
D3 Global reset setting:
“0” =>Driver control register is in reset state, all setting to default value.
“1” =>Normal operating;
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d. Register R3
Bit Function
D0 “0” => To select UPS051 timing
“1” => To select UPS052 timing
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e. Register R4 ＊
Bit Function
＊ Set VCOM AC level = 5.6V (Amplitude)
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f. Register R5
d
Bit Function
Select the horizontal input delay timing
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Level
DL1 DL0 NO.
D1~D0 0 0 +0
0 1 -1 Unit:
1 0 +1 DCLK
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1 1 +2
g. Register T0
Bit Function
PWM shutdown control circuit setting
D4 “0” => PWM control circuit will be shut down.
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“1” => PWM control circuit normal operation. (Default)

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Suggested reference application circuit

(1) Internal LED booster circuit
The integrated driver IC provides build-in LED booster controller, DC-DC charge pump, and VCOM driver.
See Fig. 8 for the application circuit. The recommended capacitance values of the external capacitor
please refer to page 5. The capacitors of 411 will be used shrinkage IC.
R405 3.3V
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L101 GRB VCC
3. 3V VCC 1 2 AVDD
VCC 1k
330uH
R404 C410
C300 C401 20K 1uf
0.1uf 1uf 10uF C409
VCOM FRP U 206
DGN D 33
3
L100 VCC 32 33
VR100 SCL 31 32
2 100K SDA 30 31
47uH CXLD120 CSB 29 30
GRB 28 29
I_LED_Anode VC5 27 28
DD0 26 27
D100
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1
C100 0. 01uf 26
SW LED_Anode DD1 25
C411 DD2 24 25
DD3 23 24
FS1J3
LED1 R403 4.7uf DD4 22 23
DR V Q1 22
FMMT618 C402 6. 2k OPEN DD5 21
IC 21
R100 12K 10uf DCLK 20
VSY N C 19 20
Vgof f _L H SY N C 18 19
AVDD 17 18
AGN D 16 17
FB(LED cathode) .co

R406
180
LED , R406 and IC build in on panel
Q2
I_LED VC1 Vgof f _L AVDD1
R12
10k
Vgof f _H
C25
10uf
VCC
FB
LED_Anode
DRV
DGN D
FRP
AVDD1
VC4
VC3
Vgof f _L
15
14
13
12
11
10
09
08
07
06
16
15
14
13
12
11
10
09
08
07
3
C403 C408 C405 C406 Vgof f _H 05 06

EXTERN AL-SWITCH 1 1 1uf 1uf 1uf VC2 04 05
1uf
VC1 03 04
5H N01SS VC2 VGH 02 03
2
VCOM 01 02
d
VC3 01
C407
C404 R402 CON 33
R401 1uf DGND AGN D 1uf
24
VC4 000A
slc
SMD1206
Fig. 8 Typical Application Circuit
Note:
w.y
C25 & R12 are new adding external components.

C25 => to stable the AVDD power
R12 => used for discharge AVDD power faster
Q2 to control backlight on/off function
EXTERNAL-SWITCH1 “H” backlight on
EXTERNAL-SWITCH1 “L” backlight off
ww
Please refer to suggestion power and standby on/off sequence.

Page 27 / 31
External LED circuit
I_LED_anode L4
3.3V 1 2 AVDD U207
LED_Anode GRB R505 3.3V DGND 33
330uH 33
VCC 32
1k SCL 32
R504 31
20K C509 SDA 30 31
D300 C501 LED1 10uF C508 1uf CSB 29 30
UDZS 9.1B(9.1V) 10uf VCOM FRP GRB 28 29
VC5 27 28
3
IC DD0 26 27
VR101 DD1 25 26
2 100K C510 DD2 24 25
.tw
R506 DD3 23 24
4.7uf 23
180 DD4 22
DD5 21 22
LED , R506 and IC build in on panel 21
DCLK 20
1
VSY NC 19 20
FB HSY NC 18 19
(LED cathode) AVDD 17 18
R503 AGND 16 17
Q1 6.2k OPEN VCC 15 16
I_LED FB 14 15
3
R500 LED_Anode 13 14
EXTERNAL-SWITCH2 1 Vgof f _L 10k C500 12 13
1uf DGND 11 12
11
m
5HN01SS FRP 10
2
AVDD1 09 10
VC1 AVDD1 Vgof f _H Vgof f_L VC4 08 09
Connect to LED driv er's FB 08
VC3 07
C504 C505 C507 Vgof f _L 06 07
1uf C502 1uf 1uf Vgof f _H 05 06
1uf 05
R501 VC2 04
52 VC2 VC1 03 04
VGH 02 03
02
d 1uf
VC3
.co
C503
VC4
DGND
R502
000A
SMD1206
Fig. 9 External LED driver Circuit

AGND
C506
1uf
VCOM 01
01
CON33
Note:
Q1 to control backlight on/off function
slc
EXTERNAL-SWITCH2 “H” backlight on
EXTERNAL-SWITCH2 “L” backlight off
Please refer to suggestion power and standby on/off sequence.
w.y
Power supply VCC (typical 3.3V) and AVDD (typical 3.3V) are required to provide driver IC power and
generate all necessary voltages for LCD related circuits.
We recommend the external LED driver circuit provide a constant 25mA for LED backlight unit.We suggest
the R501 resister value is greater than 30 ohm to turn off DRV signal.The capacitors of C510 will be used
shrinkage IC.
ww

Page 28 / 31
Suggestion power on/off sequence

m .tw
(2) External LED circuit
d .co
slc
w.y
ww
We recommend power on/off sequence that base on differential application circuit to make sure power on/off
function can work successfully in every time power on.
Note: In standby mode, VSYNC signal will don’t care, but we suggestion VSYNC is disable.

Page 29 / 31
Suggestion Standby on/off sequence

m .tw
(2) External LED circuit
d .co
Note: xx means don’t care this signal.
slc
w.y
Note: xx means don’t care this signal.

We recommend standby on/off sequence that base on differential application circuit to make sure function can
ww
work successfully.

Page 30 / 31
I. Appendix – LED life time data
m .tw
d .co
J. Mechanism Notice for EPSON
slc
w.y
ww
Fig.1
After conducting 30°, 180°, and 270° bending tests around the “non-bending area” of FPC,
AUO believes that the panel arrangement in Fig.1 would not lead to FPC damage at the
soldering points.

Page 31 / 31
K. UPS051 input timing power on sequence for EPSON
m .tw
below.
d .co
Note, if remove application circuit fig8’s L101 or fig9’s L4, power on sequence will be become as
slc
w.y
ww
L. Green note
In accordance with SEIKOEPSON Group's requirements specified by "Green Purchasing Standard
for Production Material," all production parts shall conform to SEIKO EPSON's Banned/Eliminated
Chemical Substances policy and shall be controlled by "4M Variation Management."

Спецификация AUO A015AN05-V1

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Studio Technology Co. Ltd. ( www.yslcd.com.tw )

Doc. Vers i o n: 0.1

Note: T h e co n te nt of th i s sp ec ificat i o n i s © 200 9 AU Optro n ic s

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30 Add [LED life time data]

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A. Physical Specifications ........................................................................................................................................ 2

F. Outline drawing ................................................................................................................................................... 20

I. Appendix – LED life time data ............................................................................................................................. 30

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No. Item Specification Remark

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Pin no. Symbol I/O Description Remark

33 GND P Ground pin for digital circuits

Note 2:The capacitor of V5(pin27) is needed.

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a. Typical operating conditions (GND = AGND = 0V)

VCC 3.0 3.3 3.6 V

Operating value of Withstanding

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Note1: Internal LED booster circuit. FB=0.6V

5. Input timing AC characteristic

(VCC=3.3V, AVDD=3.3V, AGND=GND=0V, TA=-25℃~85℃)

VSYNC hold time Tvhd 12 - - ns

HSYNC width Thsw 1 1 96 tDCLK

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Parameter Symbol Min. Typ. Max. Unit. Remark

Display period thd 280 tDCLK

HSYNC Back porch

Front porch tvf tH

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Parameter Symbol Min. Typ. Max. Unit. Remark

Note1: Horizontal display position:

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7. 3-wire serial communications

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8. DC-DC Converter Circuit

Fig. 1 Dc-Dc converter block diagram

duty cycle for (Fdc).

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Fig. 3 PWM Control state diagram

b. Charge Pump Block Diagram

Fig. 4 charge pump diagram

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Note 2 Measured in the dark room

Note 5 Definition of contrast ratio:

Note 7 Definition of viewing angle:

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Refer to the figure as follows.

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Vibration (with carton)

Drop (with carton)

Note1 Ta: Ambient temperature.

Note2: ESD Testing Flow as the below,

LCD power on,

1 corner, 3 edges, 6 surfaces

Operation System: “CT30AA-A” and adapter “A015AN04 V5T0”

Studio Technology Co. Ltd. ( www.yslcd.com.tw )