4.

1 Introduction

This chapter outlines and demonstrates the experimental results

of the system on chip design of ECG processing and arrhythmia
detection. The present work proposes low power design of 12 lead
ECG acquisitions. The design contains amplifier, feature extraction,
ECG analysis and arrhythmia detection using low power technique. It
makes use of the performance evaluation parameters like power of
each design, on and off resistance of multiplexer, gain, PSRR, CMRR,
3dB bandwidth and unity gain bandwidth of amplifier, Ripple factor,
form factor, peak factor, efficiency and offset voltage of half wave
rectifier, rise time, fall time of comparator and accuracy of arrhythmia
detection to estimate the performance of the SOC design. A circuit is
designed to extract the RR intervals for ECG analysis. The work
utilized Tomkins algorithm for analyzing ECG to detect arrhythmia.
Dynamic threshold logic, current scaling and circuit level low power
techniques are employed for power reduction.

4.2 12 lead ECG acquisition system

The 12 Lead ECG signal is acquired by selecting electrode

combination for each lead sequentially and this is accomplished by
designing CMOS multiplexer. The analog multiplexing unit for
acquiring the combination of different electrode signals to produce
different lead signals of ECG. 180nm Cadence tool is used to design
and simulate the multiplexer. The circuit employs dynamic body
biasing which reduces the threshold voltage to 0.3V. However to
operate the transistor in strong inversion mode, 0.4V supply is used.
The circuit is tested with a maximum switching frequency of 300 kHz
and the power dissipation was 22.12µW achieved. The circuit is
 89

simulated by applying sinusoidal signals with amplitude ranging from

1µV to maximum of 0.4V to each channel. The decoder is designed to
select the channels of the corresponding multiplexer.

The decoder is designed using 4 input AND gate with GDI

technique as it requires less number of transistors. The DTMOS
technique is used to reduce power in this design. The schematic
circuit of AND gate in Cadence environment is given in Fig.4.1 and the
simulation result is shown in Fig.4.2.
The four input AND gate is used to design a 3 to 8 decoder with
active eight HIGH outputs and three inputs. The fourth input is used
as EN signal which will enable or disable the decoder.

Fig.4.1 Schematic circuit of AND gate using GDI technique in

Cadence tool
 90

Fig.4.2 Simulation result of AND gate using GDI technique

4 input AND gate design is shown in Fig.4.3 and simulation result
in Cadence is shown in Fig.4.4. .

Fig.4.3 Schematic circuit of 3 to 8 decoder in Cadence tool

 91

Fig.4.4 Simulation result of 3 to 8 decoder

The channel selection frequency is varies from DC to 1 KHz. The

multiplexer design on Cadence is given in Fig.4.5.

Fig.4.5 Multiplexer design on Cadence Tool

 92

Depending upon the decoder input and the INH signal the
channels of the corresponding multiplexers are selected which is given
in the Table 4.1.

Table 4.1 Channel selection of the corresponding multiplexer

Decoder input
Inhibit MUX1 o/p MUX2 o/p MUX3 o/p
CB A
0 0 0 1 CH1 CH1 -
0 0 1 0 CH2 CH2 -
0 0 1 1 CH3 CH3 -
0 1 0 0 CH4 CH4 -
0 1 0 1 CH5 CH5 -
0 1 1 0 CH6 CH6 -
1 0 0 1 CH7 - CH1
1 0 1 0 CH7 - CH2
1 0 1 1 CH7 - CH3
1 1 0 0 CH7 - CH4
1 1 0 1 CH7 - CH5
1 1 1 0 CH7 - CH6

The multiplexer circuit is simulated by sinusoidal signal with

amplitude ranging from 1uV to maximum of 0.4V to each channel.
The circuit is tested with input signal amplitude of 1,2,3,4,5,6,7 μV,
1,2,3,4,5,6,7 mV and 100,150,200,250,300,350,400 mV given to
respective channels and simulation results are shown in Fig.4.6,
Fig.4.7 and Fig.4.8. The results show that the output obtained from
multiplexer is less swing degradation. The circuit is drawn less current
which is 55.83 μA and it is marked in Fig.4.9.
 93

Fig.4.6 Simulation result of multiplexer with input signal amplitude of

1,2,3,4,5,6,7 μV

Fig.4.7 Simulation result of multiplexer with input signal amplitude of

1,2,3,4,5,6,7 mV
 94

Fig.4.8 Simulation result of multiplexer with input signal amplitude of

100,150,200,250,300,350,400 mV

Fig.4.9 Simulation result of multiplexer with measured current

 95

The dynamic power dissipation is measured at various switching

frequencies ranging from DC to 1 KHz and the graph is shown in Fig.
4.10. The power consumed is 22.12 µW up to a switching frequency
of 300 kHz. Above this frequency the power dissipation is increased
and a maximum of 25.32µW is consumed at frequency of 1 MHz.

Power in uw

0 100 200 400 600 800 1k 2K

Frequency in Hz
Fig.4.10 Switching frequency vs power dissipation in multiplexer
design

Integrated circuits are designed to work for a range of

temperature and voltage, and not just for a single temperature and
voltage. These have to work under different environmental conditions
and different electrical setup and user environments. For instance, the
temperature in the internals of an automobile may reach as high as
150 degrees while operating. Also, automobiles may have to work in
colder regions where temperatures may reach -40 degrees during
winters. So, a chip designed for automobiles has to be designed so as
to be able to work in temperatures ranging from -40 to 150 degree
Celsius. On the other hand, consumer electronics may have to work in
the range of -20 to +40 degrees only. Thus, depending upon the
application, the chip has to be robust enough to handle varying
surrounding temperatures. Not just surrounding temperatures, the
 96

voltage supplied by the voltage source may vary. The battery may
have an output voltage range. Also, the voltage regulator sitting
inside or outside the chip may have some inaccuracy range defined.
Let us say, a SOC has a nominal operating voltage of 1.2V with 10%
variation. Thus, it can operate at any voltage from 1.08 V to 1.32V.
The integrated circuits have to be tolerable enough to handle these
variations.
Thus in this design process corner condition has tested. The
results have been shown for the traditional process corner conditions,
while they have been obtained through CADENCE SPECTRE
SIMULATOR transistor model for the respective technology node to
account for all short-channel effects. Observe that the actual value of
body bias and its sensitivity to drain current strongly depends on the
process corner: fast, typical, or slow.
For the typical NMOS and PMOS device, maximum drain current
is obtained with a bulk voltage of 959 mV and 315.3mV respectively.
Source and drain junction forward biased leakage current increases
exponentially when the bulk voltage Vbulk is greater than VDD. Ijunc tries
to reach close to Ion which is linearly increasing ON current. It causes
charging and discharging of internal and output node of transistor
become slow. This conflict between (I on) and (Ijunc) is also the cause
for degradation of the output high and low levels. Junction
capacitance increment also slows down the circuit. The PVT corner
simulation of NMOS and PMOS of different corners like small-small
(SS), typical-typical (TT) and fast-fast (ff) is given in Table 4.2 and
Table 4.3.
 97

Table 4.2 PVT corner simulation of NMOS Transistor

VD
SS MODEL TT MODEL FF MODEL
D
0 0 0 0 0 0 0
Tem -40 C 27 C 110 - 27 110 -40 C 27 C 110 C
0
p C 40 C 0C C
0.9 1.5V 1.43V 1.28 1.3V 1. 1.38 1.47V 1.43 1.25V
V 7V 35 V V
V
0.8 1.5V 1.35V 1.17 1V 1V 1V 1.45V 1.33 1.168
V V V V
0.7 1.40 1.26V 1.08 1V 1V 1V 1.38V 1.25 1.08V
V 5V V V
0.6 1.29 1.165V 990 1V 1V 959 1.29V 1.14 990
V V mv mv 8V mV
0.5 1.19 1.07V 900 992 1V 880 1.199 1.05 900
V V mV mv mV V V mV
0.4 1.10 963 784. 1V 95 800 1.1V 960 781.1
V 8V mV 4 mV 9 mV mV mv
m
V
0.3 1.01 871.2 687. 991 80 678 1.03V 870 689.8
V V mV 7 mV mV 0 mV mV mV
m
V

Table 4.3 PVT corner simulation of PMOS Transistor

VDD SS MODEL TT MODEL FF MODEL

0 0 0 0 0 0 0
Tem -40 C 27 C 110 - 27 C 110 - 27 C 110
0 0
p C 40 C C 40 C C
0.9V 0 0 0 0 0 0 0 0 0
0.8V 63.1 0 0 54 0 0 56 0 0
mV mV mV
0.7V 150.9 48.6 0 162. 54.1 0 162. 47.5 0
mV mV 8 mV mV 3 mV mV
0.6V 242 130. 21.2 261. 144 22 267. 154. 14.6
mV 5 mV mV 2 mV mV mV 1 mV 9 mV mV
0.5V 350 227. 86 343 223 86 358. 242 99.5
mV 7 mV mV mV mV mV 6 mV mV mV
0.4V 438.9 311 153. 441 315. 158 447. 331. 186
 98

mV mV 2 mV mV 3 mV mV 3 mV 9 mV mV
0.3V 525m 411 259. 525 411 257 552 434 285
V mV 1 mV mV mV mV mV mV mV

4.3 Amplifier design

ECG signal amplitude lies in the range of few millivolt which is

very difficult to monitor, record for further processing. Hence it is
required to amplify the ECG signals for better interpretation. This
amplification process is accomplished in this work using sub-threshold
single stage folded cascode OTA. The main noise source in ECG signal
is baseline wander and power-line interference. The baseline wander
noise is nearly 0.05 Hz which is eliminated by amplifier lower cutoff
frequency.

The single stage folded cascode amplifier has been designed to

amplify ECG signal with an operating voltage of 0.4 V. The cascoding
connection is given to increase the gain due to high output
impedance. Folded cascode connection is used to provide high gain,
large output signal swing and broad bandwidth. To reduce the noise in
amplifier the source degenerated circuit is used. The current obtained
in transistors M7-M12 is approximately maintained to one third of the
current drawn in M1 and M2 transistors which is shown in Table 4.4.
This arrangement makes the noise contribution is negligible. The
measured results show that the circuit is consuming very low power
and less noise.

The CMOS design of modified folded cascode OTA in Cadence

Environment is given in Fig.4.11.

 99

Fig.4.11 CMOS circuit design of modified folded cascode OTA in Cadence

Tool

The operating region, aspect ratio and drain current of transistors of

amplifier design is given in Table 4.4.

Table 4.4 Operating region and aspect ratio of transistors in OTA design

Operating
Devices W (um) / L (nm) ID
region

Sub-threshold
M1,2 20/180 393.4nA
region

Sub-threshold
M3,4 50/180 393.4nA
region

100
 Sub-threshold
M5,6 10.02/180 514.1nA
region

Sub-threshold
M7,8 1/180 120nA
region

Sub-threshold
M9,10 1/180 120nA
region

Sub-threshold
M11,12 1/180 120nA
region

The simulation results of folded cascode amplifier are given

below which show the parameters of amplifier like bandwidth,
differential gain, common mode gain, phase, input referred noise and
power analysis.

Fig.4.12 Common mode gain plot of OTA

 101

The common mode gain plot of OTA is shown in Fig.4.12. It is

plotted during 0-300KHz.

Fig.4.13 Differential gain of OTA with C = 100fF

The differential gain of OTA is given in Fig.4.13 with 100fF of

capacitance, 256.76 KHz of bandwidth and 55.254dB gain.

 102

Fig.4.14 Gain-phase plot of OTA

The Gain-phase plot of OTA is given in Fig.4.14. It is obtained

for gain of 58dB and 3600 phase.

Fig.4.15 Noise response of OTA

 103

The input noise of OTA is plotted in Fig.4.15. The input referred

noise is 1.159 µVrms which is negligible.

Fig.4.16 Unity gain bandwidth of OTA

The unity gain bandwidth is 18.04MHz which is pointed in above

Fig.4.16.

Fig.4.17 Power analysis of OTA

 104

The power obtained is 620nW which is calculated using Cadence

calculator tool shown in Fig.4.17.

Fig.4.18 Transient analysis of OTA

The transient analysis of OTA is plotted for V+, V- and OTA

output shown in Fig.4.18.

A low power single stage folded cascode amplifier for Bio-Signal

is designed with 400mv operating voltage, driving with total current of
1.24µA and 620nW power consumption. The obtained gain of OTA is
58db with 282.16 KHz bandwidth and 18.04MHz of unity gain
bandwidth. The calculated CMRR and PSRR are 89dB and 95dB
respectively. Table 4.5 shows the measurement result of the circuit.
 105

Table 4.5 The measured parameter of OTA

Parameter Measured

Supply Voltage 400mV

Total Current 1.24µA

Gain 58dB

Bandwidth 282.16KHz

Unity Gain Bandwidth 18.04MHz

Input referred Noise 1.159µVrms

CMRR 89dB

PSRR 95dB

Power Dissipation 620nW

4.4 Notch filter

While recording ECG signal, power-line interference is the main

source of noise in ECG signal which is removed by notch filter. Narrow
bandwidth and high Q factor band-stop filter is designed to remove
interference. The notch filter is designed with 0.4V supply voltage,
49.286Hz centre frequency, 47.3Hz lower cut off frequency, 52.1 Hz
higher cut off frequency and 768.9nW power consumption. The
schematic circuit of filter is given in Fig.4.19 and simulation result is
shown in Fig.4.20.
 106

Fig.4.19 Schematic circuit of notch filter in Cadence Tool

Fig.4.20 Frequency response of notch filter

 107

The design summary of notch filter is given in Table 4.6 shown below.

Table 4.6 Design summary of notch filter

Parameter Measured value

Center Frequency
49.286Hz
Low cut-off Frequency
47.3Hz
High cut-off frequency
52.1Hz

4.5 QRS detection

The amplified ECG signal is required to analyze for identifying

cardiac arrhythmias. The QRS component is a predominant attribute
in ECG signal and is considered essential for cardiac arrhythmia
detection. A MFBP filter is designed to detect QRS complex with 0.4V
supply voltage and 829.8nW power consumption. AC analysis of filter
shows the center frequency, low cut-off frequency and high cut-off
frequency. The bandwidth of the filter is maintained narrower to
extract QRS components accurately which is 1Hz. The schematic
circuit of MFBP filter in Cadence environment is given in Fig.4.21.
 108

Fig.4.21 Schematic circuit of MFBP filter in Cadence Tool

The frequency response of filter is given in Fig.4.22 which shows

the low cut-off frequency of 47.3 Hz, high cut-off frequency of 52.1 Hz
and center frequency of 49.286 Hz. The design summary of MFBP
filter is given in Table 4.7.
 109

Fig.4.22 Frequency response of band pass filter

Center Frequency (fC) = 17.62 Hz

Table 4.7 Design summary of MFBP filter

Parameter Measured value

Center Frequency
17.058Hz
Low cut-off Frequency
16.414Hz
High cut-off frequency
17.91Hz
 110

4.6 R wave detection and shaping

A low power and low voltage approach for detection of R- peak

and shaping is presented and is simulated in 180nm Technology

Cadence environment. It has low power and is energy efficient as per

the measured result. This circuit is tested for the ECG frequency

ranging from 40 beats per min to 200 beats per min. The ECG signal

is filtered by band pass filter that allows only QRS complexes which is

given as input to the present system. The half wave rectifier removes

the negative components Q and S in the QRS complex and allows only

R peak. The sample and hold circuit samples these R peaks which set

an automatic threshold for the comparator and when turned ON, it

triggers a monostable that produces a 200ms pulse. This in turn

triggers a second monostable to produce a pulse of 50ms duration to

act as a sampling clock. The schematic and simulation result of half

wave rectifier in Cadence environment is given in Fig.4.23 & Fig.4.24.

 111

Fig.4.23 Schematic diagram of half wave rectifier in Cadence Tool

Fig.4.24 Simulation result of half wave rectifier

 112

The schematic and simulation result of sample hold circuit

in Cadence environment is given in Fig.4.25 & Fig.4.26.

Fig.4.25 Schematic diagram of sample and hold circuit in

Cadence Tool

Fig.4.26 Simulation result of sample and hold circuit

 113

The schematic and simulation result of comparator in Cadence

environment is given in Fig.4.27 & Fig.4.28.

Fig.4.27 Schematic diagram of comparator in Cadence Tool

Fig.4.28 Simulation result of comparator

 114

The schematic and simulation in Cadence environment of Mono

shot circuit with 200ms width and monostable circuit with 50ms width
is given in Fig.4.29, Fig.4.30, Fig.4.31 and Fig.4.32.

Fig.4.29 Schematic diagram of monostable circuit for 200ms pulse

width generation in Cadence Tool

Fig.4.30 Simulation result of monostable circuit for 200ms pulse width

generation
115

Fig.4.31 Schematic diagram of monostable circuit for 50ms pulse

width generation in Cadence Tool

Fig.4.32 Simulation result of monostable circuit for 50ms pulse

width generation
 116

Detection of R- peak and shaping circuit is designed with low

power and low voltage using body biasing technique. The overall
circuit and simulation result is given in Fig 4.33 & 4.34. This circuit is
suitable for 40mv to 220mv voltage and 5Hz to 12.5 KHz frequency
range. The operating voltage of circuit is + 400mv with 3.99µW power
consumption. Parameter measurement of QRS detection circuit is
given in Table 4.8.

Table 4.8 Parameter Measurement of QRS detection circuit

Circuit Parameter Measured

Ripple factor 2.11
Form factor 2.337
Peak Factor 3.814
Half wave rectifier Efficiency 42.78%
Offset voltage 11.468µV
Comparator Offset Voltage 651.9897 µV
Delay 3.298µs
Rise time 96.34 µs
Fall time 34.4 µs
Monostable circuit Offset voltage 184.492nV
Delay 130.8µs
Rise time 123µs
Fall time 504.59862µs
R-Peak detection
Operating voltage +400mv
and shaping circuit
Power consumption 3.997µW
 117

Fig.4.33 R peak detection and shaping circuit in Cadence Tool

Fig.4.34 Simulation result of R peak detection and shaping circuit

 118

4.7 ECG processing and arrhythmia detection

Each R peak is shaped into a pulse of 200ms width including
refractory period. The time interval between the falling edge of R peak
and rising edge of next R peak is measured by using a 12 bit counter
with a resolution of 1ms. During the rising edge of R peak, the
counter output is latched and the standard pulse width of 200ms is
added to calculate the RR interval. Similarly other 8 RR intervals are
also calculated and are labeled as RR t-1, RRt-2, RRt-3, RRt-4, RRt-5, RRt-6,
RRt-7 and RRt-8. The average of 8 RR intervals AR is calculated and
consecutive averages are labeled as ARt-1, ARt-2, ARt-3 and ARt-4. RTL
schematic diagram of ECG processing and arrhythmia detection in
Xilinx ISE is given in Fig.4.35.

Fig.4.35 RTL Schematic diagram of ECG processing and arrhythmia

detection in Xilinx ISE
 119

The wave forms of mono shot circuits of normal and abnormal

ECG signal are given in Fig.4.36 & Fig.4.37.

Fig.4.36 Simulation result of latch enable and counter reset signal

for normal shaped ECG signal

Fig.4.37 Simulation result of latch enable and counter reset signal

for abnormal shaped ECG signal
 120

11 arrhythmias are considered for processing of ECE for

arrhythmia detection which is mentioned in Table1.1. The QRS
complex is shaped into a square pulse of 200ms pulse. The design is
implemented on Spartan3 FPGA and the algorithm is written by using
Verilog HDL language. Adder (CSA) and multiplier (Wallace multiplier)
are used to develop algorithm which are consuming less power.
XILINX ISE13.1 is used for simulation and functional verification. The
on chip functionality is verified by chip scope analyzer. The result of
on chip verification is shown in Fig.4.36 & Fig.4.37.The simulation
results of different arrhythmias are shown in Fig.4.38, Fig.4.39,
Fig.4.40 and Fig.4.41. The dynamic power consumption is calculated
on Xilinx and was measured as 22mW and power analysis report is
shown in Fig.4.42.

Fig.4.38 Simulation result of arrhythmia APB detection

 121

Fig.4.39 Simulation result of arrhythmia asystole detection

Fig.4.40 Simulation result of arrhythmia bradycardia detection

 122

Fig.4.41 Simulation result of arrhythmia tachycardia detection

Fig.4.42 Power analysis of arrhythmia detection algorithm

The present work is compared with existing work which is

shown in Table 4.9.
 123

Table 4.9 Comparison with existing work

MULTIPLEXER DESIGN
S.N Author TITLE Journal Year Specificatio
o n
1. Przemys.a “Low Power, IJET 2010 Power
w High Dissipation
Rydygier, Dynamic 0.28 mW
Range with supply
Analogue voltage 3.3v
Multiplexer
for Multi-
Channel
Parallel
Recording
Neuronal
Signals
Using Multi-
Electrode
Arrays”
2. Jinhe Cai “A Portable Volume 1.8V power
Low-Power SPRINGE 42, 2014 supply and
7-Lead ECG R the power
Recorder required is
with a New around
Analogue 40mW
Front-End
IC”
3. Jun-Chau A 15-Gb/s IEEE VOL. 16, Power
Chien, 2:1 NO. 10, consumption
Multiplexer OCTOBER of 110 mW
in 0.18-_m 2006 from a
CMOS 2-V supply
voltage
4 Daniel 40-Gb/s 2:1 IEEE VOL. 38, 1.5V supply
Kehrer Multiplexer JSSC NO. 11, voltage and
and 1:2 NOVEMBE 108mW
Demultiplex R 2003 power
er in consumption
120-nm
Standard
CMOS
5 Present Supply
124
 work voltage 0.4V
and power
consumption
22.12μW

AMPLIFIER DESIGN
S.N Author TITLE Journals Year Specificat
o ion
1 Shahab Low Voltage IEEE Mar. 0.8v
Ardalan, Cascode Explorer 2002. POWER
Amplifier SUPPLY
AND 82uW
power
consumpti
on
2 Woradorn An Energy- IEEE VOL. 1, Power:7.5
Wattanapa Efficient TRANSACTI NO. 2, 6uW
nitch Micropower ONS JUNE
Neural 2007
Recording
Amplifier
3 Leon Fay A Micropower IEEE Vol. 3, Power:2.7
Electrocardio TRANSACTI no. 5, 6uW
gram ONS Oct
Amplifier 2009.
4 Jun Giap A low power ARPN VOL. 9, The power
Lau low noise Journal of NO. 12, consumpti
cmos Engineering DECEMB on is 5.51
amplifier for and Applied ER 2014 µW and
portable Sciences low noise
ecg of 17.2
monitoring µV/VHz at
application 10 Hz.
High
differential
voltage
gain of
54.5dB
and
71dB in
5 Jesus Ruiz A Low Noise Sensors 2015, Supply
Amplifier for 15 Voltage:1.
 125

Neural Spike 2V
Recording Power:
Interfaces 1.92uW
6 Siddharth Design of Indian Vol 9. Supply
Bhat Low Voltage Journal of May Voltage:0.
CMOS OTA Science and 2016 4V
Using Technology, Power:
Bulk-Driven 350uW
Technique
7 Present Voltage:0.
work 4V
Power:620
nW

Notch filter design

S.No Author TITLE Journal Year Specification
1. Akhilesh DESIGN AND IJAET 2011 Supply
Kumar NOISE voltage:1.8V
ANALYSIS OF Power:0.54mW
BIQUAD GIC
NOTCH
FILTER IN
0.18 µM
CMOS
TECHNOLOGY
2. Alessio Analysis and IEEE 2009 Power:32mW
Vallese Design of an Transaction
Integrated
Notch Filter
for the
Rejection of
Interference
in UWB
Systems
3. Sen A High-Q PIERS 2011 Power:1.2mW
Wang CMOS
Tunable
Notch Filter
4. Zhe- CMOS dual- IEEE 2007 Supply voltage:
Yang wideband 1.8V
Huang low-noise Power:24.07mW
amplifier
 126

with notch
filter for
3.1GHz–
10.6GHz
ultra-
wideband
wireless
receiver

5. Che- 0.18um IEEE 2007 Supply

Cheng CMOS Low- Voltage:1.8V
Huang Noise Power:21.9mW
Amplifier
with two
nd
2 -order
notch filters
for Ultra-
Wideband
Wireless
Receiver

6. Present Supply
work voltage:0.4V
Power:768.9nW

Band Pass filter design

S.N Autho TITLE Journal Year Specification
o r
1 C.J. An ECG- IEEE 2010 Power supply:1V
Deepu, on-Chip Power
X.Y. for consumption:9.6
Xu Wearable uW
Cardiac
Monitorin
g
Devices

2 Arash An Ultra Circuits and 2011, 2, Power

Low- Systems, 183-189 supply:500mV
Voltage Power
127
 and Low- consumption:28
Power uW
OTA
Using
Bulk-
Input
Techniqu
e and Its
Applicati
on in
Active-
RC
Filters
3 Kimmo A 1-V IEEE VOL. 52, Supply voltage:1
Lasane Analog TRANSACTIO NO. 12, to 1.8V
n CMOS NS DECEMB Current
Front- ER 2005 consumption:
End for 3uA
Detectin
g QRS
Complex
es in a
Cardiac
Signal
4 Marya A Low- IEEE 2005 Supply voltage:
m Power 3V to 4V
Shojae and Current: 22uA
i- Compact
Baghin Analog
i CMOS
Processin
g
Chip for
Portable
ECG
Recorder
s
7 Presen Supply
t work voltage:0.4V
Power: 829.8nW
 128

R wave detection design

S.N Author TITLE Journ Year Specification/Met
o al hod
1 Rodrigues A IEEE 2004 Wavelet transform
JN Wavelet Circuit Vol.4Pag
Based R- s and e: 13–
Wave Syste 16.
Detector ms
for
Cardiac
Pacemake
rs in 0.35
CMOS
Technolog
y
2 W. Heart IEEE 2006 1.5 muW power
Massagra Rate dissipation
m Variabilit
y
Monitorin
g and
Assessm
ent
System
on Chip

3 Deboleena R-peak Elseive 2012 Sorting and

Sadhukha detection r thresholding of the
na algorithm squared double
for ECG difference signal of
using the ECG data to
double locate the
difference approximate QRS
and RR regions, relative
interval magnitude
processing comparison in the
QRS regions.
4 C. Efficient IEEE 2016 Smart phone based
Crema R-peak (SAS) system
detection
algorithm
 129

for real-
time
analysis of
ECG in
portable
devices
5 Present Supply
work voltage:0.4v
Power:3.997μW

Arrhythmia detection algorithm implementation

S.N Author TITLE Journ Year Specification
o and Title al
1 Sheikh FPGA based ACEEE Vol. 3, -
Md. Rabiul Heart No. 1,
Islam Arrhythmia’s March
Detection 2013
Algorithm

2 Kalyana Abnormality ANAS 2015 Considered

Sundaram Detection of processing
C ECG Signals Speed
using Partial
Reconfigurati
on in FPGA
3 L.V.Rajani FPGA Based ICRTC 2015 94.76%
Kumari Arrhythmia accuracy
Detection

4 Chia-Hung FPGA JBISE 2012 -

Lin implementati
on of fractal
patterns
classifier for
multiple
cardiac
arrhythmias
detection
5 Prediction of IJAREE Issue Power:105.28m
R. Ventricular I 11, W.
Dhayabara Arrhythmia Novemb
ni for er 2016
130
 ECG System
Using FPGA
6 Present 11 arrhythmias
work are considered.
Power:22mW

4.7. Summary

Low power system on chip is designed for ECG processing and

arrhythmia detection. The unique characteristic of this research is that
a system on chip is designed and it can monitor EGG for long term,
ECG analysis and arrhythmia detection with less power consumption.
This might be a result obtained due to low power technique used in
design. The other existing designs are only capable of short term
monitoring. This research plays a crucial role in the field of medicine.
The arrhythmia alert is conveyed well in advance and thus by alerting
the patients themselves or the doctors to take necessary precautions,
it can rescue several lives.