CHAPTER 1

Introduction

1.1 Interconnects in VLSI Circuits

Integrated circuits (ICs) consist of millions of transistors and other devices. To per-
form the desired operations in ICs, the signals are carried from one transistor to another
transistor or other devices and interconnects are used to create the electrical connection
among those devices and transistors (Rabaey et al. 2002). Moores law predicts that
the numbers of transistors will be doubled in every eighteen months (Wilson 2013).
Scaling down improves the speed of the circuit (Saraswat and Mohammadi 1982). Due
to scaling of transistors for high speed requirements, the transistors are required to be
placed either to very close or apart in the ICs. The signal is carried from one point
of the circuit to another point to perform the desired operation. The length of the in-
terconnect depends on the application. Due to scaling down, there are possibilities of
increasing length of interconnects. Therefore, Scaling down of transistors will also af-
fect the performance of interconnects (Kil et al. 2008). The interconnects will have to
carry signals through a long distance which will also affect the delay and noise. The
length of the interconnect is directly proportional to the resistance and the propagation
delay for the signal depends on the resistance and capacitance (Rabaey et al. 2002).
Scaling down of technology node increases the resistivity of copper interconnects. An
interconnect material with lesser resistivity reduces the delay. Closely packed transis-
tors bring the interconnects closer in the ICs (Rabaey et al. 2002). Signal transmission
in these interconnects induces crosstalk due to coupling capacitance. Crosstalk of the
interconnect increases due to the wire pitch (Kumar Sharma et al. 2014) . Preferring
a material with lesser conductivity reduces the crosstalk, but increases the delay of the
interconnect. There is a trade-off between delay and crosstalk in selecting the inter-
connect material. Interconnects process the signals faster for high operating voltages.
At the same time, high operating voltages have more power dissipation. Design of low
power devices for future requirements, require low operating voltages for interconnects.
Low-power operation is also required for extended battery life in hand held instruments
(Pable and Hasan 2012a). The above requirements leads to the scaling of supply volt-
age and threshold voltage. Scaling the supply voltage reduces the power dissipation

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and increases the propagation delay. Scaling the threshold voltage leads to more leak-
age power dissipation (Sharma and Pattanaik 2013). Process technology scaling in ICs
is also increasing the interconnect delay (Kureshi and Hasan 2009). Buffer insertion
reduces the delay in interconnects (Rabaey et al. 2002). Designing of interconnects at
nanometer scale is a major challenge. Copper interconnects used in the current silicon
devices are more feasible for high technology nodes (Ceyhan and Naeemi 2013). But
at low technology nodes, many challenges like grain boundary scattering, electromag-
netic interference, and electro migration affect the performance of copper interconnect
which are pushing engineers to concentrate on carbon nanotube (CNT) interconnects
(Naeemi et al. 2005). Buffer insertion is a good solution in CNT interconnects to meet
the challenges. Designing buffers to reduce the delay and power dissipation will play
a major role in future VLSI interconnects. Carbon nanotubes are classified into sin-
gle walled carbon nanotube (SWCNT), Multi walled carbon nanotube (MWCNT) and
Mixed Carbon nanotubes. Mixed CNT bundle interconnects are better in terms of delay
as compared to SWCNT and MWCNT interconnects (Sathyakam and Mallick 2011).
Designing a suitable buffer for global VLSI interconnects by selecting the proper con-
figuration of mixed CNT bundles for sub threshold applications are the major focuses
of CNT based VLSI interconnects.

1.2 Types of Interconnects

The interconnects are classified as local interconnects, intermediate interconnects and

global interconnects based on its length. Interconnects of length up to 300µm are called
local interconnects. Interconnects between 300µm to 700µm are called as intermediate
interconnects, and interconnects up to or more than 1200µm are called global intercon-
nects. Fig 1.1 shows the various types of interconnects. Based on the length the delay
of the interconnect varies. Global interconnects have largest RC delay as compared to
the others.

1.2.1 Local interconnects

Local interconnects are used to connect the nearest transistors or to connect fewer num-
ber of transistors or gates in an integrated circuit. Local interconnects are used for
connecting the gate and the diffusion area in transistors (Bakoglu 1990). In the closely
packed integrated circuits to connect the nearest cells or logic blocks, these interconnect
are used. Connecting the gates of multiple transistors within a single block are possible
using these interconnects (Bakoglu 1990). These interconnects are also used to connect
the channel region between source to drain or to gate (Saraswat and Mohammadi 1982).
Local interconnects are very short, and delay in these interconnects are very less.

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 Fig. 1.1 Types of interconnects (Saraswat and Mohammadi 1982)

1.2.2 Intermediate interconnects

Intermediate interconnects are lengthier than local interconnects. Scaling the technol-
ogy node or voltage at intermediate interconnects have lesser effect in delay compared
to the global interconnects. These interconnects are basically used to distribute the
clock and the other signals to the network within a functional block (Bakoglu 1990).
They have lesser resistance compared to global interconnect, so distribution of clock
signal within a functional block of intermediate length is more effective (Saraswat and
Mohammadi 1982). These intermediate interconnects are applicable for plasmonics
waves. Here the propagation lengths are short enough for plasmonics and the cross
sectional area is also below the diffraction limit. connecting wafer to wafer or smaller
circuit blocks are possible with these intermediate interconnects.

1.2.3 Global interconnects

Global interconnects are more lengthy and consume more RC delay. Distribution of
clock and other signals between the functional blocks and logic cells is possible by
these interconnects (Bakoglu 1990). Connecting multiple power supplies or ground for
the devices in ICs are possible using these interconnects (Saraswat and Mohammadi
1982). These interconnects are also able to distribute the common power or ground
signals to large number of transistors or functional blocks within the integrated circuit.
These interconnect need buffers to be inserted between them to reduce the delay

1.3 Scaling of interconnects

Transistors are scaled based on Moores law to reduce its size and to increase the number
of transistors in ICs. This leads to increases in length of the interconnect and intercon-

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nect requirements, due to that the interconnect parasites also increases (Rabaey et al.
2002). Scaling of interconnects are also essential. Scaling of the interconnects leads
to variations in its capacitance and resistance. While trying to reduce the resistance by
scaling, the capacitance may increase, which would again increase the delay.

1.4 Interconnect materials

Proper selection of interconnect material is necessary for high speed and low power
dissipation in interconnects. The resistivity and the mean free path of the materials play
a major role in the interconnect materials. The materials with low resistivity have more
speed and materials with higher mean free path is also required for the free movement
of electrons without scattering at the lower technology nodes which again improves the
speed and current density.

1.4.1 Copper interconnect

Copper materials have lesser resistivity compared to the aluminium. The excellent prop-
erty of copper is that it has more resistance to electro migration. It is able to withstand
high temperatures up to certain level and has lesser corrosion effect compared to alu-
minium (Rai and Sarkar 2011). Copper materials are used to produce a more narrow
interconnect. The challenges in dealing with copper interconnect is that copper can eas-
ily diffuse into the silicon materials for higher temperatures and leads to short circuit.
Closely packed integrated circuits used copper as their interconnect material because it
has high heat conductivity. At the same time due to the higher switching operation of
integrated circuits, heat dissipation is higher. Aggressive scaling of technology node to
reduce the gate delay increases the resistivity of copper material due to grain boundary
scattering (Naeemi et al. 2005). This leads to the introduction of new materials like
carbon nanotubes for lower technology nodes.

1.4.2 Carbon nanotube interconnect

Carbon nanotubes have excellent electrical, mechanical and thermal properties. The
resistivity of the material increases based on its size (Ceyhan and Naeemi 2013). At
lower technology nodes the traditional copper material has increase of resistivity. Since
carbon nanotubes have more conductivities than copper, they are preferred as intercon-
nect material. The mean free path of electrons in carbon nanotube is 1000nm compared
to copper which is of 400nm. Since the carbon nanotube tubes have longer mean free
path the scattering of electrons occurs lesser than copper. Grain boundary scattering
occurs at lower technology nodes which affects the copper interconnects. These issues
are overcome by carbon nanotubes. Higher mean free path leads to movement of elec-
trons faster, which also improves the speed of interconnects. Higher kinetic inductance

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in CNT interconnects reduces the skin effect in CNT bundles. Based on this, the CNT
bundle could be used for high frequency applications (Li et al. 2009). Carbon nanotube
bundle interconnect have lower signal delay and optimal wire size (Qian et al. 2013).
Carbon nanotubes have better thermal conductivities and electrical conductivities, so
they can be preferred in interconnects for reducing the delay and heat dissipation.

1.4.3 CNT interconnects over copper interconnects

Carbon nanotubes are more promising materials for VLSI interconnects. Carbon nan-
otubes have been widely used as interconnects for deep sub-micron technologies due
its ability to resist electro migration (Rossi et al. 2007). While using copper materials
as interconnects at lower technology node, the scattering of electrons in the surface and
boundary increases the resistivity of copper interconnects (Alam et al. 2011). A ca-
pacitive analysis of mixed CNT bundles with the copper shows that the capacitance of
the mixed CNT bundle reduces compared to the copper interconnects for intermediate
and global interconnect levels (Alam et al. 2011). A capacitive coupling model is pro-
posed for SWCNT bundles. The proposed model has improved reduction in crosstalk
noise voltage compared to its copper counter parts for increase of temperature (Rai and
Sarkar 2015). SWCNT interconnects have high resistivity, so the extension of SWCNT
to SWCNT bundles is necessary. Usage of multiple parallel tubes can further improve
the RC delay of SWCNT interconnects with only slight degradation in energy delay
product (EDP). Even the broken tubes in multiple can perform better than copper in-
terconnects (Ceyhan and Naeemi 2013). Comparison of CNT bundle with the copper
in terms of repeater insertion shows that the repeater insertion is required for the CNT
bundles with length of interconnects comparatively double the length of copper inter-
connects and also requires lesser buffer size than copper interconnects (Patel and Kim
2010). Optimization techniques like shielding, boosting, skewing, boostable repeater
which are performed for copper interconnects can be extended to CNT based intercon-
nects (Karthikeyan and Mallick 2017a). Since CNT based interconnects are better than
copper interconnects, using these techniques could further improve the performance of
interconnects. SWCNT bundle interconnects are more suitable for lengthy intercon-
nects as compared to copper interconnects. Scaling the technology node, the improve-
ment in performance is more for SWCNT bundle interconnects compared to the copper
interconnects (Das and Rahaman 2012). MWCNT interconnects shows improvement in
delay compared to copper wires for intermediate and global interconnects. MWCNTs
are easier to fabricate, they can be attractive for use as horizontal interconnects in VLSI
circuits (Li et al. 2008). Inductance performances of SWCNT, MWCNT and mixed
CNT bundles have been analyzed (Wang et al. 2007). The comparison of CNT bundles
with copper wire was done and shown that the mixed CNT bundles are preferred for

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inductors and RF applications (Wang et al. 2007).

1.5 Design issues in interconnects

The major issues in the design of interconnects in integrated circuits is the area, power
dissipation and delay in processing the signal. Noise, electromagnetic interference and
crosstalk are the other issues in design of the interconnects. Lot of works were con-
centrated on reducing these issues. Interconnect delay due to the parasites are the main
issues in the interconnects. Since the integrated circuits requires lot of interconnects to
be running into it. The interconnects have to be placed such that to avoid delay, power
dissipation and crosstalk. When two parallel wires closely running leads to capaci-
tive coupling, i.e., the transfer of energy within the electrical network (Kumar Sharma
et al. 2014). This capacitive coupling is called crosstalk. It also induces delay in the
wires. When the length of these wires increases, the crosstalk and the delay induced
due to that will also increase. The impact of interconnects in ICs were negligible, and
they were not considered up to 0.5µm technology node, below that the resistance and
capacitance have a lot of impact on performance of the circuit (Kumar Sharma et al.
2014). The time taken for signal transfer between chips or parts of the circuit consumes
a particular amount of delay in the processing unit (Awwad and Nekili 2001). Due to
the increasing demand of portable devices, increase of leakage power dissipation and
self-heating leads to the requirement of low power devices. Ultra-low power applica-
tions are required to have an extended battery life in portable devices. These low power
applications requires scaling of voltage or scaling of technology node. The technol-
ogy scaling degrades the copper interconnects from delay, power, reliability and leads
to electro migration in strong inversion operating region (Pable and Hasan 2012a). At
lower technology nodes the traditional copper interconnects suffers from increase in
resistivity due to surface roughness, grain boundary scattering, and electro migration
problems due to lower current densities (Kureshi and Hasan 2009). Increase in length
of the interconnect increases the propagation delay of the interconnect quadratically
(Rabaey et al. 2002). Buffer insertion is a solution to change the delay of the inter-
connect length from quadratically to linear (Srivastava et al. 2010). The buffer also
consumes some amount of delay and power dissipation. The design of buffer should be
such that the delay of the buffer should be within the delay of the interconnect, similarly
the power dissipation. So sizing of buffer, proper designing and placing of buffer are es-
sential. So the interconnects have to be optimized in parallel with the gate or transistor
to improve the performance of integrated circuits. Voltage scaling is a trend to reduce
the power dissipation. Reduced energy point can be achieved in sub threshold operating
region, but due to the lowering of current drive increases the delay of CMOS device in
sub threshold region (Ho, Chen and Su 2012). The performance of interconnects also

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depends on material of the interconnect, its geometry and the technology.

1.6 Motivation and Objectives

Interconnects are the integral part of integrated circuits which are used to carry the
signal within the integrated circuits. They are also used to carry the power, ground
and clock signals to the entire part of the circuit. Lot of optimizations have been done
at the circuit level, transistor level and architecture level in the integrated circuits. In
all these cases, the impact due to interconnect is not considered. Some of the works
concentrated on optimization of interconnects compared to optimization of transistors
and other parameters. Therefore, it is basically to motivate the researchers to optimize
the interconnects in all the possible levels. Interconnects also consumes a lot of delay,
power dissipation and area compared to the transistors in integrated circuits. Our main
objective is to optimize the parameters like delay and power dissipation. Scaling the
dimensions in integrated circuits leads to increase in the length of the interconnect. To
optimize these parameters, scaling down of the dimensions of wires can be done, or by
using buffers which divides the lengthy wire into many number of segments to reduce
the delay, we can also boost the signal strength of the interconnect using boostable
repeaters. Here the care should be taken to avoid power dissipation. Our main objective
is to design buffers to reduce the delay and power dissipation. CMOS buffers are mostly
preferred to drive the interconnects. Our aim is to use devices like transmission gates
or source follower and other devices as buffer. CMOS inverters are also used to drive
the interconnect. We need to improve the signal strength for this driver by designing a
separate circuit. Our other objectives are to select a material which could replace the
traditional copper interconnect. Material like carbon nanotubes must be the best choice.
Because they have excellent electrical and mechanical properties, these properties are
more suitable for carbon nanotubes to be an interconnect. Different configurations of
carbon nanotubes like single walled carbon nanotube (SWCNT), Multi walled carbon
nanotube (MWCNT) and Mixed CNTs are available. Our objective is to identify a
particular configuration of carbon nanotube to reduce the delay and power dissipation
in the interconnect. There are a lot of optimization techniques like buffer insertion,
boostable buffer, skewing, surfing, shielding and bootstrapping the CMOS driver were
applied to copper interconnect (Kim et al. 2012) but only very few techniques like
buffer insertion were applied to carbon nanotube interconnects. Our objective is to
utilize all these techniques to carbon nanotube interconnects for lower delay and power
dissipation as compared to copper interconnects.

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1.7 Summary of contributions

Our initial objective is to improve the signal strength required for the interconnect. Our
contributions are mainly on designing a buffer suitable for the interconnect, and also
to improve the signal strength for the CMOS driver which drives the interconnect. We
have designed a new buffer using transmission gate, CMOS inverter and charge pump
to improve the speed of the interconnect. We have named it as buffer for high perfor-
mance in VLSI interconnects. This buffer has lesser delay and more power dissipation
compared to the conventional CMOS buffer. The amount of reduction in delay is more
compared to the increase of power dissipation. We have designed another buffer called
High speed and low power buffer for VLSI interconnects, this buffer has lesser delay
and power dissipation compared to the conventional CMOS buffer. The proposed buffer
also has more reduction in delay with an increase of power dissipation compared to the
low power transmission gate (LPTG) CMOS buffer (Sharma and Pattanaik 2013). We
have also designed a bootstrapped CMOS driver called Body biased sub threshold boot-
strap CMOS driver which can improve the signal strength for the CMOS driver. The
proposed CMOS driver is applied with proper body biasing to reduce the delay and
power dissipation compared to the conventional bootstrapped CMOS driver. Optimiza-
tion techniques like buffer insertion, boostable buffer, shielding, skewing, surfing and
other techniques were used in copper interconnects. Most of the techniques were not
used in carbon nanotube interconnects. We have done a review on Optimization tech-
niques for CNT based VLSI interconnects and explained the possibility of extending the
techniques to CNT based VLSI interconnects. In CNT interconnects, basically CMOS
devices were used as a driver or buffer. We have used transmission gate as a buffer
for the first time in CNT interconnects. We have made a comparison of CMOS buffer
with transmission gate buffer in CNT interconnects. We have also identified the par-
ticular configurations of CNTs from various configurations of CNTs and shown which
configuration can be used for lesser delay or power dissipation or power delay product.
We have also done the comparison at sub threshold region of operation and identified
a particular CNT configuration which is more suitable for the buffer insertion of the
interconnect.

1.8 Organization of the thesis

The summary of the thesis has been organized as follows, Chapter 1 consists of Intro-
duction with design issues, motivation and summary of contributions, Chapter 2 con-
sists of the literature review with various issues faced in the interconnects, optimiza-
tion techniques in the interconnects, devices used to drive the interconnects, Chapter
3 consists of delay and power analysis of the repeater with the explanation of works

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high speed and low power buffer for VLSI interconnects, Chapter 4 consists of the in-
volvement of carbon nanotubes as interconnects and the comparison of various types of
carbon nanotubes used as interconnects. Chapter 5 consists of Buffer insertion in car-
bon nanotube based VLSI interconnects, Comparison of transmission gate buffer with
conventional CMOS buffer for various configurations of carbon nanotubes. Chapter 6
consists of a new proposed bootstrapped CMOS driver and its comparison with the con-
ventional bootstrapped CMOS driver. Chapter 7 consists of conclusion and the future
works that can be done, followed by the References.