Sohan Internship Report Final

VISVESVARAYA TECHNOLOGICAL UNIVERSITY
Jnana Sangama , Belagavi ,Karnataka_590014
An Internship Report
On
“VLSI PHYSICAL DESIGN FLOW”

Submitted in partial fulfilment for the award of the degree
Bachelor of Engineering
In
Electronics & Communication Engineering
Submitted by
SOHAN U
1BI17EC120
Internship Carried Out at

MICROCHIP TECHNOLOGY
EPIP, Industrial Area, Whitefield, Bengaluru, Karnataka 560048
Internal Guide External Guide

MRS.VIDYASARASWATHI H N MR. KISHORE R
ASSISTANT PROFESSOR SENIOR ENGINEER
DEPARTMENT OF ECE, BIT PHYSICAL DESIGN, MICROCHIP
DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING BANGALORE INSTITUTE OF TECHNOLOGY
K R Road, V.V Puram, Bengaluru_560004 2020-2021
BANGALORE INSTITUTE OF TECHNOLOGY
K.R. Road, V. V Puram, Bengaluru -560004

Phone: 26613237/26615865, Fax:22426796
www.bitbangalore.edu.in
Department of Electronics and Communication Engineering.

CERTIFICATE
Certified that the Internship / Professional practice work entitled “VLSI PHYSICAL
DESIGN FLOW” carried out by MR. SOHAN U, bearing USN: 1BI17EC120 a
bonafide student of BANGALORE INSTITUTE OF TECHNOLOGY in partial
fulfillment for the award of Bachelor of Engineering in Electronics and
Communication Engineering of the Visvesvaraya Technological University,
Belgaum during the year 2020-2021. It is certified that all corrections indicated for
Internal Assessment have been incorporated in the Report deposited in the
departmental library. The Internship report has been approved as it satisfies the
academic requirements in respect of Internship work prescribed for the said Degree.
MRS.VIDYASARASWATHI H.N DR. K V PRASAD

Assistant Professor Professor & H.O.D
Dept. of E.C.E Dept. of E.C.E
External Viva
Name of the examiners Signature with date
1.
2.
ACKNOWLEDGEMENT
I take this opportunity to express our sincere gratitude and respect to the
Bangalore Institute of Technology, Bangalore for providing us an opportunity to
carry out my internship training at MICROCHIP TECHNOLOGY.
I express my sincere regards and thanks to KISHORE
RAMACHANDRA, Senior Engineer, physical design, Microchip. For giving
necessary advices and guidance.
With profound sense of gratitude, I acknowledge the guidance and support

extended by MRS.VIDYASARASWATHI H.N, Assistant Professor, Department of
Electronics & Communication Engineering, BIT, Bangalore. Her incessant
encouragement and valuable technical support have been of immense help in
realizing this internship training. Her guidance gave us the environment to enhance
our knowledge, skills and to reach the pinnacle with sheer determination, dedication
and hard work.
I would like to thank Dr. A.R HEMANTH KUMAR, professor and

Internship coordinator, Department of Electronics & Communication Engineering,
BIT, Bangalore.
I express my sincere regards and thanks To Dr. K V PRASAD, Professor and

HOD, Electronics & communication Engineering, BIT and Dr. M U ASWATH,
Principal, BIT, Ban- galore, For their encouragement and support throughout the
internship work.
I also extend our thanks to the entire faculty of the Department of ECE, BIT,
Bangalore, who have encouraged me throughout the course of bachelor degree.
SOHAN
(1BI17EC120)
ABSTRACT
Microchip Technology is one of the pioneering company in the production of

the semiconductors. The main charter of the company is to produce top quality
semiconductor products and provide IT support. Microchip Technology offers
support and resources to educators, researchers and students in an effort to increase
awareness and knowledge of embedded applications.The purpose of the company is
to Empowering innovation which enhances the human experience by delivering smart,
connected and secure technology solutions. Physical design team is one of the core
group in microchip. The main aim of the physical design group is to use to design the
chip using the cadence software. This involves going through a few steps to reduce
the overhaul area, to reduce the power consumption and improve the timing analysis
of the design.
CHAPTER CONTENTS PAGE
NUMBER:
CHAPTER 1: PROFILE OF THE ORGANIZATION 1-18
1.1 Introduction 1
1.2 History 1
1.3 Company history 6
1.4 Products of microchip 9
1.5 Company division 14
1.6 Company major products 14
1.7 Business partners 14
1.8 Organization Structure 15
1.9 Roles and responsibilities 17
1.10 Company achievements 18
CHAPTER 2: ABOUT THE DEPARTMENT 19-29

2.1 ASIC FLOW 19
2.1.1 PNR 20
CHAPTER 3: TASKS PERFORMED 30-37

3.1 Sanity checks 30
3.2 Netlist checks 31
3.3 Timing checks 32
3.3.1 unconstrained end points 32
3.3.2 missing input output delays 32
3.3.3 multiclock driven registers 33
3.4 Library checks 33
3.5 Blockages 33
3.5.1 Soft blockage 34
3.5.2 Hard blockage 34
3.5.3 Partial blockage 34
3.5.4 Routing blockage 35
3.6 Guide fence region 35
3.7 Special cells 36
Chapter 4: PHASE 1 AND 2 OF THE WORK AND 37-45

OBSERVATION
4.1 FINFET 38
4.1.1 working principle 39
4.1.2 Construction 40
4.1.3 silicon based finfet 42
4.2 Application of finfet 44
4.3 Future scope 45
Chapter 5: PHASE 3 AND 4 OF THE WORK AND 46-54

OBSERVATION
5.1 STA 46
5.2Arrival time 46
5.3 Skew 47
5.3.1 positive skew 47
5.3.2 negative skew 47
5.4 Slack 47
5.5 Reg to reg path 49
5.6 Setup and hold 51
5.7 Propagation delay 53
CHAPTER 6: REFLECTION NOTES 55-57
6.1 Internship outcome 55

6.2 Non technical outcome 55
6.3 Conclusion 56
6.4 Reference 57
Table of Figures
Figure 1: Microchip logo.............................................................................................14
Figure 2: Microchip Processor.....................................................................................23
Figure 3 :Microchip MC608.......................................................................................24
Figure 4: Data converter block diagram......................................................................25
Figure 5:FPGA.............................................................................................................26
Figure 6:LED Driver....................................................................................................27
Figure 7:ROM..............................................................................................................27
Figure 8: Microchip products......................................................................................28
Figure 9:MCU Module................................................................................................28
Figure 10:Organaization structure...............................................................................32
Figure 11:ASIC FLOW...............................................................................................35
Figure 12:PNR FLOW.................................................................................................36
Figure 13:RTL FLOW.................................................................................................38
Figure 14:Latch up.......................................................................................................43
Figure 15:Types of sanity checks................................................................................46
Figure 16:FINFET.......................................................................................................55
Figure 17:Diagram Depicting Working Principle ofFINFET………. ………… 56
Figure 18:FINFET Structure........................................................................................57
Figure 19:Construction of FD-SOI FINFET...............................................................58
Figure 20: Image Showing Construction of Silicon-Based Bulk FINFET..................58
Figure 21:Hard mask...................................................................................................59
Figure 22:2-D View of Layers of FINFET..................................................................60
Figure 23:3-D View of Layers of FINFET..................................................................61

Figure 24: Arrival time................................................................................................64
Figure 25: Setup and hold slack...................................................................................65
Figure 26: Reg to reg path...........................................................................................66
Figure 27:Reg to out....................................................................................................67
Figure 28:in to reg.......................................................................................................68
Figure 29:Setup............................................................................................................69
Figure 30:Hold.............................................................................................................69
Figure 31: setup violation............................................................................................70
Figure 32: Propagation delay.......................................................................................71
BANGALORE INSTITUTE OF TECHNOLOGY
VISION
To establish and develop the Institute as a center of higher learning, ever abreast with
expanding horizon of knowledge in the field of engineering and technology, with
entrepreneurial thinking, leadership excellence for life-long success and solve societal
problem.
MISSION
• Provide high quality education in the engineering disciplines from the

undergraduate through doctoral levels with creative academic and professional
programs.
• Develop the Institute as a leader in Science, Engineering, Technology and
management, Research and apply knowledge for the benefit of society.
• Establish mutual beneficial partnerships with industry, alumni, local, state and
central governments by public service assistance and collaborative research.
• Inculcate personality development through sports, cultural and extracurricular
activities and engage in the social, economic and professional challenges.
LONG TERM GOALS
• To be among top 3 private engineering colleges in Karnataka and top 20 in India.
• To be the most preferred choice of students and faculty.
• To be the preferred partner of corporate.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION
VISION
Imparting Quality Education to achieve Academic Excellence in Elec tronics and

Communication Engineering for Global Competent Engineers.
MISSION
• Create state of art infrastructure for quality education.

• Nurture innovative concepts and problem solving skills.
• Delivering Professional Engineers to meet the societal needs.
PROGRAM EDUCATIONAL OBJECTIVES
• Prepare graduates to be professionals, Practicing engineers and entrepreneurs in the

field of Electronics and communication.
• To acquire sufficient knowledge base for innovative techniques in design and

development of systems.
• Capable of competing globally in multidisciplinary field.
• Graduates will maintain and improve technical competence through continuous

learning process.
PROGRAM SPECIFIC OUTCOMES
PSO1: Core Engineering: The graduates will be able to apply the principles of
Electronics and Communication in core areas.
PSO2: Soft Skills: An ability to use latest hardware and software tools in
Electronics and Communication engineering.
PSO3: Successful Career: Preparing Graduates to satisfy industrial needs .
COURSE OUTCOMES OF 17EC84
After going through the internship the student is able to:
CO1: Apply engineering and management principles.
CO2: Analyze real-time problems and suggest alternate solutions.
CO3: Communicate effectively and work in teams.

CO4: Inbibe the practice of professional ethics and need for lifelong learning.
CO TO PO & PSO MAPPING
PO 1 PO 2 PO 3 PO 4 PO 5 PO 6 PO 7 PO 8 PO 9 P0 PO 11 PO 12 PSO 1 PSO 2 PSO

10 3
CO 1 H M H M --- M ---- --- --- L --- --- H --- H
CO 2 --- H --- H M M --- L --- --- --- --- L L L
CO 3 --- --- --- --- L --- M H H H --- --- ---- M ---
CO 4 --- --- --- --- L --- H --- --- M H H M H M

VLSI PHYSICAL DESIGN 2020-2021
CHAPTER 1
PROFILE OF THE ORGANIZATION
1.1 INTRODUCTION
Microchip Technology Inc is a publicly-listed American corporation that

manufactures microcontroller, mixed-signal, analog and Flash-IP integrated circuits.
Its products include microcontrollers(PIC, dsPIC, AVR and SAM),Serial EEPROM
devices, Serial SRAM devices, embedded security devices, radio frequency (RF)
devices, thermal, power and battery management analog devices, as well as linear,
interface and wireless solutions.
Microchip Technology offers support and resources to educators, researchers

and students in an effort to increase awareness and knowledge of embedded
applications. Support includes access to labs, curricula and course materials, One-on-
one consultations, online resources (e.g., code examples, textbook recommendations),
training at regional training centers, silicon donations,assistance finding low cost
development tools, free versions of Microchip programming tools and product
discounts.
Figure 1: Microchip logo
Department of Electronics and Communication Engineering, PAGE 14

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1.2 HISTORY
Microchip Technology was founded in 1987 when General Instrument spun off
its microelectronics division as a wholly owned subsidiary. The newly formed
company was a supplier of programmable non-volatile memory, microcontrollers,
digital signal processors, card chip on board, and consumer integrated circuits. An
initial public offering later in the year was canceled because of the October 1987
stock market crash. Microchip Technology became an independent company in 1989
when it was acquired by a group of venture capitalists led by Sequoia Capital. In
the same year, Microchip Technology announced the release of small,
inexpensive 8-bit reduced instruction set computing (RISC) microcontrollers for

$2.40 apiece whereas most RISC microcontrollers were 32-bit devices selling for
hundreds of dollars.
In 1990, 60% of Microchip Technology's sales were from the disc drive industry
and the product portfolio relied heavily on commodity EEPROM products. The
company was losing $2.5 million per quarter, had less than 6 months of cash in
reserve, had exhausted lines of credit, and was failing to control expenses. Early in the
year, the venture capital investors accepted an offer to sell Microchip Technology to
Winbond Electronics Corporation of Taiwan for $15 million. Winbond Electronics
backed out of the deal after the Taiwanese stock market decrease in May 1990. Vice
President of Operations, Steve Sanghi, was named president and chief operating
officer of Microchip Technology in 1990. After several quarters of losses, Sanghi
oversaw Microchip Technology's transition from selling commodity-based products
to specialized chips, such as the RISC technology.
Microchip Technology conducted an IPO in 1993, which Fortune magazine cited

as the best performing IPO of the year with a stock appreciation of 500% and over $1
billion in market . At the end of 2015, Microchip Technology posted its 100th
consecutive quarter of profitability. In-line with the general consolidation of the
semiconductor industry, Microchip Technology purchased 17 semiconductor

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manufacturers from 2007 through 2017.
Microchip Technology offers 8-bit microcontrollers, 16-bit PIC

microcontrollers, dsPIC digital signal controllers, 3analog and interface products,
security authentication products, timing/communication/real-time clock and
calendar products, real-time clock and calendar devices, memory products, wireless
products, high-throughput USB and Ethernet interface solutions[buzzword], MOST
technology, embedded controllers and super I/O devices, touch, multi- touch and 3D
gesture control solutions[buzzword], power over Ethernet systems and ICs, and field
programmable gate arrays (FPGAs).
8-bit microcontrollers
Microchip Technology's 8-bit portfolio consists of over 1,200 devices

constructed under two architectures: PIC microcontrollers or AVR microcontrollers.
Key features of the 8-bit microcontrollers are Core Independent Peripherals, low-
power performance with picoPower and eXtreme Low Power (XLP) technology and
EMI/EMC performance.
The 16-bit microcontrollers, such as the PIC24, offer an upgrade over the 8-bit
devices in features and peripherals (e.g., more memory, additional pins. The 16-bit
microcontrollers are constructed under the PIC microcontroller architecture.
Microchip Technology's 32-bit product portfolio run at up to 600 DMIPs with up

to 2048 KB Flash and 512 KB RAM with 32 MB integrated DDR2 dynamic
random-access memory (DRAM) or 128 MB externally addressable options. The
32-bit portfolio addresses advanced graphics and Internet of things (IoT)
applications.

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32-bit microprocessors
The 32-bit Arm microprocessors were designed for applications beyond the 32-
bitmicrocontrollers with 600 MHz (942 DMIPS) operation, support for up to 512 MD
of external DDR2 or DDR3 DRAM and power down to 0.3mW sleep. Available
peripherals and users interfaces include gigabit Ethernet MAC addresses, USBs,
hardware video decoding, capacitive sensing, 12- bit CMOS sensors, I²S audio
interfaces and 24-bit graphic LCD controllers with overlays.
Analog and interface products
Microchip Technology offers a broad portfolio of analog products that address

thermal management, power management, battery management, mixed-signal, linear,
interface, safety and security needs. The product portfolio includes stand-alone analog
and interface devices in highly integrated solutions[buzzword] that combine various
analog functions, save space, support a variety of bus interfaces and enhance analog
features on microcontrollers, digital signal controllers, microprocessors and FPGAs.
The power solutions[buzzword] include silicon diodes, MOSFETs, insulated-gate
bipolar transistors, silicon carbide MOSFETs and Schottky diodes.
Digital signal controllers
The dsPIC product family of digital signal controllers includes a digital signal
processor engine with up to 100 MIPS of motor control that offers variable speeds,
constant torque PI control.
Embedded controllers and super I/O
Microchip Technology offers computer-related products including embedded

controllers based on enhanced serial peripheral interface (eSPI) bus technology,
Input/Output (I/O) devices, keyboard controllers and root of trust, secure boot and
authentication and system management devices. Common applications include

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traditional computing applications (e.g., laptop computers) and embedded computing,

such as interactive kiosks, networking equipment, and automated teller machines.
Memory products
Microchip Technology offers a wide-range of memory products that includes

serial EEPROM, serial SRAM, serial flash, serial NvSRAM, serial EERAM, parallel
EEPROM, parallel one-time programmable flash, parallel flash and Crypto Memory
devices.
Programming and development tools
Microchip Technology offers a variety of programming tools and other tools to

support the use of microcontrollers, digital signal controllers, and microprocessors.
The MPLAB and Atmel Studio ecosystems include integrated development
environments, compilers, configurators, MPLABPICkit™),MPLAB devices), and
debuggers.
Security and authentication products
Microchip Technology offers crypto element devices that provide authentication,

data integrity, and confidentiality in a variety of applications, such as disposables,
accessories and nodes. The crypto element devices use ultra-secure, hardware-based
cryptographic countermeasures including tamper detection.
Timing, communication and real-time clock and calendar products
Microchip Technology offers oscillators, clock generators, clock and data

distribution products and real-time clock and calendar devices. The oscillator product
line offer low jitter and low power online-configurable products with quartz-based or
MEMS silicon-based resonator options. The clock generation product line offer

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online-configurable, single chip, multiple-frequency clock tree options. The clock

and data distribution product line offers buffers, logic translators and
multiplexers. The packet network synchronization product line includes
ITU-T/IEEE® standards-compliant digital phase-locked loops for synchronous
Ethernet as well as IEEE 1588 based applications. The real-time clock and calendar
devices offer a battery back-up capability, digital timing, and on-board EEPROM and
SRAM memory.
USB and Ethernet interface products
Microchip Technology offers Ethernet solutions[buzzword] including Ehternet

PHYs, switches, controllers and bridge devices. The USB solutions[buzzword]
include USB smart hub controllers, power delivery and charging,
transceivers/switches, flash memory controllers and security solutions.[buzzword] .
Product milestones
In April 2009, Microchip Technology announced the nanoWatt XLP

microcontrollers, claiming the world's lowest sleep current. Microchip Technology
had sold more than 6 billion microcontrollers as of 2009. As of 2011, Microchip
Technology ships over a billion processors every year. In September 2011, Microchip
Technology shipped the 10 billionth PIC microcontroller.
1.3 COMPANY STRATEGY
PURPOSE
Empowering innovation which enhances the human experience by delivering
smart, connected and secure technology solutions.

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MISSION STATEMENT
Microchip Technology is a leading supplier of embedded control solutions by

delivering a broad spectrum of innovative standard and specialized microcontrollers;
FPGA products; analog, mixed- signal, timing and security products; wired and
wireless connectivity products; related non-volatile memory products and Flash-IP
solutions.
In order to contribute to the ongoing success of customers, employees,

shareholders and the communities in which we operate, our mission is to focus
resources on high value, high quality products, total system solutions, software and
services, and to continuously improve all aspects of our business, providing an
industry leading return on investment.
VISION
Be the very best embedded control solutions company ever.
GUIDING VALUES
Quality Comes First
We are on a relentless quest for perfection and are committed to the goal of zero
defects. We will perform correctly the first time and maintain our company’s quality
management system certifications to ensure customer satisfaction. We employ the
aggregate system so that all employees anticipate problems and implement root
cause solutions using effective and standardized improvement methods. We believe
that quality is built-in, and not inspected in; and that when quality comes first,
reduced costs follow.

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Customers Are Our Focus
We establish successful customer partnerships by exceeding customer

expectations for products, services and attitude, while ensuring that our intellectual
property is protected as we exchange information and share knowledge. We start by
understanding our customer’s needs, earning our credibility by producing quality
products, delivering comprehensive total systems solutions and meeting
commitments. We believe each employee must effectively serve their internal
customers in order for Microchip’s external customers to be properly served.
Continuous Improvement Is Essential
We utilize the concept of “Vital Few” to establish our priorities. We concentrate

our resources on continuously improving Vital Few while empowering each
employee to make continuous improvements in their area of responsibility. We strive
for constructive and honest self-criticism to identify improvement opportunities.
Employees Are Our Greatest Strength
We design jobs and provide opportunities promoting employee teamwork,

productivity, creativity, pride in work, trust, integrity, fairness, involvement,
development and empowerment. We base recognition, advancement and
compensation on an employee’s achievement of excellence in company, team and
individual performance. We provide for employee health and welfare by offering
competitive and comprehensive employee benefits.
Products and Technology Are Our Foundation
We make ongoing investments and advancements in the design and

development of our manufacturing processes, device, circuit, system and software
technologies and services. We valueand protect intellectual properties that allow us to
develop timely, innovative, reliable and cost effective total system solutions that give

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our customers the freedom to innovate for today and tomorrow.
Total Cycle Times Are Optimized
We focus resources to optimize cycle times to our internal and external

customers by empowering employees to achieve efficient cycle times in their area of
responsibility. We believe that cycle time reduction is achieved by streamlining
processes through the systematic removal of barriers to productivity.
Safety Is Never Compromised
We place our concern for safety of our employees and community at the forefront
of our decisions, policies and actions. We are all individually and collectively
responsible for safety. Profits and Growth Provide For Everything We Do We strive
to generate and maintain industry leading rates of company profits and growth as they
allow continued investment in the future, enhanced employee opportunity, and
represent the overall success of Microchip.
Communication Is Vital
We encourage appropriate, honest, constructive and timely communication in

company, customer, investor, government and community relationships to resolve
issues, exchange information and share knowledge.
Suppliers, Representatives And Distributors Are Our Partners
We strive to maintain professional and mutually beneficial partnerships with

those suppliers, rep resentatives, distributors, design houses and consultants who are
an integral link in the achievement of our mission and guiding values.
Professional Ethics and Social Responsibility Are Practiced
We manage our business and treat customers, employees, shareholders,

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investors, suppliers, channel partners, community and government in a manner that

exemplifies our honesty, ethics and integrity. We honor our short- and long-term
fiscal, social and environmental responsibilities and are proud to serve as an equal
opportunity employer.
1.4 PRODUCTS OF MICROCHIP
We are a leading provider of smart, connected and secure embedded control

solutions that enable low-risk product development, lower total system cost and faster
time to market for thousands of diverse applications for the industrial, automotive,
consumer, aerospace and defense, communications and computing markets. Browse
these product categories or use one of our product selection tools to find the right
solutions for your next design.
Effortless Embedded Control Solutions
Effortlessly meet the ever-changing requirements of modern electronics with our

portfolio of scalable 8-bit, 16-bit and 32-bit microcontrollers (MCUs), Digital Signal
Controllers (DSCs) and microprocessors (MPUs). Our flexible peripherals and
functions make it easy to create differentiated applications that set you apart from
your competition. You’ll find it simple to get started by using our intuitive design
environments and visual configuration tools, while our proven reference designs and
professionally-tested software libraries lower your design risk.
Figure 2: Microchip Processor

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Smart Energy/Metering
To address the needs of the smart energy market, we offer a platform that
incorporates application- specific solutions as well as standard microcontroller,
microprocessor, security, memory, wireless and power-line connectivity devices. This
smart energy portfolio offers you best-in-class feature sets and performance for
designing equipment for the smart grid.
Amplifiers and Linear ICs
For the simplest to the most complex designs, our extensive portfolio of
amplifiers and comparators enables you to develop low-risk solutions with minimal
risk of a forced redesign. These devices are also backed by our client-driven
obsolescence practice of continuing to supply a product for as long as possible and
while demand for the product exists. We provide thorough documentation that
explains how and why these devices work, and you will find that their performance
on the bench matches the specifications in their data sheets. Design risk and
complexity are further mitigated with integrated features such as on-chip filters to
reduce electromagnetic interference, integrated references and hardware enable pins
that are available on select devices.
Figure 3 :Microchip MC608

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Clock and Timing Solutions with a Long and Proven Heritage
Whatever your complex timing requirements are, you can rely on our heritage of
supplying clock and timing products for more than half a century and our
comprehensive portfolio of technologies, services and solutions to help you build
more reliable systems. Our easily configurable quartz- or MEMS-based oscillators
and multiple-output clock generators support a broad array of low-jitter and low-
power applications. Our jitter attenuation products simplify design complexity by
integrating the oscillators and discrete PLLs required for jitter attenuation and
frequency conversion. We also offer the industry's broadest packet network
synchronization portfolio, including ITU- T/IEEE® standards-compliant Digital Phase
Locked Loops (DPLLs) for Synchronous Ethernet (SyncE) and IEEE 1588 based
applications. To round out our portfolio, our clock and data distribution products
include buffers, logic translators and multiplexers to provide you with a total solution
for your clock and timing requirements.
Data Converters
To meet the latest requirements for high-speed and low-power data conversion
performance in today’s applications, we offer a broad portfolio of proven and easy-to-
use solutions.
Figure 4: Data converter block diagram

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Field-Programmable Gate Arrays and Other Programmable Logic Devices
Meet your design requirements for low power consumption, reliability and
security with our broad portfolio of low- and mid-range density Field-Programmable
Gate Arrays (FPGAs). Use our FPGAs, System-on-Chip (SoC) FPGAs, and
radiation-tolerant FPGAs to satisfy the high- band- width connectivity and high-data
throughput needs across many applications including hybridand electric vehicles,
communications, Internet of Things (IoT) infrastructure, industrial controls and
automation, spacecraft, commercial aircraft and defense equipment. Robust DSP and
memory resources streamline development of hardware acceleration, Artificial
Intelligence (AI), image processing and edge computing designs.
Figure 5:FPGA
LED Drivers and Backlighting

Simplify the development of LED applications and get to market faster with our
complete portfolio of LED drivers, which can be combined with our microcontrollers
and power management, interface and connectivity products. These solutions help
you integrate LED technologies into complex and high-reliability applications such
as automotive safety systems. We can also simplify the design of other emerging
applications such as Human Centric Lighting (HCL) where LED technologies work
together as a system to mimic the cycle of natural lighting which can improve health
and productivity. We offer development tools and other design resources, along with

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specialized technical support to help you create exciting and innovative LED
applications.
Figure 6:LED Driver
Memory
The electronic systems we use today require some form of memory for data and
software storage. As a leading supplier of high-quality memory products, we offer a
broad portfolio of serial EEPROM, serial EERAM, parallel EEPROM, OTP EPROM,
serial Flash, parallel Flash, serial SRAM, NVSRAM, and Crypto Memory security ICs
to meet your memory needs. We also offer the industry’s first commercially available
serial memory controller for use in high-performance data center computing
applications. Our extensive testing protocols have ensured industry-leading
robustness and endurance along with best-in-class quality to provide you with reliable
products, dependable technical support and a consistent supply of devices throughout
your product’s lifecycle.
Figure 7:ROM
Sensors and Motor Drive

Are you building a system that needs to measure real-world data accurately and
reliably to make intelligent, real-time decisions? Our large portfolio of sensors
measure data from the analog world and deliver it to the digital world. These sensors
feature high-accuracy, low-power performance, real-time protection, robust interfaces

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and compact packages to satisfy the requirements of industrial, automotive,

consumer, data center and communications applications. Their high accuracy makes
them an excellent choice for high-precision applications, while their small packages
and low power consumption make them ideal for hand-held or battery-powered
devices. Explore our different types of sensors to find the most cost-effective and
space-saving option to suit your specific design requirements.
Figure 8: Microchip products
Wireless Connectivity
With the massive growth of the Internet of Things, wireless connectivity has
never been more important. Quickly incorporate connectivity into your designs with
wireless ICs, modules, software and development kits that make connecting
effortless for your customers. Our comprehensive wireless portfolio has the
technology to meet your range, data rate, interoperability, frequency and topology
needs.
Figure 9:MCU Module

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1.5 COMPANY DIVISION
Microchip Technology Bangalore is divided into various division based on the work
performed
 HR division.
 IT division.
 Analog division.
 Front end division.
 Physical design division
 CAD division.
1.6 Company major service
Microchip Technology receive the orders from various domestic and

international customers. The orders may the Manufacture of semiconductors,
modifications of chip parts and Repairs, Major Servicing and Supply of
microcontrollers and microprocessors.
1.7 Business partners
Our Security Design Partners offer key expertise using our security devices and
libraries. If you are developing a solution to secure an IoT application, consumable or
accessories, you can rely on our partners' competencies to reduce your time to market.
The companies listed below are trusted partners who have demonstrated their
knowledge and have been vetted as a genuine security expert on our technologies. If
reducing cost, time to market and increasing flexibility are your goals, try these
solutions.
Some of the partners are amazon web service, afero, agosto, cerberos, crosshill
,ecolux, dgms,exosite, golden bits,optimal design, medium one,panna etc.

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1.8 Organization Structure
Mr. Sanghi was named the Executive Chairman in March of 2021. He served as
Chief Executive Officer of Microchip since October 1991, and the Chairman of the
Board of Directors since Oc- tober 1993. Mr. Sanghi served as President from August
1990 to February 2016 and has servedas a director since August 1990. Before joining
the Company, Mr. Sanghi was Vice President of Operations at Waferscale
Integration, Inc., a semiconductor company, from 1988 to 1990. Mr.
Sanghi was employed by Intel Corporation from 1978 to 1988, where he held various
positions in management and engineering, the most recent serving as General
Manager of Programmable Memory Operations. Mr. Sanghi holds a Masters of
Science degree in Electrical and Computer Engineering from the University of

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Massachusetts and a Bachelor of Science degree in Electronics and Communication

from Punjab University, India.
 President and chief executive officer
Mr. Moorthy was promoted to Chief Executive Officer in March 2021. He was
appointed to Microchip's Board of Directors in January 2021. He served as the
President and COO of Microchip since February 2016. He served as Chief Operating
Officer since June 2009 and as Executive Vice President from October 2006 to May
2009. From November 2001 to October 2006 Mr. Moorthy served as Vice President
the Advanced Microcontroller and Automotive Division (AMAD). Mr. Moorthy
holds an M.B.A. in marketing from the National University, Sacramento, Calif.; a B.S.
degree in electrical engineering from the University of Washington, Seattle, Wash.;
and a B.S. degree in physics from the University of Bombay, Bombay, India.
Figure 10:Organaization structure
1.1 Roles and responsibilities

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1.9.1 Interns(physical design)
 To learn and understand the VLSI physical design flow.

 To improve the timing, power and area of the design.
 To learn about standard cells, placement and other aspects of VLSI.
 To get exposure to cadence tool.
1.9.2 Duties and Responsibilities of manager
 To supervise the working of whole team.

 To supervise the team progress in the project.
 To report to the higher manager.
 To bid for new projects.
 To take a look at team members attendance and leave allowance.
 To recruite new members to the team.
1.9.3 Duties and Responsibilities of HR
 To take care about the payroll of the employees

 To recruite the employees.
 Maintain employee records.
 Supporting health and wellness.
 Conduct benefit analysis.
 Conduct disciplinary action.
1.10 COMPANY ACHIVEMENTS
We are proud to have been recognized many times for our successes and
accomplishments. Microchip has received numerous awards for business and
technical excellence throughout the years. Here are some of the most recent ones:

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 Named one of The Best Employers for Diversity in 2021 by Forbes

 "Alfred P. Sloan" award for Business Excellence for 10 consecutive years as an
employer that has been successfully implementing workplace flexibility to meet both
business and employee goals.
 Training Magazine has continually named Microchip to its "Training Top 125" list.
This list recognizes organizations that successfully execute strong employee
development programs.
 Listed on SellingPower Magazine's "Top 50 Companies to Sell For" several times.
 Multiple "Best Place to Work" awards, such as:
o America's Best Employers – Forbes Magazine
o Best Places to Work – Phoenix Business Journal
o Top Workplaces List – Bay Area News
o Arizona's Most Admired Companies – Best Companies AZ
 Steve Sanghi, Microchip's former President and CEO, has been recognized multiple
times for outstanding leadership:
o Named to the Phoenix Business Journal's annual list of "Most Admired Leaders."
o Named by the Arizona Business Magazine as one of the "Most Influential Minority
Business Leaders" in Arizona.
o Named "Executive of the Year" – Annual Creativity in Electronics (ACE) Award
– EE Times.
 "Company of the Year" – ACE Award – EE Times.

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Chapter 2
ABOUT THE DEPARTMENT
2.1 ASIC FLOW
Today, ASIC design flow 6.46 is a very mature process in silicon turnkey design.
The ASIC design flow and its various steps in VLSI engineering that we describe
below are based on best practices and proven methodologies in ASIC chip designs.
This blog attempts to explain different steps in the ASIC design flow, starting from
ASIC design concept and moving from specifications to benefits.
Figure 11: ASIC FLOW

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2.1.1 PNR
Figure 12: PNR FLOW

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To ensure successful ASIC design, engineers must follow a proven ASIC design
flow which is based on a good understanding of ASIC specifications, requirements,
low power design and performance, with a focus on meeting the goal of right time to
market. Every stage of ASIC designcy- cle has EDA tools that can help to implement
ASIC design with ease.
Step 1. Chip Specification
This is the stage at which the engineer defines features, microarchitecture,

functionalities (hardware/software interface), specifications (Time, Area, Power,
Speed) with design guidelines of ASIC. Two different teams are involved at this
juncture:
Design team: Generates RTL code. Verification team: Generates test bench.
Step 2. Design Entry / Functional Verification
Functional verification6.47 confirms the functionality and logical behavior of the

circuit by simu- lationon a design entry level. This is the stage where the design team
and verification team come into the cycle where they generate RTL code using test-
benches. This is known as behavioral simulation.
In this simulation, once the RTL code (RTL code is a set of code that checks
whether the RTL implementation meets the design verification) is done in HDL, a lot
of code coverage metrics proposed for HDL. Engineers aim to verify correctness of
the code with the help of test vectors and trying to achieve it by 95% coverage test.
This code coverage includes statement coverage, ex- pression coverage, branch
coverage, and toggle coverage.

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There are two types of simulation tools:
Functional simulation tools: After the testbench and design code, functional
simulation verifies logical behavior and its implementation based on design entry.
Timing simulation tools: Verifies that circuit design meets the timing requirements
and confirms the design is free of circuit signal delays.
Step 3. RTL block synthesis / RTL Function
Figure 13:RTL FLOW
Once the RTL code and testbench are generated, the RTL team works on RTL
description – they translate the RTL code into a gate-level netlist using a logical
synthesis tool that meets required timing constraints. Thereafter, a synthesized
database of the ASIC design is created in the system. When timing constraints are met
with the logic synthesis, the design proceeds to the design for testability (DFT)
techniques.

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Step 4. Chip Partitioning
This is the stage 6.49 wherein the engineer follows the ASIC design layout
requirement and specification to create its structure using EDA tools and proven
methodologies. This design structure is going to be verified with the help of HLL
programming languages like C++ or SystemC.
After understanding the design specifications, the engineers partition the entire
ASIC into multiple functional blocks (hierarchical modules), while keeping in mind
ASIC’s best performance, technical feasibility, and resource allocation in terms of
area, power, cost and time. Once all the functional blocks are implemented in the
architectural document, the engineers need to brainstorm ASIC design partitioning by
reusing IPs from previous projects and procuring them from other parties.
Step 5. Design for Test (DFT) Insertion
With the ongoing trend of lower technology nodes, there is an increase in

system-on-chip variations like size, threshold voltage and wire resistance. Due to
these factors, new models and techniques are introduced to high-quality testing.
ASIC design is complex enough at different stages of the design cycle. Telling
the customers that the chips have fault when you are already at the production stage is
embarrassing and disruptive. It’s a situation that no engineering team wants to be in.
In order to overcome this situation, design for test is introduced with a list of
techniques:
Scan path insertion: A methodology of linking all registers elements into one long
shift register (scan path). This can help to check small parts of design instead of the
whole design in one go.
Memory BIST (built-in Self-Test): In the lower technology node, chip memory
requires lower area and fast access time. MBIST is a device which is used to check
RAMs. It is a comprehensive solution to memory testing errors and self-repair
proficiencies.

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ATPG (automatic test pattern generation): ATPG is a method of creating test

vectors / sequential input patterns to check the design for faults generated within
various elements of a circuit.
Inputs for PNR flow
1. NETLIST
2. SDC
3. LOGICAL LIBRARIES
4. PHYSICAL LIBRARIES
Step 6. Floor Planning (blueprint your chip)
After, DFT, the physical implementation process is to be followed. In physical

design, the first step in RTL-to-GDSII design is floorplanning. It is the process of
placing blocks in the chip. It includes: block placement, design portioning, pin
placement, and power optimization.
Floorplan determines the size of the chip, places the gates and connects them
with wires. While connecting, engineers take care of wire length, and functionality
which will ensure signals will not interfere with nearby elements. In the end, simulate
the final floor plan with post-layout verification process.
A good floorplanning exercise should come across and take care of the below
points; otherwise, the life of IC and its cost will blow out:
*Minimize the total chip area
*Make routing phase easy (routable)
STEPS

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*Decide core width and height for die size estimation.
*IO pad sites are created for placement of IO pad placement.
*Placement of macros.
*The standard cell rows created for standard cell placement.
*Power planning (pre routing)
*Adding physical only cells.
Floorplan control parameter:
Aspect ratio: Aspect ratio will decide the size and shape of the chip. It is the ratio
between hori- zontal routing resources to vertical routing resources (or) ratio of
height and width. Aspect ratio
= width/height
Core utilization:- Utilization will define the area occupied by the standard cells,
macros, and other cells. If core utilization is 0.8 (80%) that means 80% of the core
area is used for placing the standard cells, macros, and other cells, and the remaining
20% is used for routing purposes.
core utilization = (macros area + std cell area +pads area)/ total core area
Macro placement:
Macros may be memories, analog blocks. Proper placement of macros has a

great impact on the quality and performance of the ASIC design. Macro placement
can be manual or automatic.
Manual macro placement is more efficient when there are few macros to be
placed. Manual macro placement is done based on the connectivity information of
macros to IO pin/pads and macro to macro. Automatic macro placement is more
appropriate if the number of macros is large.
Types of macros:

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Hard macros: The circuit is fixed. We can’t see the functionality information about
macros. Only we know the timing information.
Soft macros: The circuit is not fixed and we can see the functionality and which type
of gates are using inside it. Also we know the timing information.
Types of floorplan techniques:
Abutted:- When the chip is divided into blocks in the abutted design there is no gap
between the blocks.
Non abutted:- In this design there is a gap between blocks. The connection between
the blocks is done through the routing nets.
The mix of both: This design is a combination of abutted and non- abutted
Outputs of floorplan:
1. Get core and boundary area
2. ports/pins placed
3. IO Macros placement done
4. Floorplan def file
Step 7. Placement
This step has three parts
 pre-placement
 placement
 post-placement(MBR)
Pre-placement
This step is also know as the latch-up condition and should never occur in the
design .It is creation of a low impedence path between vdd and vss which might
cause breakdown and hence should be avoided.

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Figure 14:Latch up
Placement
Placement is the process of placing standard cells in row. A poor placement

requires larger area and also degrades performance. Various factors, like the timing
requirement, the net lengths and hence the connections of cells, power dissipation
should be taken care. It removes timing violation.
Post-placement
Step wherein 2 or more cells in nearby area are combined to form a single cell to
reduce overhaul area and improve the timing.
Ex:4 1-bit register is combined to form 1 4-bit register.

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Step 8. Clock tree synthesis
Clock tree synthesis is a process of building the clock tree and meeting the
defined timing, area and power requirements. It helps in providing the clock
connection to the clock pin of a sequential element in the required time and area, with
low power consumption.
In order to avoid high power consumption, increase in delays and a huge number
of transitions, certain structures can be used for optimizing CTS structure such as
Mesh Structure, H-Tree Structure, X-Tree Structure, Fishbone Structure and Hybrid
structure.
With the help of these structures, each flop in the clock tree gets the clock
connection. During the optimization, tools insert the buffer to build the CTS structure.
Different clock structures will build the clock tree with a minimum buffer insertion
and lower power consumption of chips.
Step 9. Routing
Global Routing: Calculates estimated values for each net by the delays of fan-out of
wire. Global routing is mainly divided into line routingand maze routing.
Detailed Routing: In detailed routing, the actual delays of wire is calculated by

various optimization methods like timing optimization, clock tree synthesis, etc.
As we are moving towards a lower technology node, engineers face complex

design challenges with the need for implanting millions of gates in a small area. In
order to make this ASIC design routable, placement density range needs to be
followed for better QoR. Placement density analysis is an important parameter to get
better outcomes with less number of iterations.

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Step 10. Final Verification (Physical Verification and Timing)
After routing, ASIC design layout undergoes three steps of physical verification,
known as signoff checks. This stage helps to check whether the layout working the
way it was designed to. The following checks are followed to avoid any errors just
before the tapeout:
Layout versus schematic(LVS) is a process of checking that the geometry/layout

matches the schematic/netlist.
Design rule checks(DRC)6.411 is the process of checking that the geometry in the
GDS file follows the rules given by the foundry.
Logical equivalence checks(LVC) is the process of equivalence check between

pre and post design layout.
In the last stage of the tape out, the engineer performs wafer processing,
packaging, testing, verification and delivery to the physical IC. GDSII is the file
produced and used by the semiconductor foundries to fabricate the silicon and
handled to client.
Infochips has contributed to over 500 product designs for top global companies,
with more than 40 million deployed around the world. As a leading ASIC design and
verification service provider, Infochips has brought together IP cores, verification IP
and design and verification expertise

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Chapter 3:
TASKS PERFORMED
3.1 Sanity Checks
The main intention of sanity checks in Physical Design is that they are mainly
done for checking the design for further acceptance at each stages of the physical
implementation
Following are the sanity checks carried out in physical design:
Figure 15:Types of sanity checks

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check_library: It performs consistency checks between logical and physical libraries.

That means each cells that are described in the netlist has its corresponding physical,
timing and logical information dened in the libraries.
check_timing: PNR tool won't optimize the paths which are not constrained. So we
have to check any unconstrained paths are exist in the design. The check_timing
command will report the unconstrained paths. If there are any unconstrained paths in
the design, run the report_timing command to verify whether the unconstrained
paths are false paths.
check_design: This check is to report problems like undriven input ports, unloaded
output ports, nets/ports with multiple drivers, unloaded nets, pins mismatch, cells or
instances with out I/O pins/ports etc.
report_timing: The report_timing command provides a report of timing information

for the current design. By default, the report_timing command reports the single
worst setup path in each clock group.
report_qor : It reports the statistics/QoR of the current design includes its timing
information, cell count, details like combinational and sequential cells, total area of
the current design. This will also reports any DRV s present.
report_constraint: It reports the following parameters in the current design such as

WNS, total negative slacks etc. The report includes whether the constraints are
violated or not, by how much it is violated and the worst violating object.
3.2 Netlist check: check_design -netlist
This check which verifies correctness of the netlist.
1. Input pin of a net should not be floating .It may lead to power issues or IR drop in
later stages.
2. There should not be any direct connection to Vdd and Vss. It may lead to circuit

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burns.
3. Multi-driven nets are not allowed in the netlist.
4. No combinational loops should be there, it may lead to meta stable state.
5. There should not be any assign statement.
3.3 Timing check: check_timing

Includes few checks which verifies correctness of SDC. Timing Constraints
present inside SDC are given by the synthesis team and check_timing command
verifies following:
 Unconstrained end points

 Missing input output delays
 Missing clock definitions
 Multi Clock Driven registers
3.3.1 Unconstrained end points
If timing paths are unconstrained, the check_timing command only reports the
unconstrained endpoints, not the unconstrained start points.
Similarly, for paths constrained only by set_max_delay, set_min_delay, or both

rather than set_input_delay and set_output_delay, the check_timing command only
reports any unconstrained endpoints, not unconstrained start points.
To check for unconstrained endpoints use: report_timing -exceptions.

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Missing input output delays and Missing clock definitions
Specifies a timing delay from one group of points to another

(maybe clock signal ). Define the timing arrival at Input port when
clock comes . set_output_delay: signal must arrive at least the specified
amount of time that define by command "set_output_delay" .
3.3.2 MultiClockDriven registers:
Where same flop get driven by more than a single clock which is
logically incorrect. In such cases tool wont be able to decide the correct clock
port and may lead to more than single launchand capture edges for the data.
Which can further lead to setup and hold violations.
3.4 Library check
This check verifies, whether physical libraries are consistent with logical
libraries or not. For any missing libraries check_library command will show
black boxes and timing calculation will not be proper.
3.5 Blockages
Blockages are specified locations where placing cells are prevented or

blocked. These act as guidelines for placing standard cell* in the design.
Blockages will not be guiding the placement tool to place standard cell at
some particular area, but it won't allow placement tool to place standard cell
at specified locations. This way blockages are act as guidelines to placement
tool.
Standard cell: A standard cell is a group of transistors and interconnects

structures that provides a boolean logic function (e.g. AND, OR, XOR,
XNOR, NOT) or a storage function (flipflops or latch).

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Types of blockages describes as below,
3.5.1 Soft (Non-buffer) blockage:
Soft blockage specifies a region where only buffer can be placed. That
means standard cells cannot be placed in this region. It blocks(prevents) the
placement tool from placing non-buffercells such as std. cell in this region.
3.5.2 Hard blockage:
Hard blockage specifies a region where all standard cells and

buffers cannot be placed. It prevents the placement tool from placing
standard cells and buffers in this region.
Hard blockage are mostly used to
 Block standard cells to certain regions in the design,

 Avoid routing congestion at macro conners,
 Control power rail generations at macro cores.
3.5.3 Partial blockage:
The blockage factor for any blockage is 100% by default. So no

cells can be placed in that region, but the flexibility of blockages can be
chosen by partial blockages.
Placement blockage:
Placement blockage prevent the placement tool from placing cells at

specified regions. Placement blockages are created at floor planning
stage.
Placement blockage are used to
 Define standard cells and macro* area,

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 Reserve channels for buffer insertion,

 Prevent cells from being placed nearer to macros,
 Prevent congestion near macros.
Macros: Macros are intellectual properties that can be directly used in the
design. These are need not to be design. For example memories, processor
core, PLL etc.
3.5.4 Routing blockage:
Routing blockages block routing resources on one or more layers. It

can be created at any point in the design.
Halo (keep-out-region):
Halo is the region around the boundary of fixed macro in the design in
which no other macro or standard cells can be placed. Halo allows placement
of buffers and inverters in its area
Halos of two adjacent macros can be overlap.
If macro are moved from one place to another place, halos will also be
moved. But in case of blockages if the macros are moved from one place
to another place the blockages .
3.6 GUIDE FENCE REGION
• Guide - The module is preplaced in the core design area. A module guide
represents the logical module structure of the netlist. The purpose of a
module guide is to guide placement to place the cells of the module in the
vicinity of the guide's location. The preplaced guide is a soft constraint.
After the design is imported, but before floorplanning, you can locate
module guides on the left side of the core area, which appear as pink
objects (by default) in the Floorplan view.
• Fence - The module is a hard constraint in the core design area. After

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specifying a hierarchical instance as a partition, the constraint type status

of a module guide is automatically changed to a fence. Instances
belonging to a module of type fence must be placed inside the fence
boundary.
• Region - This constraint is the same as a fence constraint except that

instances from other modules can be placed within its physical outline by
placement.
• Soft Guide - This constraint is similar to a guide constraint except there

are no fixed locations. This provides stronger grouping for the instances
under the same soft guide. The soft guide constraint is not as restrictive as
a fence or a region constraint, so some instances might be placed further
away if they have connections to other modules.
3.7 Special cells required for Multi-Voltage Design
As discussed in the previous session, Special cells6.411 are required for

implementing a Mul ti-Voltage design. Today lets discuss about these cells in brief.
(1) Level Shifter

(2) Isolation Cell
(3) Enable Level Shifter
(4) Retention Flops
(5) AON cells
(6) Power Gating Switches/MTCMOS switch
Level Shifter: Purpose of this cell is to shift the voltage from low to high as well as
high to low. Generally buffer type and Latch type level shifters are available. In
general H2L LS’s are very simple, L2H LS’s are little complex and are in general
larger in size(double height) and have 2 power pins. There are some placement

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restrictions for L2H level shifter to handle noise levels in the design. Level shifters
are typically used to convert signal levels and protect against sneak leakage paths.
With great care, level shifters can be avoided in some cases, but this will become less
practicable on a wider scale.
Isolation Cell: These are special cells required at the interface between blocks which
are shut-down and always on. They clamp the output node to a known voltage. These
cells needs to
be placed in an ‘always on’ region only and the enable signal of the isolation cell
needs to be‘al- ways_on’. In a nut-shell, an isolation cell is necessary to isolate
floating inputs.
There are 2 types of isolation cells (a) Retain “0” (b) Retain “1”
Enable Level Shifter: This cell is a combination of a Level Shifter and a Isolation
cell.
Retention Flops: These cells are special flops with multiple power supply. They
are typically used as a shadow register to retain its value even if the block in which its
residing is shut-down. All the paths leading to this register need to be ‘always_on’
and hence special care must be taken to synthesize/place/route them. In a nut-shell,
“When design blocks are switched off for sleep mode, data in all flip-flops contained
within the block will be lost. If the designer desires to retain state, retention flip-flops
must be used”.
The retention flop has the same structure as a standard master-slave flop.
However, the retention flop has a balloon latch that is connected to true-Vdd. With
the proper series of control signals before sleep, the data in the flop can be written
into the balloon latch. Similarly, when the block comes out of sleep, the data can be
written back into the flip-flop.

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AON cells: Generally these are buffers, that remain always powered irrespective of
where they are placed. They can be either special cells or regular buffers. If special
cells are used, they have thier own secondary power supply and hence can be placed
any where in the design. Using regular buffers as AON cells restricts the placement of
these cells in a specific region.

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Chapter 4:
PHASE 1 AND 2 OF THE WORK AND OBSERVATION

4.1 FINFET
A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal-

oxide- sem- iconductor field-effect transistor) built on a substrate where the gate is
placed on two, three, or four sides of the channel or wrapped around the channel,
forming a double gate structure. These devices have been given the generic name
"FinFETs" because the source/drain region forms fins on the silicon surface. The
FinFET devices have significantly faster switching times and higher current
density than planar CMOS (complementary metal-oxide-semiconductor) technol-
ogy.
FinFET is a type of non-planar transistor, or "3D" transistor.[1] It is the

basis for modern nanoelectronic semiconductor device fabrication. Microchips
utilizing FinFET gates first became commercialized in the first half of the 2010s,
and became the dominant gate design at 14 nm, 10 nm and 7 nm process nodes.
It is common for a single FinFET transistor to contain several fins, arranged

side-by-side and all covered by the same gate, that act electrically as one, to increase
drive strength and performance.

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Figure 16:FINFET
4.1.1 Working principle
The working principle of a FinFet is similar to that of a conventional MOSFET.

The MOSFET can function in two modes: enhancement mode and deflection mode
for both p-channel and n- channel MOSFETs.
The channel shows maximum conductance when there is no voltage on the gate
terminal. As the voltage changes to positive or negative, the conductivity of the
channel reduces.
Figure 17:Diagram Depicting Working Principle of FINFET Based on MOORE’S

LAW
In enhancement mode of MOSFET, when there is no voltage on the gate

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terminal, it does not conduct. Unlike the depletion mode, in enhancement mode, the
device conducts better when there is more voltage on the gate terminal.
The main aim of the MOSFET is to control the flow of voltage and current
between the source and drain terminals. A high quality capacitor is formed by the
gate terminal. The gate is composed of the silicon oxide layer, the p-body silicon and
gate metallization and the p-body silicon. This capacitor is the most vital part. The
semiconductor surface at the below oxide layer which is located between source and
drain terminal. This is inverted from p-type to n-type by applying a positive or
negative gate voltage respectively.
When a small amount of voltage is applied to this structure (the capacitor),

keeping gate terminal positive with respect to source, a depletion region is formed.
This depletion region is formed at the interface between the silicon and the SiO2.
The positive voltage applied attracts electrons from the source terminal, the drain
terminal as well as the n+ source. This forms the electron reach channel. If we apply
voltage between the source and drain terminals, current will flow between source and
drain terminals. The concentration of electrons is controlled by the gate voltage (Vg).
Figure 18:FINFET Structure

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4.1.2 CONSTRUCTION OF FINFET

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Figure 19:Construction of FD-SOI FINFET
Figure 20: Image Showing Construction of Silicon-Based Bulk FINFET

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4.1.3 Silicon based FinFet
The important characteristics of this FinFet is that the conducting channel is

wrapped by a thin Si fin. This forms the body of the device. The fins are the 3D
channel between the source and the drain terminals.they are built on top if silicon (Si)
substrate. The gate terminal is wrapped around the channel. This allows formation of
several gate electrodes so as to reduce leakage current and enhance the drive current.
1. Substrate:
The base of a FinFET is a lightly p-doped substrate with a hard mask on top. It also
has a patterned resist layer.
2. Fin etch:
The fins are formed in a highly anisotropic etch process.Absence of a stop layer
forces the etch process to be time based. This layer is present in the SOI models.
Figure 21:Hard mask
3. Oxide deposition: An oxide deposition with a high aspect ratio filling behaviour is
needed so as to separate the fins from one another.

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4. Planarization: The oxide is planarized by chemical mechanical polishing. In this,

the hard mask acts as a stop layer.
5. Recess etch: this process is needed so as to recess the oxide film to form a lateral
isolation of the fins.
6. Gate oxide: On top of the fins the gate oxide is deposited via thermal oxidation to
isolate the channel from the gate electrode. Since the fins are still connected
underneath the oxide, a high- dose angled implant at the base of the fin creates a
dopant junction and completes the isolation.
7. Deposition of the gate: Finally a highly n+-doped poly silicon layer is deposited
on top of the fins. This leads to wrapping of three gates around the channel: one on
each side of the fin, and a third gate above. The third gate is wrapped depending on
the thickness of the gate oxide which is on top.
Figure 22:2-D View of Layers of FINFET
The influence of the top gate can also be inhibited by the deposition of a nitride
layer on top of the channel.

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Due to the presence of an oxide layer on an SOI wafer, the channels are isolated
from each other anyway. Along with this, the etch process of the fins is simplified.
This is done because the process can be easily stopped on the oxide.
Figure 23:3-D View of Layers of FINFET
4.2 APPLICATIONS OF FINFET
World leader in smartphones, Samsung Electronics has incorporated FinFet in its

14nm processors (Exynos7 Octra). This processor is used in the latest Samsung
smartphone, the Samsung Galaxy S6. They teamed up with Globalfoundries for this
project.
Along with Samsung, Apple, Intel and TSMC are set to ship the 14nm
technology by 2016. This technology will benefit all smartphones as it will speed up
the phone. This technology has surpased the previous technologies by overcoming
scaling and performance limitations faced while using the 20nm technology.

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4.3 FUTURE SCOPE
Future scope of FinFet include further scaling down to 10nm. The optimization
of the transistor fin will play a crucial role in this development. Further research is
being conducted to scale down the FinFet so as to improve efficiency. It is worth
mentioning that 14nm size is equivalent to the size of a virus. We have definitely
come a long way in terms of scaling down a transistor. So the next time you complain
about the price of the iphone or the new Samsung smartphone, remember that the
technology it uses will not be found in most other phones!

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CHAPTER 5:
PHASE 3 AND 4 OF THE WORK AND OBSERVATION
5.1 STA (STATIC TIMING ANALYSIS)
static timing analysis6.46, a method of checking the ability of the design to meet
the timing requirements statically without simulation
Static timing analysis (STA) is a method of validating the timing performance of

a design by checking all possible paths for timing violations.
5.1.1 Four categories of timing paths
• Register to Register (reg2reg)
• Register to Output (reg2out)
• Input to Register (in2reg)
• Input to Output (in2out)
5.2 Arrival and required time
• The arrival time represents the time at which the data arrives at the input of the
receiving sequentialele- ment. A.T=tcq+tcombo
• The required time is the time within which data is required to arrive at some
internal node of the design. Designer specify this value by setting
constraints.R.T=Tclk-tsetup.

BIT
Figure 24: Arrival time
5.3 Skew
• Skew is the difference in arrival of clock at two consecutive pins of a sequential

element is called skew
5.3.1 Positive Skew
If capture clock comes late than launch clock then it is called +ve skew. Clock
and data both travel in same direction.
 +ve skew can lead to hold violation.
 +ve skew improves setup time.
5.3.2 Negative Skew
If capture clock comes early than launch clock it is called –ve skew. Clock and
data travel in opposite direction.
 -ve skew can lead to setup violation.

BIT
 -ve skew improves hold time.
5.4 Slack
Slack is defined as difference between actual or achieved time and the desired
time for a timing path. For timing path slack determines if the design is working at
the specified speed or frequency.
Figure 25: Setup and hold slack
Data Arrival Time
This is the time required for data to travel through data path.
Data Required Time
This is the time taken for the clock to traverse through clock path.Setup and hold
slack is defined as the difference between data required time and data arrival time.

BIT
setup slack= Data Required Time- Data Arrival Time
Hold slack= Data Arrival Time- Data Required Time
A +ve setup slack means design is working at the specified frequency and it has
some more margin as well.
Zero setup slack specifies design is exactly working at the specified frequency
and there is no margin available.
Negative setup slack implies that design doesn’t achieve the constrained
frequency and timing. This is called as setup violation.
5.5 Reg to Reg path
Data arrival time is the time required for data to propagate through source flip
flop, travel through combinational logic and routing and arrive at the destination flip-
flop before the next clock edge occurs.
Figure 26: Reg to reg path
setup slack= Required Time- Arrival Time

=( Tclock-Tsetup) – (Tclk-q+Tcombo)
5.5.1 Reg to Output:

BIT
Data arrival time is the time required for data to leave source flip-flop, travel
through combinational logic and interconnects and leave the chip through output
port.
Figure 27:Reg to out

BIT
5.5 Input to reg
Figure 28:in to reg
5.6 Setup and hold time
Every flip-flop has restrictive time regions around the active clock edge in
which input should not change. We call them restrictive because any change in the
input in this regions the output may be the expected one (*see below). It may be
derived from either the old input, the new input, or even in between the two. Here we
define, two very important terms in the digital
clocking. Setup and Hold time.
The setup time is the interval before the clock where the data must be held
stable.
The hold time is the interval after the clock where the data must be held stable.
Hold time can be negative, which means the data can change slightly before the clock

BIT
edge and still be properly captured. Most of the current day flip-flops has zero or
negative hold time.
Figure 29:Setup
In the above figure, the shaded region is the restricted region. The shaded region
is divided into two parts by the dashed line. The left hand side part of shaded region
is the setup time period and the right hand side part is the hold time period. If the data
changes in this region, as shown the figure. The output may, follow the input, or
many not follow the input, or may go to metastable state (where output cannot be
recognized as either logic low or logic high, the entire process is known as
metastability).
Figure 30:Hold
The above figure shows the restricted region (shaded region) for a flip-flop

BIT
whose hold time is negative. The following diagram illustrates the restricted region of
a
D flip-flop. D is the input, Q is the output, and clock is the clock signal. If D changes
in the restricted region, the flip- flop may not behave as expected, means Q is
unpredictable.
Figure 31: setup violation
5.7 Propagation delay
Propagation delay6.49, symbolized tpd, is the time required for a digital signal to
travel from th einput(s) of a logic gate to the output. It is measured in microseconds
(µs), nanoseconds (ns),or picoseconds (ps), where 1 µs = 10-6 s, 1 ns = 10-9 s, and 1
ps = 10-12 s.
The propagation delay for an integrated circuit (IC) logic gate may differ for
each of the inputs. If all other factors are held constant, the average propagation delay

BIT
in a logic gate IC increases as the complexity of the internal circuitry increases. Some
IC technologies have interently longer tpd values than others, and are considered
"slower." Propagation delay is important because it has a direct effect on the speed at
which a digital device, such as a computer, can operate. This is true of memory chips
as well as microprocessors.
Figure 32: Propagation delay

BIT
CHAPTER 6
REFLECTION NOTES
I am thankful to having the opportunity to work with microchip because I

discovered a program that I would like to work with and at the same time gained
fabulous ideas to develop projects on embedded system. The time I spent at
microchip as an intern was a memorable one for me as it was rich in experience
sharing and helped me discover my potential. I had so many experiences and
opportunities that I personally believe will forever shape and influence my
professional life while fostering personal growth and development. To enhance my
knowledge and skills, microchip gave me the opportunity to intern with their project
for a period of 4 weeks. It has been a great pleasure working and getting qualified
with colorful grades from the microchip company it has provided with me a great
opportunity to learn leadership skills.
6.1 INTERNSHIP OUTCOMES

Internship outcomes are:
This internship has taught me how to deal with sudden changes in my workload and
has improved my team-working skills.
I have learned how to work independently and be responsible in a professional
setting, I had to keep myself accountable in order to get the job done.
This internship has taught me how to deal with sudden changes in my workload and
has improved my team-working skills.

BIT
6.2 NON-TECHNICAL OUTCOMES:

The non-technical outcomes that an internship will teach are:
Exercising Leadership
Behaving Professionally. Behaving ethically.
Listening effectively
Addressing colleagues and superiors appropriately.
6.3 CONCLUSION
Training can be initiated to address a "performance gap" (learning needed to

meet performance standards for a current task or job), "growth gap" (learning needed
to achieve career goals) or "opportunity gap" (learning needed to qualify for an
identified new job or role).
Majority of the employees feel happy and are willing to spend the rest of their
carrier with the organization. Along with this, the employees also feel the
organization’s problem as their ownand adhering to the organization is not the
consequence of any obligation to them. Further, the employees feel that training
programs establish a clear view of work roles and increase their performance level.
Also the training program provide knowledge sharing demonstrated in the organ-
ization. Also, the training programs are practical and employees were able to apply
the training techniques in their work.
Keeping in view the organizational requirement and goals and objectives of

training, the following have been identified as the key focus areas of training:
I am grateful to have been able to get the opportunity to pursue my industrial

training at microchip technology. I had a good learning experience at microchip. I
was introduced some state of technologies that are used to PNR flow.

BIT
6.4 REFERENCE
1. www.microchip.com
2. https://en.wikipedia.org/wiki/Microchip_Technology
3. https://www.microchipdirect.com
4. https://www.theofficialboard.com
5. https://theorg.com/org/microchip-technology
6. https://www.teamvlsi.com
7. https://www.vlsiguide.com
8. https://www.physicaldesign4u.com
9. http://ivlsi.com
10. https://www.synopsys.com
11. http://www.vlsi-expert.com
12. https://www.vlsisystemdesign.com

BIT
CO, PO AND PSO JUSTIFICATION

PO1: Engineering Knowledge
Applied the knowledge Electronics to know the basics of VLSI and physical design.
PO2: Problem Analysis

Factors such as different version of P.D.
PO4: Conduct investigation of complex problem
Did conduct investigation of problems to improve timing and reduce area and power
in design.
PO5: Modern Tool Usage

Used cadence and other modern tools.
PO6: The Engineer and Society

Learnt that the use of cadence to improvise the physical design.
PO8: Ethics
Applied ethical and professional principles at work.
PO9: Individual and Teamwork-

Worked individually for the overhaul of different instruments andsen- sors and
also in the team.
PO10: Communication
Completed the report and provided presentation on the overhaul and understanding of
differentengine structures under the instructions of the internal guide.
PO12: Life-long learning
Learnt to be independent.

BIT

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VISVESVARAYA TECHNOLOGICAL UNIVERSITY

Jnana Sangama , Belagavi ,Karnataka_590014

“VLSI PHYSICAL DESIGN FLOW”

Internship Carried Out at

Internal Guide External Guide

DEPARTMENT OF ELECTRONICS & COMMUNICATION

K.R. Road, V. V Puram, Bengaluru -560004

Department of Electronics and Communication Engineering.

MRS.VIDYASARASWATHI H.N DR. K V PRASAD

With profound sense of gratitude, I acknowledge the guidance and support

I would like to thank Dr. A.R HEMANTH KUMAR, professor and

I express my sincere regards and thanks To Dr. K V PRASAD, Professor and

Bangalore, who have encouraged me throughout the course of bachelor degree.

Microchip Technology is one of the pioneering company in the production of

CHAPTER 2: ABOUT THE DEPARTMENT 19-29

CHAPTER 3: TASKS PERFORMED 30-37

Chapter 4: PHASE 1 AND 2 OF THE WORK AND 37-45

Chapter 5: PHASE 3 AND 4 OF THE WORK AND 46-54

CHAPTER 6: REFLECTION NOTES 55-57

6.1 Internship outcome 55

Figure 2: Microchip Processor.....................................................................................23

Figure 3 :Microchip MC608.......................................................................................24

Figure 4: Data converter block diagram......................................................................25

Figure 6:LED Driver....................................................................................................27

Figure 8: Microchip products......................................................................................28

Figure 9:MCU Module................................................................................................28

Figure 10:Organaization structure...............................................................................32

Figure 11:ASIC FLOW...............................................................................................35

Figure 12:PNR FLOW.................................................................................................36

Figure 13:RTL FLOW.................................................................................................38

Figure 14:Latch up.......................................................................................................43

Figure 15:Types of sanity checks................................................................................46

Figure 17:Diagram Depicting Working Principle ofFINFET………. ………… 56

Figure 18:FINFET Structure........................................................................................57

Figure 19:Construction of FD-SOI FINFET...............................................................58

Figure 20: Image Showing Construction of Silicon-Based Bulk FINFET..................58

Figure 21:Hard mask...................................................................................................59

Figure 22:2-D View of Layers of FINFET..................................................................60

Figure 23:3-D View of Layers of FINFET..................................................................61

Figure 25: Setup and hold slack...................................................................................65

Figure 26: Reg to reg path...........................................................................................66

Figure 27:Reg to out....................................................................................................67

Figure 28:in to reg.......................................................................................................68

Figure 31: setup violation............................................................................................70

Figure 32: Propagation delay.......................................................................................71

BANGALORE INSTITUTE OF TECHNOLOGY

• Provide high quality education in the engineering disciplines from the

LONG TERM GOALS

• To be among top 3 private engineering colleges in Karnataka and top 20 in India.

• To be the most preferred choice of students and faculty.

• To be the preferred partner of corporate.

Imparting Quality Education to achieve Academic Excellence in Elec tronics and

• Create state of art infrastructure for quality education.

• Delivering Professional Engineers to meet the societal needs.

PROGRAM EDUCATIONAL OBJECTIVES

• Prepare graduates to be professionals, Practicing engineers and entrepreneurs in the

• To acquire sufficient knowledge base for innovative techniques in design and

• Capable of competing globally in multidisciplinary field.

• Graduates will maintain and improve technical competence through continuous

PROGRAM SPECIFIC OUTCOMES

COURSE OUTCOMES OF 17EC84

After going through the internship the student is able to:

CO1: Apply engineering and management principles.