Department of Electrical Engineering

EGEE-465 Fall 2020

Introduction to VLSI Design (Fall 2020)

Differential Amplifier
Design

Student Name: __Jeffry Salazar

Student CWID: __891884140__

Instructor: Yitsen Ku Ph.D.

December 16, 2020

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I. Introduction

Differential Amplifier with Active Load is an operational amplifier that takes the difference of two
voltages to get the maximum gain out of a single output. It is an improvement on the amplifier shown in ‘Figure
1’. The differential amplifier with resistors (Figure 1) requires two outputs to get the full gain. The amplifier
being used in this project has PMOS transistors (Q3=M3, Q4 = M4) instead of resistors. The transistors Q3 and
Q4 replace R1 and R2. The resistors create small signal and large signal variations, where the large signal
variations are removed by the transistors, which affects current biasing. Voltage drop from the resistors is not an
issue with 15V Vdd, but with 2.5V or 3.3V, biasing problems occur, therefore active loads are needed.
Therefore, using a current-mirror instead of drain resistors, improves biasing. The bias voltage is influenced by
the current-mirror transistors width-to-length ratio(W/L). Larger W/L will create a larger drain current (Id), with
equation shown in Figure 4. Open loop gain is determined by the drain current, which comes from the
transistor’s (gm) in the current-mirror, and the Q2 and Q4 transistors’ resistance (ro), where the calculation is
shown in Figure 7.

Figure 1:Common amplifier Figure 2: Differential Amplifier with Active Load & symbol

Figure 3: Shows the current path of the current mirror created by Q3 and Q4.
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Figure 4: Biasing improvement with current-mirror. Figure 5: Schematic depicting drain current in amp.

Figure 6: Differential amp Figure 7: Intuitive schematic showing how Open Loop Gain is

showing small signal calculated.

resistance from Q3 and Q4.

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II. Circuit Description
A. Differential Amplifier with Active Load
Both Figures 7 & 8, show the final design of the differential amp Schematic in S-Edit. The amplifier is created
using two PMOS transistors on the top to create a current mirror and three NMOS transistors, one for current
biasing and two for inputs driving the amplifier. Simulation is performed with an AC signal to simulate Gain in
decibels and phase in degrees relative to frequency.
Differential Amplifier Schematic

Figure 8: Differential Amplifier Schematic in S-Edit

For the simulation (Figure 8) Vdd = 2.5V, Vin+ = 1.25Vdc, Vin- = 1.25Vac, and Vbias = 480mV.

Differential Amplifier Simulation Schematic

Figure 9: Differential Amplifier simulation schematic in S-Edit

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Figure 9, shows the Differential Amplifier symbol which puts the two PMOS transistors and three NMOS
transistors in the box. There is constant voltage input (Vdd ) and ground (Gnd). Input signals are Vin+ and Vin-,
with output signal Vout.

Differential Amplifier Symbol

Figure 10: Differential Amplifier symbol in S-Edit

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B. Spice Code

Final Design Differential Amplifier Spice Code

Figure 11: Differential Amplifier spice code in T-Spice

The spice code shows the sub circuits for the specifications for the five transistors. The ‘Top Level’ section has
the differential amp (XmyOp_1) symbol being used for simulation. Right below has the functions for the
constant voltages, voltage sinusoid and plotting. The Simulation settings are AC, 10Hz sampling for a range of
10n Hz to 100G Hz.

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C. IC Layout

Differential Amplifier Layout with Measurements

Figure 12: Differential Amplifier layout in L-Edit

The Differential Amplifier layout consist of two PMOS transistors and three NMOS transistors. The green
outlined area has the PMOS transistors and the red outlined area has the NMOS transistors. The layout shows
the proper size based on the specifications made to the transistors. The main concern in the analog design is
noise issues like crosstalk, but most design requirements were satisfied based on the table to the right.
Application of design considerations were used to remove 90 deg corners on the poly circuit. Chip area is
measured on the layout, which is (12.35um x 12.96 um).

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III. Simulation Results
A. Simulation & Hspice
The spice code shown below shows the initial specifications used for most of the simulations, except the final
design. The spice code for the final design is shown in the ‘Circuit Design’ section above. The initial values are
Vbias = 600mV, all transistors have W = 1.5um. The values listed are the only variables in the simulations, the
rest are left constant. The Hspice simulation results are given next to the T-Spice simulation results. The T-Spice
simulation results give the voltage output gain in decibels and voltage output phase for the amplifier. The
Hspice result shows the power consumption of the amplifier design, and each transistor mode.

Test Specifications for simulation.

Figure 13: Differential Amplifier spice code in T-Spice for initial specifications of simulations

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 Simulation 1: Initial Specifications: Vbias = 600mV, W= 1.5um(All transistors)

Figure 14: T-spice for simulation 1 results.

Figure 15: Hspice for simulation 1 results.

The amplifier has initial specification: Vbias = 600mV and all W=1.5um. Figure 13 displays T-Spice results:
Open Loop Gain(Max Gain) = 6.2dB, Bandwidth = 125MHz, Unity Gain Frequency = 251MHz, and phase
margin of 67 degrees. Figure 14 displays Hspice results showing all transistors are in Saturation mode and
power consumption is 42.4167uW. The transistor for biasing has Vth = 449.3mV, which means Vbias has to
be above 450mV to come out of cutoff mode. Id(current) for the system is 17.0uA.

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 Simulation 2: Specifications: Vbias = 800mV, L= 1.5um(All transistors)

Figure 16: T-spice for simulation 2 results.

Figure 17: Hspice for simulation 2 results.

The amplifier is modified by increasing Vbias to 800mV. Figure 15 displays T-Spice results: Open Loop
Gain = 4.5dB, Bandwidth = 316MHz, Unity Gain Frequency = 500MHz, and phase margin of 60 degrees.
Figure 16 displays Hspice results showing all transistors are in Saturation mode and power consumption is
171.2440uW. Id(current) for the system is 68.5uA. Increasing the Vbias didn’t reduced the open loop gain
and phase margin, but increased the bandwidth and the unity gain frequency.

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 Simulation 3: Specifications: Vbias = 400mV, W= 1.5um(All transistors)

Figure 18: T-spice for simulation 3 results.

Figure 19: Hspice for simulation 3 results.

The amplifier is modified by decreasing Vbias to 400mV. Figure 17 displays T-Spice results: Open Loop
Gain = 6.3dB, Bandwidth = 6.3MHz, Unity Gain Frequency = 12.6MHz, and phase margin of 65 degrees.
Figure 18 displays Hspice results showing all transistors are in Cutoff mode and power consumption is
1.2582uW. Id(current) for the system is 0.503uA. Based on the results, this design won’t allow the device to
operate.
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 Simulation 4: Specifications: Vbias = 480mV, W= 0.5um(Q1,Q2), W=1.5um(Q3,Q4)

Figure 20: T-spice for simulation 4 results.

Figure 21: Hspice for simulation 4 results.

The Vbias is set to 480mV for Simulations 4-7, and Final Design. For this simulation the transistors Q1 and
Q2 have modified W = 0.5um. Figure 19 displays T-Spice results: Open Loop Gain = 5.6dB, Bandwidth =
31.6MHz, Unity Gain Frequency = 50.1MHz, and phase margin of 60 degrees. Figure 20 displays Hspice
results showing all transistors are in Saturation mode and power consumption is 7.0705uW. Id(current) for
the system is 2.8282uA. Compared to Simulation 1, decreasing W for Q1 and Q2 bandwidth and unity gain
frequency, the gain is lower since the Vbias is at 480mV instead of 600mV.

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 Simulation 5: Specifications: Vbias = 480mV, W= 2.5um(Q1,Q2), W=1.5um(Q3,Q4)

Figure 22: T-spice for simulation 5 results.

Figure 23: Hspice for simulation 5 results.

For this simulation the transistors Q1 and Q2 have modified W = 2.5um. Figure 21 displays T-Spice results:
Open Loop Gain = 6.7dB, Bandwidth = 31.6MHz, Unity Gain Frequency = 63.1MHz, and phase margin of
68 degrees. Figure 22 displays Hspice results showing Q1 and Q2 in cutoff mode, and the rest of the
transistors are in Saturation mode and power consumption is 7.1593uW. Id(current) for the system is
2.8637uA. Based on the results, this design won’t allow the device to operate properly. This is due to biasing
issues due to small voltage range 0-2.5V between Vdd and Ground.

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 Simulation 6: Specifications: Vbias = 480mV, W= 1.5um(Q1,Q2,), W=0.5um(Q3,Q4)

Figure 24: T-spice for simulation 6 results.

Figure 25: Hspice for simulation 6 results.

For simulations 6-7 the transistors Q1 and Q2 have W = 1.5um. Transistors Q3 and Q4 have W=0.5um.
Figure 23 displays T-Spice results: Open Loop Gain = 7.0dB(Greatest from testing), Bandwidth = 39MHz,
Unity Gain Frequency = 79MHz, and phase margin of 72 degrees. Figure 24 displays Hspice results showing
Q1 and Q2 in cutoff mode, and the rest of the transistors are in Saturation mode and power consumption is
7.1043uW. Id(current) for the system is 2.8417uA. Based on the results, this design won’t allow the device
to operate properly. This is due to biasing issues due to small voltage range 0-2.5V between Vdd and
Ground. Shrinking W/L for Q3 and Q4 gave a larger gain, which is taken to the maximum in final design.
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 Figure 26: T-spice for simulation 7 results.

Figure 27: Hspice for simulation 7 results.

For this simulation, transistors Q3 and Q4 have W=2.5um. Figure 25 displays T-Spice results: Open Loop
Gain = 5.8dB, Bandwidth = 32MHz, Unity Gain Frequency = 50MHz, and phase margin of 62 degrees.
Figure 26 displays Hspice results showing Q1 and Q2 in cutoff mode, and the rest of the transistors are in
Saturation mode and power consumption is 7.1117uW. Id(current) for the system is 2.8447uA. Based on the
results, this design won’t allow the device to operate properly. This is due to biasing issues due to small
voltage range 0-2.5V between Vdd and Ground.
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 Final Design Simulation: Specifications: Vbias = 480mV, W=4.3um & L=250nm(Bias Transistor)

Figure 28: T-spice for final design simulation results.

Figure 29: Hspice for final design simulation results.

For the final simulation, transistors Q1 and Q2 have W = 4.3um and L=400nm. Transistors Q3 and Q4 have
W=0.7um and L=500nm. The biasing transistor has Vbias = 480mV, W=4.3um, and L=250nm. Figure 27
displays T-Spice results: Open Loop Gain = 13.9dB, Bandwidth = 22MHz, Unity Gain Frequency = 98MHz,
and phase margin of 89 degrees. Figure 28 displays Hspice results showing all transistors in Saturation mode
and power consumption is 14.5990uW. Id(current) for the system is 5.8396uA. Due to the small voltage
range of 2.5V instead of 3.3V, I had to do a lot of trial and error, but first goal was to make Q1 and Q2 have
largest W capable, and for Q3 and Q4, I tried to make W/L the smallest possible. Then I did trial and errors
with Q1’s and Q2’s L size. The biasing transistor had same W as Q1 and Q2 to have same size NMOS
transistors on layout.
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B. Performance Table

Figure 30

The performance table clearly shows that gain increases noticeably when W/L is reduced for Q3 and Q4
transistors. When Vbias is increased, the bandwidth and unity gain frequency are increased dramatically. The
chip area used in the table is from the final design since it was about the same size as the initial specification
design when put next together on the layout. Only considered FOM for the final design, since it was the only
one that really mattered, since it was the only design that achieved the minimum requirement of being greater
than 10dB.

IV. Conclusion
The design of the Differential Amplifier with Active Load with single-ended output was created with Vdd=2.5V.
Using the transistor for a 2.5V Vdd design created the major problem of not maintaining biasing when
transistors sizes were modified. I was still able to achieve a gain of 10dB, but this project would have been
easier using Vdd = 3.3V. This would allow to have a larger Vbias without causing problems. Since small
changes to the transistors made them go into cutoff mode, a few of the simulations for testing and comparing
couldn’t be used to analyze how the modifications were affecting the amplifier system. This forced me to do
trial and error, until I got a useful design.

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