DSP（Digital Signal Processing）

Hardware manual

Ver.1.0.0 Nov., 2016

Techno AP Corporation
No. 2976-15 Mawatari, Hitachinakaa-city, Ibaraki pref. 312-0012
PHONE.029-350-8011 FAX.029-352-9013
http://www.techno-ap.com
 第 1.0.0 版 2016 年 11 月

Disclaimer
We thank you for your kind usage of the products of Techno AP Coprporation (hereinafter
referred to as out company).

Even if the accident caused by using this product, we are not in a position to take any
responsibility for the damages of apparatus, peripheral devices, abnormality of software,
breakage and other damages including secondary damages.

Prohibited matters
This apparatus cannot be used for the purpose required special responsibility and quality
related to human life, and accident.
This cannot be used at the places with high temperature, high humidity, and place
subject to vibration.
Don not supply power beyond the rating.
Do not supply power with the state that board surface contacts other metal products.

Cautions
Turn power off immediately when smoke or abnormal heat generation occurs.
This apparatus may occur mal function at the place with plenty noise.
Pay thorough attention on static electricity
・ Specifications and contents of documents may be revised without preliminary notice.

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 第 1.0.0 版 2016 年 11 月

Table of contents

1. General description 4

1.1 General Description ４

2.1 General view ５．

2.1.1 APV8008 VME type DSP8CH 5.

2.2 APG8101 CPU board 8

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１． General description

１．１．General description

The digital spectrometer APV8004X is a 4-channel digital spectrometer. Because it is a multi-channel

analyzer (MCA) equipped with a real-time digital signal processing function (DSP), waveform shaping
processing by analog circuit becomes unnecessary, and using a very high speed A/D converter, it converts
signal from pre-amplifier directly into digital and processed in trapezoid filter in real time by pipeline
architecture with FPGA. This provides excellent energy resolution and time resolution, and it has excellent
stability even at high counting rate (over 100 kcps)

By connection with PC and LAN cable. this apparatus can set of parameter, data loading, analysis and read
out of measured data with the supplied application “APP-4SDD” (hereinafter referred to as this
application).

This document describes about handling of this apparatus.

２．１．Appearance

２．１．1. APV8008 VME type DSP8CH

（１）

（２）

（３）

（４）

（５）

（６） （７）

（８） （９）

（１０）

Fig. 1 APV8008

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 （１） LED ： P is power source, V is DSP processing, E is pile up detection
（２） CH1～8 ： LEMO connector for pre-amplifier signal inpot
（３） P.Z ： Pole zero adjusting knob
（４） F.G ： Fine gain adjusting knob. 0.333x ～ 1.0x.
（５） MONI ： LEMO connector for monitor output. Ouptputs DSP processing signal of
CH1～8.
（６） LEMO Left top（CLK） ： LEMO connector for external clock signal input. Inputs 25MHｚ
TTL signal.
（７） LEMORight top（GATE） ： LEMO connector for external gate signal input. Inputs TTL signal.
While input is “L”, this enablers data acquisition.
（８） LEMO Left bottom（VETO） ：LEMO connector for external beto ベト signa. While it is “H”, data
acquisition
is disabled.
（９） LEMO 右下（CLR） ： LEMO connector for external clear signal input. Inputs TTL signal.
Clears time counter data at the edfge of rising of “H”.
（１０） LAN ： RJ45 connector for easer net cable.

Explained on next page

（４）

（５）

（６）

（７）

（１）
（８）
（２）

（３）

（９）

Fig. 2 APV8004 board

（１） SW1 ： Not used.

（２） SW2 ： Unit number. Number to be added to List data

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（３） CN10、CN16 ： Connector for administrator debug
（４） JP1 ： Plural DSP corresponding jumper. Without JP1 jumper – not corresponds,
with JP1 jumper -
corresponds
（５） VME J1 ： J1 connector of VME. Not controllable from market available VME
controller.
（６） CN14 ： Power connector for debug. EI connector (4PIN). No. 1 – 5 or 6V, No. 2 GND, No. 3 -
+12V,
No. 4 – 12V.

-12V +12V GND +6V

（７） CPU board： As for details, refer to the later description.

（８） VME J2 ： J2 connector of VME. Not controllable from market available VME
controller.
（９） MFC NO ： Serial No.

（５）
（６）

（７）
（１）

（２）

（３）

（４）

Fig. 1 APV8004Board input

（１） ×0.1、×1.0 ： Jumper for attennutor. ×1.0 multiplies input by 1.0 times（default）, ×0.1
multiplies input by
0.1 times.
※ Surely jumper either one.
（２） CN1 ： LEMO connector for pre-ampliifier signal input
（３） VR2 ： Knob for pole zero adjustment
（４） VR1 ： Knob for fine gain adjustment. 1～3 times.
（５） DC ： First stage differential circuit jumper. No jumper is enabled (default), jumper is
invalid
（６） RC ： Pole zero adjustment jumper. Use in accordance with type of detector. With jumer –
valid (default) in case of rtesistance feed back type, without jumer – invalid in case of
reset type.
（７） RSW1 ： Switch for shaping time setting. １ is 2.2μs, 2 is 3.9μs, 3 is 6.8μs（defauｌｔ）.
For X-Ray detectging (SDD and so on) - １ is 0.56μs, 2 is 1.5μs, 3 is 6.8μs
（default）.

２．２．APG8101 CPU Baord

DSP products such as APV 8000 and APN 7000, use Techno AP's CPU board APG 8101 as an interface
for various external setting and data acquisition. The APG 8101 is equipped with a microcomputer, FROM,
SDRAM, SRAM, RTC, LAN as standard.
Use the network function of this board, execute parameter setting of DSP, acquisition/-
transmission of event data, creation and transmission of histogram data, etc.
This also sets and stores network information such as IP address necessary for communication with the

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 DSP.

（１） General view

Fig. 2 APG8101
（２）Specifications

CPU ： SH7619（SH-2） from RENESAS

Max. operative frequency 125MHｚ、Ethernetcontroller
Flash FOM ： MBM29LV160T-90PFTN 16MB from SPANSION
SDRAM ： MT48LC16M16A2P-75 256MB from MICRON
SRAM ： R1LV0414DSB-5SI 4MB from RENESAS
RTC ： RTC-9701JE from EPSONTOYOCOM
Built-in serial interface RTC from EEPROM
Connector
For boaｒｄ ： FX8C-100S-SV5(91) 100 pin from HIROSE
For debug ： DF11-14DP-2DS 14 pin from HIROSE
Switch ： RES(Reset), SEL（Select） and INC（Increment）
Ethernet ： Corresponds to 100Base
Overall dimensions ： 100(W)x60(H) x11(D) ※Excl. RJ45 connector
Weight ： 34g ※Excl. RJ45 connector
Operative condition ：Working temperature 0 ～ 40℃, no condensaqtion

（3）Network information setting

Settings of IP address of CPU board, sub-net mask, default gateway can be altered. The network
information is secured in the following CPU board APG 8101. Below is the setting method of network
information using APG 8101.
RES switch
reset

INC switch
increment

SEL switch 7seghment LED

Select

Fig. 3 CPU board APG8101

・Check the positions of the SEL switch, INC switch, RES switch, and 7 segment LED on the CPU board
APG 8101.
※ When setting up with NIM or VME chassis, be sure to secure enough working space so as not
to get injured.

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・Turn on DSP.
・While pressing SEL switch, press RES switch for a moment.
・Wait for approx. 1 se3cond, then release SEL switch.
After4 releasing, check that the dot part of 7 segment LED flashes.
Flashing of dot of 7 segment LED expresses the beginning of the 24 times setting.
When it does not flash, press RES switch and start from the above （３） again.
・Set IP address
The setting is done in hexadecimal notation. In case default is 192.168.10.128, set the eight characters
of "C0A80A80".
While watching the 7-segment LED, press INC switch continuously until it reaches "C". When reached,
press SEL switch once to move to next "0" setting.
Confirm that the next value is displayed and the dot is lit.
Dot lighting indicates that setting of lower 4 bits of setting 8 bits is in progress.
Press INC switch continuously until it reaches "0" while watching the segment LED.
In the same way also set the remaining 6 characters.
・Set the subnet maskl.
After setting 8 characters of IP address, go to subnet mask setting in hexadecimal notation. In case
default is
255.255.255.0, set 8 characters of “FFFFFF00”.
Setting method is the same with IP address setting.
・Set default gateway.
After setting 8 characters of the subnet mask, move on to the default gateway setting in hexadecimal
notation. In case of default 192.168.10.1, set the eight characters "C0A80A01".
The setting method is the same as for IP address.
Upon completion of setting, it returns to the setting of IP address of the beginning, and
”C” is disp0layed on 7 segment LED and dot flashes.
・Check the contents of setting.
Check the contents of setting while pressing SEL switch 24 times continuously and confirm returning to the head is
possible.
・Press RES switch.

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 SEL switch+RES switch

Flash
C。
↓
0.
↓
A
↓
8.
↓
IP address 0
↓
A.
↓
8
↓
0.
↓
F
↓
F.
↓
F
↓
F.
↓
F
↓
subnet mask F.
↓
0
↓
0.
↓
C
↓
0.
↓
A
↓
8.
de
↓
0
↓
A.
default gateway ↓
0
↓
1.

Fig. 4 Network information setting order

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