Karnatak Law Society’s

Vishwanathrao Deshpande Institute of Technology, Haliyal - 581 329

Doc. No.: VDIT/ACAD/AR/05b Rev.No.:02
Page 1 of 1 Rev. Dt: 25/03/2021
IA TEST QUESTION PAPER
AY: 2021-22
Department: Electronics & Communication Engineering SET 2 IA Test No: 1
Semester / Division: 1 (E/F/D) Date:
Subject with Sub-code: Basic Electronics & Comm Engg – 21ELN14 Time:
Faculty Name: Dr. Arun Kakhandki/Dr. Vikas Balikai/Prof. Nikhil Kulkarni Max Marks: 50
Note: Answer any one full question from each module; each full question carries 25 marks.
Module 1 Mark
s
1a Explain with neat circuit diagram the working of Bridge rectifier with reservoir capacitor. (10)
b Draw the block diagram of both negative feedback and positive feedback amplifier and
obtain the expression for gain. (10)
c A mains transformer having a turns ratio of 44:1 is connected to a 220 V r.m.s. mains
supply. If the secondary output is applied to a half-wave rectifier, determine the peak
voltage that will appear across a load. Assume a forward voltage drop of 0.7 V. (5)
OR
2a What are the ideal characteristics of opamp. Explain how opamp can be used as an
integrator and differentiator with neat circuit diagram. (10)
b Explain i) Voltage multipliers ii) frequency response characteristics for various types of
amplifier (10)
c A 5 V zener diode has a maximum rated power dissipation of 500 mW. If the diode is to be
used in a simple regulator circuit to supply a regulated 5 V to a load having a resistance of
400 Ω, determine a suitable value of series resistor for operation in conjunction with a
supply of 9 V. (5)
Module 2
3a Explain in detail the working of 8:1 multiplexer and 3:8 decoder (10)
b Explain in detail with a neat block diagram “a typical microcontroller system”. (10)
c Explain the operation of D bistable in detail. (5)
OR
4a A logic arrangement has to be designed so that it produces the pulse train shown in Fig. 4a.
Devise a logic circuit arrangement that will generate this pulse train from a regular square
wave input.

Fig 4a (10)
b Explain in detail the operation of all the logic gates. (10)
c Convert i) 11101010101010 = (?)16 = (?)10 ii) CEABC = (?)2 = (?)10 (5)

Q.No. CO PO BLT Q.No. CO PO BLT Q.No. CO PO BLT Q.No. CO PO BLT

1
1(a) 1 2,3 L2 2(a) 2,3 L2 3(a) 2 2,3 L3 4(a) 2 2,3 L3
1(b) 1 2,3 L2 2(b) 1 2,3 L2 3(b) 2 2,3 L2 4(b) 2 2,3 L2
 1 1 2 2
1(c) 2,3 L2 2(c) 2,3 L2 3(c) 2,3 L2 4(c) 2,3 L2