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Pulse Width Modulation Control Circuit: Semiconductor Technical Data
Pulse Width Modulation Control Circuit: Semiconductor Technical Data
The SG3526 is a high performance pulse width modulator integrated PULSE WIDTH MODULATION
circuit intended for fixed frequency switching regulators and other power CONTROL CIRCUIT
control applications.
Functions included in this IC are a temperature compensated voltage
reference, sawtooth oscillator, error amplifier, pulse width modulator, pulse SEMICONDUCTOR
metering and steering logic, and two high current totem pole outputs ideally TECHNICAL DATA
suited for driving the capacitance of power FETs at high speeds.
Additional protective features include soft start and undervoltage lockout,
digital current limiting, double pulse inhibit, adjustable dead time and a data
latch for single pulse metering. All digital control ports are TTL and B–series
CMOS compatible. Active low logic design allows easy wired–OR
connections for maximum flexibility. The versatility of this device enables
implementation in single–ended or push–pull switching regulators that are
transformerless or transformer coupled. The SG3526 is specified over a
junction temperature range of 0° to +125°C.
• 8.0 V to 35 V Operation 18
–Error 2 17 VCC
Compensation 3 16 Output B
Representative Block Diagram
CSoft–Start 4 15 Ground
18
Vref Reset 5 14 VC
Under–
17 Reference Voltage
VCC
Regulator –CS 6 13 Output A
Lockout
15 +CS 7 12 Sync
Ground To Internal
12 Circuitry 14
Sync Shutdown 8 11 RDeadtime
11 VC
RDeadtime
9 Oscillator 13
RT RT 9 10 CT
10
CT
Output
A (Top View)
5
Reset Soft
4 Start Toggle
CSoft–Start Memory F/F
3 F/F
Compensation Q
VCC S T
SQ Q
1 Amp – RQ
+Error +
2 + D 16 ORDERING INFORMATION
–Error – Q
7 Output Operating
+C.S. + Metering
6 B
–C.S. – F/F Device Temperature Range Package
8
Shutdown SG3526N TJ = 0° to +125°C Plastic DIP
50 mV 4.0
Spec
Limit 3.0
2.0
1.0
–75 –50 –25 0 25 50 75 100 125 150 1.0 2.0 3.0 4.0 5.0 10 20 30 40
TJ, JUNCTION TEMPERATURE (°C) VCC, SUPPLY VOLTAGE (V)
7.0
SHUTDOWN VOLTAGE (V)
A Vol , VOLTAGE GAIN (dB)
6.0
80
5.0
60
4.0
40
3.0
20 1 +
_ 3 2.0
2
100 pF CComp
0 1.0
0
10 100 1.0 k 10 k 100 k 1.0 M 10 M 25 50 75 100 125 150 175 200
f, FREQUENCY (Hz) DIFFERENTIAL INPUT VOLTAGE (mV)
8.0 2.5
7.0
2.0
6.0
RESET VOLTAGE (V)
5.0
1.5
4.0
3.0 1.0
2.0
0.5
1.0
0 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 2.0 5.0 10 20 50 100 200
Vref, REFERENCE VOLTAGE (V) OUTPUT DRIVER SINK CURRENT (mA)
100
2.0
R T, TIMING RESISTOR (k Ω )
50
1.5
20
1.0
10
0.5 5.0
0 2.0
10
2.0 5.0 10 20 50 100 200
0.1
1.0
100
0.01
1000
20
50
0.2
0.5
2.0
5.0
200
500
0.02
0.05
0.002
0.005
IC, SINK CURRENT (mA)
OSCILLATOR PERIOD (ms)
VCC Vref
Q6
To Reset
Vref
Q5 R1
125 To Driver A
µA + To Driver B
Q11
1.2V
Q3 Q4 Bandgap –
50µA Reference
50µA
Q12 R2
100µA
14µA 100 14µA 3 Compensation
µA Q10 100µA
Q7 Q8 Q9
Q1 Q2
1.0k 500 1.0k 500
1
– Error + Error
Memory
F/F The metering Flip–Flop is an asynchronous data latch
which suppresses high frequency oscillations by allowing
Sync S only one PWM pulse per oscillator cycle.
S Q R Q Clock
PWM D
Q PWM The memory Flip–Flop prevents double pulsing in a
push–pull configuration by remembering which output
Metering produced the last pulse.
F/F
APPLICATIONS INFORMATION
Figure 12. Extending Reference
Output Current Capability Figure 13. Error Amplifier Connections
Negative
Output
C* R1 Voltage
R3 1 + R2 1 +
Vref Vref
27 17 Reference 18 2 – 2 –
VCC Vref
Regulator R2 R3
+ R1 Positive
15 10µF Output
Gnd Voltage Gnd
Gnd
R1 + R2 R1
Vout = Vref Vout = Vref
* May be required with some types of transistors R2 R2
R1R2
R3 =
R1 + R2
Output Filter +
RS
11 12
SG3526 Sync
– 6
8 Vout
R1
RD 9 10
+ 7
R2
Gnd –
RT CT
Vout R1
0.1 V +
R1 + R2 0.1 V
I(max) = ISC =
RS RS
Figure 16. Soft–Start Circuity Figure 17. Driving VMOS Power FETs
+12V
Vref
100 14
Ramp –
µA VC
+ Error
1 + PWM A 13
Error +
2 – Amp
– Error
SG3526
Q2
5 Q1
Reset 16
B
Gnd
To
Q3 Undervoltage
Lockout CSoft–Start
+V Supply Q1 To +V Supply
R1 Output
Filter R1
C1
R2 14
VC 13 R2 T1
A Q1
14
VC C2
13 SG3526
A
SG3526 16 R3
16 B Q2
B Gnd
Gnd 15
15
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
18 10 MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
B 2. DIMENSION L TO CENTER OF LEADS WHEN
1 9 FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
A MILLIMETERS INCHES
DIM MIN MAX MIN MAX
L A 22.22 23.24 0.875 0.915
C B 6.10 6.60 0.240 0.260
C 3.56 4.57 0.140 0.180
D 0.36 0.56 0.014 0.022
F 1.27 1.78 0.050 0.070
N K G 2.54 BSC 0.100 BSC
J H 1.02 1.52 0.040 0.060
F D SEATING M J 0.20 0.30 0.008 0.012
PLANE K 2.92 3.43 0.115 0.135
H G L 7.62 BSC 0.300 BSC
M 0_ 15_ 0_ 15 _
N 0.51 1.02 0.020 0.040
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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*SG3526/D*
10 ◊ MOTOROLA ANALOG IC DEVICE DATA
SG3526/D