INTEL (2020-22)

1. Introduce yourself
2. Why VLSI?
3. What are your favourite subjects in 1st sem
4. Explain briefly about your projects
5. What is pipelining
6. Pros and cons of CMOS circuits
7. What do you mean by robustness in CMOS
8. Why high noise margin is needed
9. Difference between Flip Flop and Latch and which is preferred the most?
Justify?
10.Why clock is used
11.Different types of power dissipation in CMOS
12.Explain SC power, reasons for it, how would you reduce it
13.What is leakage power in CMOS, reasons, methods to reduce
14.Which type of power dissipation is more dominant in CMOS, justify?
15.Explain CMOS inverter VTC (in deep with regions of operation for PMOS,
NMOS)
16.Dynamic power equation, explain all terms, which has huge impact on
Pdyn
17.If you were given a circuit and asked to reduce dynamic power, what will
be your approach
18. Two Flip Flop’s with a combinational circuit in between them is given
• Explain how many delays are present in the circuit
• How would you assure that correct input will be present at the input of
2nd Flip Flop
• How would you increase clock delay for 2nd FF, decrease delay in
combinational circuit, adv and disadv of doing so
19.Setup time, hold time
20.Problem on capacitor
• C1 = 5fF and is already charged using 5v battery source, C2 = 2fF not
charged, if C1, C2 are connected using a switch between them What
happens?
21.Which domain you are interested in
22.Are you ready to work in backend
1. Tell me about yourself
2. NMOS and PMOS operation in cutoff linear and saturation
3. Realization of XOR and NAND using 2:1 Mux
4. Difference between Latches and Flip Flop. Why are latches still being
used? [ He told to look into the concept of Time Borrowing]
5. Skew
6. Setup Hold time explanation
7. Maximum frequency of operation of design using the timing constraints
8. Pinchoff
9. Latchup
10.Body effect

1. CMOS operation
2. Dynamic Power
3. Static power
4. Leakage power
5. Setup time
6. Hold time
7. Metastabilty

1. Asic design flow.

2. Tell me about yourself.
3. Parametrized verilog or system verilog code of universal shift register.
4. Timing diagram of D-flip flop(+ve and -ve edge triggered).
5. Realization of and gate using 2:1 mux and if the inputs of mux
interchanged what will be the Resulting Gates.
6. Synchronous and asynchronous clock difference.
7. Synchronous and asynchronous reset difference.
8. Blocking and Nonblocking assignments, where it is used and why.
9. Setup and hold time.
10.Setup and hold time violations and How it can be eliminated.
11.Transparent latch.
12.Difference between latch and flip flop.
13.Difference between combinational and sequential circuits.
14.Fpga and asic difference. Which is opted more?.

1. Explain the CMOS operation

2. Theory concepts of PERL, Verilog and TCL
3. Setup and Hold time Violations. Explain about SDC
4. Difference between Latch and Flip Flop
5. Static and Dynamic circuits
6. Power models in CMOS
7. Difference between Blocking and Non
8. Blocking assignments
9. Explain the role of inversion layer in CMOS
10.CMOS INVERTER characteristics
11.What are the advantages and disadvantages of CMOS
12.What is meant by technology node?
13.Why do we use verilog HDL?
14.Explain about the PERL experiments you did in your lab?

1. Explain any of your project

2. Equivalent resistance from network theory..( he drew a ckt in a small
white board- moderate level_but tricky)
3. Gave a waveform of clock, some input and at some time period output as
1 for half clock cycle. Asked me to design a ckt which can detect the
raising edge.(raising edge detector)
4. Setup time - hold time, and equations if u know.
5. Asynchronous and synchronous ckts,
6. Blocking and non blocking assignments differences and which are used in
async and synchronous ckts?
7. Asynchronous reset program.
8. Differences between verilog and system verilog, what is oops ?
9. Gap in education ?

1. Tell me about yourself?

2. Explain your projects?
3. Draw CMOS Nand Gate?
4. Difference between mealy and moore machine?
5. Difference between synchronous and asynchronous reset?
6. Tell advantages and disadvantages of synchronous and asynchronous
reset?
7. Tell about cache memory?
8. What are your strengths?
9. What is ASIC Flow?

1. Tell me about yourself

2. Explain your projects
3. Set up time , hold time
4. electromigration
5. cmos cross-section
6. How current varies cmos inverter?
7. How to avoid latchup?
8. Pinchoff
9. IR drop

1. Tell me about yourself

2. Explain your project
3. Do you know anything about cache memory
4. What is setup and hold time
5. How do you resolve hold time violation?
6. Are you comfortable with verilog coding?
7. Verilog code for 1:4 demux

1. Mux
2.project
3.do you know oops?
4.do you about system verillog?
5. Verilog code non blocking and blocking.
6. Aptitude questions.
7. C questions related to function,pointer,typedef.

1. Introduce yourself
2. Most questions from resume
3. Any other topics that I know other than given in my resume..If yes then
what are the topics?
4. Questions about btech and mtech projects
5. How can i implement my btech project in mtech
6. Working of SRAM( 6T,8T), output waveform characteristics
7. ASIC design flow
8. Which field are you looking for in intel
9. What is floorplanning, placement and routing
10.What is physical design in ASIC
11.What is frontend and backend design
12.Which all subjects are studied in current semester

1. Tell me about yourself

2. General and specific questions based on the projects mentioned in
Resume (mainly from work experience)
3. Simple verilog questions : To find the output of blocking and non
blocking statements
4. System verilog : To find the output of a piece of code, related to
inheritance and Polymorphism
5. List all the subjects covered in the curriculum. They were looking for
topics related to circuit level design
6. Would you be interested in working in the IP Design team?
7. General HR questions: Why did you choose Intel for Internship? Why
should Intel take you?

1. tell me about your project.

2. Asic design flow
3. Rtl compiler synthesis flow
4. Define each step
5. Which domain you want to work and why?
6. What is constraints why you use.
7. Verilog question
8. System verilog
9. Polymorphism
10. ATPG
11.Test pattern
12. Related to project
13. Scan chain

1. RISC Processor
2. ASIC Flow

1. Introduction
2. Project, Timing closure, Synthesized netlist,
3. how to avoid setup/hold violation, verilog code for mux with different
modelling,
4. verilog code to find no: of 1's in a given binary no
5. At the end he asked me name of different fabrication unit..(company
name) + 1 aptitude question
6. Technology inversion.

1. Explain briefly about your projects?

2. Difference between Verilog and VHDL?
3. Difference between blocking and non blocking statements?
4. What is meant by cashing?
5. What are the memories present other than cache memory?
6. Explain the ASIC flow?
7. Why did you use Cadence ?
8. How will you write verilog code for the complex systems?