https://www.vlsiguru.

com/zz-verilog-notes-july2020/
1] Number System:-
• Conversion of a particular number into its equivalent binary, octal,decimal
and Hexadecimal and vice versa.
• Questions could be asked on XS-3 codes,1’s and 2’s complement operation and
finding the base of a number and different weighted and non weighted code.
2] Logic Gate:-
• Why Nand and Nor are called as universal gates (or) Derive all other gates
using only Nand and Nor.
• A particular expression can be given in either SOP or POS and can ask to
optimise the circuit using only Nand or Nor.
• What is the practical application of XOR and XNOR gate?
• A particular circuit could be given and asked to find the output.
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Now from the following topic onwards actual logical and tricky questions starts. So
prepare the following topics nicely:-
3] Combinational Circuits:-
• Implement all the basic gates using 2:1 Mux.
• Implement 4:1 Mux using 2:1 Mux
• Implement Full adder using 4:1 Mux
• A function will be given like f(a,b,c) = sum(m){1,3,5,6} and implement it
using 4:1 and 2:1 Mux.
• Implement 2:1 Mux using Tristate buffers.
• Design 4:16 Decoder using 3:8 Decoder.
• Design Full adder using 3:8 Decoder.
• Implement Full adder(FA),HA,FS,HS using either NAND or NOR gates.
• Implement Full adder using Half Adder.
• LAC adder and it's working principle.
• Questions on Implicants,Prime Implicants and Essential Prime Implicants.
• Karnaugh Map and Tabulation Method - Which one to use and when.
• Hazards types and Causes.
4] Sequential Circuits:-
• Conversion of one Flip Flop to another like JK to SR,T to D,etc.
• Race around condition in JK flip flop and how to avoid it.
• Difference between Latch and Flip Flop.
• Different types of shift register and it's working.
• Difference between Johnson and Ring Counter.
• Design a synchronous counter using JK flip flop and count sequence in XS-3
code.
• Implement a counter with Mux
• Design a MOD 10 counter with 50%/33% duty cycle.
• Difference between Mealy and Moore State Machine.
• Sequence detector problems like Design a Mealy/Moore FSM for 1001.
• Design a Mealy FSM for 010 and 1010.
• Frequency Divider Circuits.
5] Advance Digital:-
• Setup and Hold time and what is Metastability and how to avoid it.
• Clock Skew/Slew/Slack/Propagation Delay.
• What are False Path and Multicycle Path.
• Hold Slack Calculation of a given Circuit.
• Frequency calculation of a given Circuit.
• Reset Strategies and what is asynchronous assertion and Synchronous
Deassertion.
• Clock domain Crossing and what is asynchronous CDC.
• What are synchonisers and when to use them.
• FIFO depth Calculation of a Asynchronous FIFO.
• What is Empty and Full Condition in FIFO.
• Between Binary and Gray Counter,which one to use and why?
• Basic questions on number systems
• Implementation of all basic gates using MUX
• Implementation of all gates using universal gates (NAND, NOR)
• Combinational circuit designs/differences - Mux, Demux, Encoders, Decoders
• Implementing D-flip flop from T-flip and similar quetions
• Difference between synchronous and asynchronous reset, advantages,
disadvantages and how to model them in an HDL like Verilog/SystemVerilog
• Questions related to timing, setup/hold time, clock skews, problems to
compute maximum operating frequenct etc
• Different counters like synchronous/asynchronous,
• Different adder circuits like ripple carry and carry look ahead and benefits
of each
• Statemachine design problems - One common tricky question is to find a
sequence detector with some overlapping patterns
• Expect questions on basic HDL programming which is also part of any Digital
logic design job - Questions like blocking/non-blocking assignments in Verilog,
difference between case statements, modelling flip flop vs latch, modelling
statemachines etc
• Circuit for 1st one finder for a series input
• For an input clk of f frequency generate an output of 2*f frequency
• For an input clk of f frequency generate a clk output of frequency f÷(3/2) or
(5/2)
• Clock dividers with 50℅ duty cycle
• Sequence detectors
• Output should be high for only odd +ve edge transition
• Max frequency calculation with transmitter as +ve edge flip flop and receiver
as - ve edge flipflop with combinational circuits having false paths in it
• Sync and Async counters (Mod n counter)
• Difference between Blocking and non_blocking statement in verilog
• Setup and hold time definition and expression for both latch and flipflop
• FSM - Mealy,Moore
• Synchronous and Async Reset difference
• Latch vs Flipflop
• All logic gates implementation using NAND , NOR
• Logic gate implementation using MUX .
• Boolean exp implementation using Decoder.
• No. of 2*1 mux needed for 64*1 mux
• No. of 2*4 decoders needed to implement 4*16 Decoder
• Finite state machines mealy and moore machine. Sequence detection like
10100,01011 etc using both mealy and moore machine and their verilog implementation
• Combinational circuits like carry look ahead adder, Multiplexers, decoder,
Priority encoders etc
• Basic Setup and hold time ( For M.techs they will go in deep into this)
• Logic implementation using MUX
• frequency division problems like f/3 with 50% duty cycle
• edge detection problems for positive and negative edge
• Synchronous reset and asynchronous reset their advantages Disadvantages. How
to model them.
• Random bits generation using shift registers
• Counters synchronous and asynchronous
• Clock domain crossing and Metastability questions ( for M.tech students)
• Synchronizers and MTBF
• Asynchronous FIFO ( Mtech )
• Memories SRAM, DRAM
• Verilog code for all the combinational and sequential circuit
• An easy example is,
what are different type of counters?
Ans: ripple counter, synchronous counter, ring counter, Johnson counter etc.
• So which counter will consume less power? Which will have largest area?
• You can dwell as deep as needed on a simple design to get the fundamentals
verified.
• Another thing is to ask to design a logic circuit. For instance, given an
input digital clock design digital circuit to divide the clock by 3, how about
divide by 5?
• The interviewer will generally look at how you approach the design. Do you
take care of all the possibilities? You might also be asked to test your design.
what is 1's complement and 2's complement? where it is used?
2. Implementation of basic gates using MUX (they frequently ask this!!), also they
may ask you to implement any function using MUX.(e.g. design D flip flop using MUX)
3. Implementation of basic gates using arithmetic operators
4. how can you implement and/or/not gate using NAND/NOR?
5. what is the difference between flip flop and latches?
6. conversion of flip flops (e.g. convert T flip flop to D flip flop)
7. what is race around condition and how to avoid it?where does it occur?
8. what is master slave configuration? why to use it?
9. what is synchronous and asynchronous counter?
10. design mod x counter (x can be 2, 3, 5 etc.)
11. what is the difference between synchronous reset and asynchronous reset?
12. what is set up time and hold time in digital circuits? conditions for set up
time violations and hold time violations?
13. what is clock gating? how it is implemented? how glitch appears in AND gate
based clock gating? how to avoid it?
1. In your design you have dual port memories each working at a different
frequency. What is the clock frequency you use for testing (MBIST)?
2. When a failure is detected in parallel testing of memories, how do you know
which memory is failing?
3. What are the extra pins needed for BIRA (Built In Repair Analysis)
implementation?
4. What could be the possible reasons for scan chain failures during GLS (Gate
level Simulation)? Other than setup issues.
5. Did you got any issues during timing simulation of MBIST patterns?
6. What are typical frequencies for scan shift, MBIST tests?
7. How is it different implementing MBIST logic for ROMs, SRAM, DRAMS, and register
files? Can same controller handle all these? What are the typical issues faced?
8. What are the differences between IJTAG and JTAG standard?
9. What are the differences between Boundary scan and IEEE1500 standards? Other
than Boundary scan is used for board level testing and the IEEE1500 for core based
testing.
10. What is the effect of LOS method for testing delay faults on the tester?
11. What are the typical issues you face during timing simulation of scan and MBIST
patterns?
12. What are copy and shadow cell? How are they useful?
13. What are the typical clock skew issues you faced during post layout/ timing
simulation?
14. How do you implement DFT for a design have lot of Analog blocks? How to improve
coverage?
15. How do you test at-speed faults for inter clock domains?
16. Are multi-cycle paths tested in the design?
17. Why do you need multiple-load patterns? What are its advantages over basic scan
patterns?
18. What are the typical steps to improve coverage when our coverage target is not
achieved?
19. Steps to fix broken scan chain issues during ATPG? Step by step procedure to
find the issue?
20. What is sequential depth?
21. How to specify clocks for at-speed testing in encounter test or any other tool?
What is the syntax?
22. In SDF we have 3 values best, typical and worst case? Best is for good
processor, less temp , high vol and worst is reverse. What is typical?
23. What is split capture?
24. What Is the most challenging issue you faced? How you fixed it?