Timing Analysis( Pre- STA)

Types of Timing analysis

• STA : Static Timing Analysis
• DTA : Dynamic Timing Analysis
 What is Static Timing Analysis?

 Static Timing Analysis is a method for

determining if a circuit meets timing
constraints without having to simulate
Much faster than timing-driven, gate-level
simulation
Proper circuit functionality is not checked
Vector generation NOT required
 Static Timing Analysis (STA)

• Advantages
 Fast, exhaustive
 Better analysis checks against timing requirements
• Disadvantage
 Less accurate
 Must define timing requirements/exceptions
 Difficulty handling asynchronous designs, false paths
 Types of STA

Pre-layout STA : wire load models

Post-layout STA : Tlu+ / Captables
 PRE STA In ASIC flow
Logic Synthesis

Constraints
(clocks, input drive,
output load) Design For test

Floor planning
Static Timing Analysis

Static Timing Analysis

(estimated parasitics)
 Pre-layout Timing

• Here the interconnect parasitics are estimated

using wireload models during the pre-layout
timing verification. In many cases,
• The resistance contribution in the wireload
models is set to 0.
• In such scenarios,the wireload contribution is
purely capacitive.
 Inputs to pre-STA
• Netlist
• SDC
• libraries
 Wire loading models

• Used to estimate the interconnect wire delay during pre-layout in a

design cycle. Wire load information is based on statistics from
physical layout parasitic.

• Different for different technology. Wire load models are

approximated from one technology to another based on scaling
factors. Due to these approximations, the accuracy of these models
diminish over multiple technology nodes.

• Describes effect of wire length and fanout on

Resistance,Capacitance, Area of the nets.
• All attributes (R, C and Area) are given per unit length wire.
• Slope value is used to characterize linear fanout.
 Here is an example of a wireload
model.
• wire_load (“wlm_conservative”) {
• resistance : 5.0;
• capacitance : 1.1;
• area : 0.05;
• slope : 0.5;
• fanout_length (1, 2.6);
• fanout_length (2, 2.9);
• fanout_length (3, 3.2);
• fanout_length (4, 3.6);
• fanout_length (5, 4.1);
• }
 Wire loading models
based calculations
• Length = 4.1 + (8 - 5) * 0.5 =
5.6 units
• Capacitance = Length *
cap_coeff(1.1) = 6.16 units
• Resistance = Length *
res_coeff(5.0) = 28.0 units
• Area overhead due to
interconnect = Length *
area_coeff(0.05)
• = 0.28 area units
• The units for the length,
capacitan
Extraction data of already routed designs are used to
build a lookup table called the wire load model
WLM is based on the statistical estimates of R and C
based on “Net Fanout”

.
Cell delay calculation
 Why SDC?
• Synopsys /standard Design Constraints is the
way for constraining the Design according to
Design Specifications like
• Timing (Speed)
• Area
• Power
 SDC contains

• 1) Optimization constraints: area, power and timing.

• 2) DRC’s: max fan out. Max transition min/max

capacitance.
•
• 3) Clock exceptions: false paths, multi-cycle paths,
disable paths.

• 4) Environmental SDC’s: PVT conditions, I/p & o/p

load.(set_load, set_driving_Cell)
 Basic SDC commands

• Timing related command comes under optimization

constraints:

• 1) Create_clock. 2)Create_ generated_clock.

3) Set_clock_ latency. 4)Set_clock_transition
5)Set_clock_uncertainty. 6) Set_min_pulse_width
7)Set_max_area 8) Set_input_delay
9)Set_output_delay 10)Set_propagated_clock
 Create_clock
• Generally clock acts as a Reference input for the sequential Elements for
proper operation.
• To define a clock, we need to provide the following information:
Create _clock
-Name: name of the clock
-Clock source: it can be a port/pin.
-Period: the time period of the clock.
-Duty cycle: on period and off period

Create_clock –period 2 [get_ports clk1]

Create_clock –period 2.5 [get_ports clk2]
Create_clock –period 6 –waveform {0 3} [get_ports clk3]
Create_clock –period 10 –waveform {0 5} [get_ports scanclk]
 Generated clocks
• We can avoid an extra PLL in design.(extra clock domains)
• We can use the timing constraints of source clock.
• Generated clocks are less prone to external effects.

Create_generated_clock –name clk5 –source [get_ports clk1] – divided_by 2 [get_pins

inst1/est/q]
Create_generated_clock –name clk6 –source [get_ports clk1] – divided_by 4 [get_pins
inst2/est/q]
 Virtual clocks
• virtual clock is not a real clock, it is used to constrain i/o paths.
• we can define input and output's relative delay by
• Instead of using set_max_delay to constraint ur combo block, we can use
virtual clock and use set_input_delay and set_output_delay, which can
decreases runtime and memory usage in DC.

Create_clock –period 2 vclk1

Create_clock –period 2.5 vclk2
Create_clock –period 6 vclk3
 Clock latency
• Clock latency is defined as the amount of time from the clock
origin point to the sync pin of the flop
 Clock Uncertainties
• Clock uncertainty is the difference between 2 clock signals. It could be the
same clock signal arriving at two different points on a PCB. (Skew).
• Clock uncertainty is jitter, skew and margin.
• Jitter is the variation in the clock period ( that is the clock edge might not
be at the required time). Jitter could be caused due to various on chip
variations.

Set_clock_uncertanity –setup 0.10 [get_clocks –all]

Set_clock_uncertanity –hold 0.05 [get_clocks –all]
Constraining Input to reg path
Constraining Reg to output path
Setting driving cells and output loads
 Clock exceptions
• i. set_case_analysis: Specifies constant value
on a pin of a cell, or onan input port.
• ii. set_disable_timing: Breaks a timing arc of a
cell.
• iii. set_false_path: Specifies paths that are not
real which implies thatthese paths are not
checked in STA.
• iv. set_multicycle_path: Specifies paths that
can take longer than onclock cycle.
Timing paths
Pre and post layot timing paths
 Checks to be Done at Pre layout Timing

• Here the Timing is Estimated with ideal clocks.

• Setup Checks –Zero Interconnect Models
• As timing is done with ideal clocks we will not
do hold Analysis.
 Basic Sanity Checks after PRE layout
Timing
• All clocks are defined properly
• All generated clocks are assigned with proper
source clock
• i/o delays are properly defined are not.
• No Dpin should assign with clocks
• There should be any combination loops
• Setup Checks.
 Report_timing Command
• Report_timing –from ck/uff1 –to D/uff2
• –delay min/max
• –crosstalk_delta
• –max_paths max_path_count
• - transition time
• –voltage
• -temperature
• -slack_greater_than limit
• -slack_lesser_than limit
 Basic SDC File
• #defining clocks
Create_clock –period 2 [get_ports clk1]
Create_clock –period 2.5 [get_ports clk2]
Create_clock –period 6 –waveform {0 3} [get_ports clk3]
Create_clock –period 10 –waveform {0 5} [get_ports scanclk]

• #Defining virtual clocks

Create_clock –period 2 vclk1
Create_clock –period 2.5 vclk2
Create_clock –period 6 vclk3

• #Defining Generated Clocks

Create_generated_clock –name clk5 –source [get_ports clk1] – divided_by 2
[get_pins inst1/est/q]
Create_generated_clock –name clk6 –source [get_ports clk1] – divided_by 4
[get_pins inst2/est/q]
 Cont…
• #Defining clock relation and groups
Set_clock_group –asynchronous-group {clk1 clk5 clk6} –group {clk2}
Set_clock_group -logically exclusive -group {clk * } –group { scanclk}

Asynchronous clocks: no relation b/w clocks.

Logically exclusive clocks :these are not actively used in the design at the
same time (e.g., multiplexed clocks),

• #setting uncertainties #we can also define different values for different
clocks with min and max values.
Set_clock_uncertanity –setup 0.10 [get_clocks –all]
Set_clock_uncertanity –hold 0.05 [get_clocks –all]

• #Setting input and output delays # for all Vclocks with min and max
Set_input_delay 1.0 [all_inputs] –vclk
Set_output_delay 1.0 [all_outputs] –vclk
 Cont…
• Set_driving_cell –[get_ports {all clocks}]
• Set_load 0.0024 [All_outputs]
# set_load says the max capacitance ur block will be driving.
#set_driving_cell says the cells at input ports.

• #design Rule Constraints

Set_max_transition 0.4 [current_design]
Set_max_fanout 20 [current_design]
Set_max_cap 0.6 [current_design] #optional

• #inter clock latencies # Latencies between same grp of clocks

• #clock exceptions
Set_false_paths –hold –from [get_clk vclk1] –to [get_clk scanclk]
Set_false_paths –setup –from[get_clk scanclk]–to [get_clk vclk1]
Set_multicycle_paths –setup 3 –from inst_cont/CK –to inst_cont/con1/D
 CLOCK SDC
• Set_clock_latency
• Set_clock_uncertanity
• Set_clock_transition
 False paths case analysis

False paths
• All Asynchronous paths

Case analysis:
• We can neglect some paths in timing.
 Design object Access command Description

1 design current_design A container for cells. A block.

2 clock1 get_clocks /all_clocks A clock in a design. All clocks in a design.

3 cell get_cells An instance of a design or library cell.

4 pin get_pins An instance of a design port or library cell pin.

5 Net get_nets A connection between cell pins and design ports

6 library get_libs A container for library cells

 Setup fixing
• DRC
– Tran (sizing /buffering)
– Cap (decrease net length/Cloaning)
– Fanout
By cell swapping (Lvt cells)
 Path Based Analysis
• PBA removes pessimism due to slew propagation. It takes
more run time. Paths which are difficult to close timing we
can use PBA.
• By default prime time takes worst time slew among the inputs
as the cell delay.
• Suppose in the case of a 3 input nand gate rise time delay of a
to y is 5ns and B to y is of 10ns and c to y is of 20ns Pt
considers C to Y as worst slew mode. But when recalculated
timing mode is enabled for a particular timing path actual
timing Arc’s delay is substituted. This may help in solving
setup issues.
• Usually this is enabled at the final Eco stage when all the ecos
are tapered out.
• command: report_timing –pba_mode exhaustive –from
ck/uff1 –to D/uff2
Thank You