Department of Electronics and Communication Engineering

SRINIVASA INSTITUTE OF ENGINEERING AND TECHNOLOGY

DESIGN AND IMPLEMENTATION OF 6

TRANSISTOR 2:1 MULTIPLEXER AND 1:2
DEMULTIPLEXER BY USING CPT LOGIC

Submitted by: Under the guidance of

G. Rishita (166N1A0481) Mr.B.N.Srinivasa Rao
K. Manoj (166N1A0487) M.Tech.,(Ph.D.,)
K. Ramya sri (166N1A0490) Associate professor
 ABSTRACT

CMOS logic circuits offer less power consumption, high speed,

easy to design and less area. Various techniques will be used to implement
the circuits for the same function. Further those techniques are performance
with reduced power consumption or optimization of any of the parameter
specifically. A trade-off between the parameters. Multiplexers and
demultiplexers play an important role in digital circuits, especially in bus
control circuitry. To select the appropriate bus. The proposed design will be
implemented the 2:1 multiplexer and 1:2 demultiplexer with less Transistors
by using the same CPT logic. The results will be compared with the
existing designs. The design will be implemented with tanner tool and will
be verified with H-spice simulator.
 INTRODUCTION

 The CMOS technology is used to construct the digital integrated

logic circuits.
 Implementation of architecture in CMOS its need large number of
transistors.
 PTL(pass transistor logic) is great tool to reduce the transistor count
without affecting the functionality.
EXISTING MODELS OF 2:1 MULTIPLEXER
 COMPARISION TABLE OF EXISTING MODELS
DESIGN NAME NUMBER OF AVERAGE TIME
TRANSISTORS POWER(milliwatts) DELAY(picosecond)
2:1 mux using 16 0.0361 0.03467
CPL LOGIC
2:1 mux using 16 0.4645 42.6561
EEPL logic
2:1 mux using 12 0.00245 14.9370
DCVSPG logic
2:1 mux using 14 0.02015 26.6768
SRPL logic
2:1 mux using 8 0.00191 35.451
CMOS
transmission
gates
2:1 mux using 7 0.33651 56.7606
LEAP logic
SCHEMATIC DIAGRAM OF PROPOSED 2:1 MULTIPLEXER
MODEL
OUTPUT OF PROPOSED MODEL 2:1 MULTIPLEXER

Avg. Power Consumption:0.0004758mw

Delay Time:53.0405psec
SCHEMATIC DIAGRAM OF PROPOSED 1:2 DEMULTIPLEXER
MODEL
OUTPUT OF PROPOSED MODEL 1:2 DEMULTIPLEXER

Power consumption: 0.0002946mw

Time delay: 38.4668 psec

 SOFTWARE TOOLS

Schematic design-Tanner
Design verification H-spice
Result Browser
Schematic design-tanner

HSPICE Verification tool

RESULT BROWSER
 CONCLUSION

By Considering the above mention parameters for all the existing
models the proposed system has less transistor count, Area, power
dissipation, Average power consumed in various models of 2:1
multiplexers and 1:2 demultiplexers circuits.
THANK YOU