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Low Area – High Speed – Energy Efficient One Bit Full Subtractor With
MTCMOS

Article · June 2015

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International Journal of Applied Engineering Research
ISSN 0973-4562 Volume 10, Number 11 (2015) pp. 27593-27604
© Research India Publications
http://www.ripublication.com

Low Area – High Speed – Energy EfficientOne Bit Full

SubtractorWithMTCMOS

1
M. MahaboobBasha, 2Dr. K. VenkataRamanaiah, 3Dr. P. Ramana Reddy
Associate Professor, Dept. of E.C.E, AVR SVR CET, JNTUA Nandyal, Kurnool (Dt.),
A.P, India.
Associate Professor, Dept. of E.C.E, YSR Engineering College of Y.V.U, Proddatur,
Y.S.R (Dt.) A.P., India.
Professor, Dept. of E.C.E, JNTUA College of Engineering, Kalikiri, Chittoor (Dt.),
A.P.,India.
E.Mail Id:- mmehboobbasha@gmail.com, ramanaiahkota@gmail.com,
prrjntu@gmail.com.

Abstract
As the technology goes down into the nanoscale domain, static or leakage
power consumption becomes an important parameter.In this paper a lower
area - energy efficient 10T 1-bit Full Subtractor has been designed. To reduce
the leakage current MTCMOS technique is applied for the proposed circuit
and have been analyzed by using Microwind 3.1 VLSI CAD tool.The
designed one bit Full Subtractor consists of two XOR gates and one
multiplexer. Various parameters such as area, delay, power dissipation and
PDP have been determined from Subtractor layout of feature size 65nm
technology. The Simulated parameters of proposed one bit Full Subtractor
compared with conventional, 20T and 14T one bit Full Subtractors.

Keywords: 10T One-bit Full Subtractor, Low area, High Speed, MTCMOS,
Low Leakage, Low Power.

Introduction
In Today’s, VLSI Digital Circuits low power consumption, less chip area and high
performance are the major concern. A Subtractor is a digital circuit that performs
subtraction between two binary numbers and which is one among the four basic
binary operations. In most of the digital systems there is a requirement for calculating
addresses, table indices frequently in some parts of processor which can be perfomed
by a subtractor. Integration and Differentiations are the two important mathematical
operations which can be performed frequently in analog circuits where as in digital
27594 M. MahaboobBasha

circuits, integration is similar to summation and differentiation is analogous to

Subtraction.
Unlike OR gate for addition, there is no direct subtractor gate for the subtraction of
two binary numbers in digital circuits.One method to perform subtraction between
two binary numbers is take the complement of subtrahend and add to the minuhend
then the result is subtraction.Another method is with logic gates by name Ex-OR gate,
AND gate, OR gate and inverter. Design of conventional one bit Full Subtractor with
above logic gates require more number of transistors which in turn increase the chip
area, power consumption and cost of the device.The system reliability can be
increased by reducing chip size, area and cost of the device.So the number of
transistors used in the portable devices must be less to consume less power and area.
In this work one bit Full Subtractor with two Ex-OR gates and one multiplexer has
been designed.The number of transistor count is reduced without compromising its
logical functionality.The Power consumption is reduced by reducing the leakage
currentwith MTCMOS technique. Section-II describes the previous work.The
proposed 1-bit Full Subtractor is described in Section-III. Section-IV presents the
simulation resultsof previous work with proposed 1-bit Full Subtractor. Section-
Vconcludes this paper.

Previous Work

A. Conventional Full Subtractor:

A basic Complementary Metal Oxide Semiconductor gate is a mixture of two
networks, one is pull up and another is pull down network. The pull up network which
is constructed using PMOS devices andthe pull-down network is constructed using
NMOS devices as shown in Fig.1. The primary reason for this choice is that NMOS
transistors produce “strong zeroes” and PMOS devices generate “strong ones”. The
function of the pull up network is to establish a connection between the
outputandsupply voltage (VDD) anytime the output of the logic gate is meant to be 1
(based on the inputs).
Similarly the function of the pull down network is to connect the output to ground
(VSS) when the output is meantto be 0. Static logic retainsits output levelas long as the
power is applied. Generally outputs are generated in response to input voltage levels
after a certain time delay. In static logic design, any combinationaldesign
willpossessan equal number of PMOS and NMOS transistors.[1],[2].
Low Area – High Speed – Energy Efficient One Bit Full Subtractor With et. al. 27595

Figure 1: StaticCMOS Circuit

Conventional Full Subtractor is a combinational logic circuit which performs

subtraction between two bits. The left significant bit have been borrowed by a
successive right significant bit. This is a three inputs and two output circuit. i.e., A, B
and C which denote minuend, subtrahend and previous borrow respectively.

Figure 2:Transistor Level Circuit of Conventional Full Subtractor

The two outputs are Difference and Borrow, respectively. The transistor level circuit
of Full Subtractor is shown in above Fig.2 and Table I reflect the logic outlined in
truth table [3].

Table 1: Truth Table of Full Subtractor

INPUTS OUTPUTS
A B C Difference(DOUT) Borrow(BOUT)
0 0 0 0 0
0 0 1 1 1
27596 M. MahaboobBasha

0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Where A, B, C inputs and Difference, Borrow are outputs.

B. 20 T Full Subtractor:
Fig. 3 shows the transistor level circuit diagram of Full Subtractor with twenty
transistors. As it has less transistor count when compared to Conventional Full
Subtractor it occupies less area, consumes less power and has low leakage current.
Here six transistors used for implementing difference equation and ten transistors for
borrow equation while rest of four transistors for inverting operation.

Figure 3:20T Full Subtractor

C. 14TFull Subtractor
Fig. 4 shows the transistor level circuit diagram of 14T 1-Bit Full Subtractor. The
modules of six transistors XNOR - XOR produce two intermediate signals which are
passed to the 2x1 MUX. The two intermediate signals produce by the above logic
gates act as input to the 2x1 MUX and third input acts as selection line for the
multiplexer. Difference between the inputs A, B and C is obtained from the output of
multiplexer. The Borrow is obtained from two AND gates and one OR gate.[4].
Low Area – High Speed – Energy Efficient One Bit Full Subtractor With et. al. 27597

Figure 4: 14T 1-bit Full Subtractor

D. 20T And 14TFull Subtractor With MTCMOS

In modern VLSI designs high performance and low-power are the major
requirements. In this paper for the designed one – bit Full Subtractor a technique by
name MTCMOS have been applied. This technique uses different threshold voltages
for designing a CMOS circuit [6]. Due to the scaling of threshold voltage, a
subthreshold leakage current play vital role to degrade the performance of high power
chips. The Propagation delay in the critical path is reduced with low-threshold (Vtl)
transistors and power consumption is reduced with High-threshold (Vth) transistors in
shortest path. The multi threshold CMOS technology has two main parts. First part of
MTCMOS Technique associate with “active” and “sleep” operational modes for
efficient power management. Second part is associated with applying two different
threshold voltages for NMOS and PMOS in a single chip. Schematic of 20T and 14T
1-bit Full Subtractor with MTCMOS is shown in Figures - Fig 5 and Fig.6.[7], [8].

Figure 5: 20T Full Subtractor with MTCMOS

27598 M. MahaboobBasha

Figure 6: 14T one-bit Full Subtractorwith MTCMOS

Proposed Work
The circuit of 10T Subtractor is a one-bit Full Subtractor core which has three inputs
(A, B, and C) and two outputs (Difference and Borrow). The Subtractor cell is made
of two XOR gates and one multiplexer. As sum and difference logics are same for
both full adder and Full Subtractor, the subtraction logic can be implemented with two
XOR gates where asthe borrowis obtained with multiplexer. The output of first XOR
gate is considered asaselection line for multiplexer to pass the logic value.The logics
B and C act as inputs for the multiplexer.Gate level Logic diagram for the proposed 1-
bitFull Subtractor is shown in Fig.7, while the circuits with transistor for the proposed
XOR gate and multiplexer are shown in Fig.8 a) & b).The total transistor based circuit
diagram forthe proposed one -bit Full Subtractor shown in Fig. 9, and Fig.10 shows
the proposedFull Subtractor with MTCMOS.

Figure 7: Logic Circuit of 10T one-bit Full Subtractor

Low Area – High Speed – Energy Efficient One Bit Full Subtractor With et. al. 27599

Figure 8: a) 4 T Xor Logic, b) 2:1 Mux

Figure 9:Proposed 10T one-bit Full Subtractor

Figure 10:10T one-bit Full Subtractor with MTCMOS

27600 M. MahaboobBasha

Simulation Results
The different types of Subtractor circuits have been simulated by using Microwind 3.1
VLSI CAD tool in 65nm technology [5]. The Proposed Full Subtractor circuit with
and without MTCMOS technique have been analyzed using BSIM 4 Parameter
analyzer. Reduction in Power, area, delay, power delay product and transistor count is
tabulated in table- II, III.
Fig.11 depicts the layout of proposed Full Subtractor, Fig.12 represents power output
waveform(V Vs T), Fig.13 shows the responses between Voltage Vs Current, whereas
Fig.14, Fig.15, Fig.16 and Fig.17 shows Id versus Vd characteristics of nMOS and
pMOS devices in Low Leakage and High Speed modes at room temperature.

Figure 11: Layout of Proposed 10T MTCMOS Full Subtractor

Figure 12: Waveform of Proposed 10T MTCMOS Full Subtractor (V vs T)

Low Area – High Speed – Energy Efficient One Bit Full Subtractor With et. al. 27601

Figure 13: Waveform of Proposed 10T MTCMOS Full Subtractor (V vs I)

Figure 14:Id/Vd characteristics ofnMOS devices in Low Leakage mode at room

temperature

Figure 15:Id/Vd characteristics ofpMOS devices in Low Leakage mode at room

temperature
27602 M. MahaboobBasha

Figure 16: Id/Vd characteristics ofnMOS devices in High Speed mode at room
temperature

Figure 17: Id/Vd characteristics ofpMOS devices in High Speed mode at room
temperature

Table 2:Simulation ResultsOf Various Types OfFull Subtractor In 65NM/27oC

TECHNIQUES AREA POWER DELAY PDP

(µm2) in (µw) in (ps) VALUE(µw X
ns)
CONVENTIONAL 864 85.037 188 15.98
FULL SUBTRACTOR
20T 280 71.533 151 10.80
20T MTCMOS 416 26.821 255 6.839
14T 175 20.433 117 2.390
14T MTCMOS 240 1.896 131 0.248
10T 154 25.126 110 2.763
10T MTCMOS 216 1.823 122 0.224
Low Area – High Speed – Energy Efficient One Bit Full Subtractor With et. al. 27603

Table 3:Transistors Required For ImplementingFull Subtractor

No.of MOS Transistors PMOS NMOS TOTAL

Conventional Full Subtractor 20 20 40
20T 10 10 20
20T MTCMOS 12 12 24
14T 7 7 14
14T MTCMOS 9 9 18
10T 5 5 10
10T MTCMOS 7 7 14

Graphical Analysis In Cmos 65 Nm Technology

Conclusion
This paper concludes that one – bit Full Subtractor with 10 transistor is better in terms
of area, delay, power and Power Delay product as compared to conventional, 20T,
14T with MTCMOS technique.In the Proposed design the number of transistor count
is reduced which in turn reduce the area, delay andphysical size of the
device.Therefore, the proposed 10T one bit Full Subtractorat 65nm technology is
Energy Efficient as it`s PDP value is less.
 27604 M. MahaboobBasha

References
[1] Neil Weste and D. Harris, “CMOS VLSI Design: A Circuit and System
Perspective,” Pearson Addition Wesley, third Edition, 2005.
[2] Ken Martin, Digital Integrated Circuit Design, Oxford University Press,
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[3] CMOS Digital Integrated Circuits Analysis and Design Third
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[4] Pranshu Sharma, Anjali Sharma, Richa Singh, “Design and analysis of
Area and Power Efficient 1-Bit Full Subtractor using 120nm Technology”,
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[5] Microwind and Dsch v3.1 – Lite User’s Manual – Etienne Sicard.
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[10] M. Mahaboob Basha, Towfeeq Fairooz, Nisar Hunadewale, K. Vasudeva
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[11] M.Mahaboob Basha, Dr. K.Venkata Ramanaiah, Dr. P.Ramana Reddy,
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