Implementation of

Low Power VLSI Architecture of MUX and DE-MUX

by
Y. CHARANYA REDDY(160120735006)
K. SAI BHAVYA(160120735019)

B.E(Electronics and Communication Engineering)

Under the Guidance of

Dr. B. Khaleelu Rehman(Associate professor, Dept. of ECE)
Chaitanya Bharathi Institute of Technology(A)
Hyderabad-500075
 AIM:
• To implement low power VLSI architecture of 2:1
Multiplexer and Demultiplexer using Adiabatic Logic with
the help of Cadence Virtuso tool using 180 nm technology.
 OBJECTIVES:

Gained knowledge on the Cadence Virtuso tool of 180 nm

technology.
Implementation of different ways of a circuit in regards of
various parameters(power,area,delay).
Circuit comes up with less power consumption and delay
parameters when compared with the most widely used
Conventional Logic Design.
Reduction of number of components used.
 LITERATURE SURVEY

S.NO TITLE YEAR TYPE KEY FINDINGS

1. High Performance VLSI 2021 Conference Power consumed in adiabatic

Architecture of MUX logic is less compared to
and DE-MUX using Conventional CMOS
Adiabatic Logic

2. Area and Power 2016 Conference Understood the concept of

Analysis of Adiabatic implementation of Adiabatic
2x1 Mux Design Logic
2x1 MULTIPLEXER LOGIC
2:1 MULTIPLEXER USING CONVENTIONAL
LOGIC
2:1 MULTIPLEXER USING ADIABATIC LOGIC
1:2 DE-MULTIPLEXER LOGIC
1:2 de-MULTIPLEXER USING CONVENTIONAL
LOGIC
1:2 de-MULTIPLEXER USING ADIABATIC LOGIC
CONVENTIONAL 2:1 MULTIPLEXER OUTPUT WAVEFORMS
ADIABATIC 2:1 MULTIPLEXER OUTPUT WAVEFORMS
CONVENTIONAL 1:2 DE-MULTIPLEXER OUTPUT
WAVEFORMS
ADIABATIC 1:2 DE-MULTIPLEXER OUTPUT WAVEFORMS
POWER CONSUMPTION OF 2:1 mux of BOTH CIRCUITS AT 40n s

CMOS 2:1 MUX ADIABATIC 2:1 MUX

power=1.971 nW power= 0.901 nW
 Delay comparison

CMOS 2:1 MUX ADIABATIC 2:1 MUX

delay: 329.56 ps delay:19.10 ns
POWER CONSUMPTION OF 1:2 de-mux of
BOTH CIRCUITS AT 40n s

CMOS 2:1 MUX ADIABATIC 2:1 MUX

power=1.971 nW power= 0.901 nW
 DELAY COMPARISON

CMOS 1:2 DE-MUX ADIABATIC 1:2 DE-MUX

delay: 10.37 ns delay: 0.258 ns
 CONCLUSION

 Learnt to work on one of the real time tool, Cadence

which is used for the implementation of Integrated
Circuits.
 Analysed the basic circuit and implemented it with
different logic to overcome major concerned drawbacks
“Power consumption” and delay reduction.
 Multiplexer and de-multiplexer design and
implementation is achieved with better performance.
THANK YOU!