Implementation of Modified Array

Multiplier for WiMAX Deinterleaver

Address Generation

Patil Nikita, Arun Kakhandki, S. Ramakrishna and Priyatam Kumar

Abstract One of the simpler techniques, which involve the implementation of gen-
erating the address of two-dimensional deinterleaver used in the WiMAX transmitter
and receiver block is proposed using the Xilinx FPGA. The Arithmetic and Logic Unit
performs various mathematical operations such as addition, subtraction, division and
many other logical operations. Apart from these operations, Multiplication is one of
the most fundamental operations to be carried out by this unit. The implementation
of multipliers is required for the address generation of the channel interleaver. The
multipliers need to be designed in such a way that they require high speed, low power,
less area, and less delay, which is of significant interest in the research area. Many
attempts have been carried out to reduce the generation of number of partial products
in the process of multiplication. Array multiplier is one such multiplier. Most of the
arithmetic operations will be performed using multipliers which consume the major-
ity amount of the power in digital circuits. The process of multiplication involves
the shift and add operations. The performance of multiplier can be improved by
optimizing the adder circuit. The objective of this paper is to build the algorithm for
generating the address of channel deinterleaver by using modified array multiplier.
The algorithm is built using the Hardware Description Language Verilog and the
functioning of the system can be verified through simulation and implemented using
the Spartan-6. The simulation and implementation results have been obtained for the
three different modulation techniques such as QPSK, 16-QAM, and 64-QAM for
some of the information rates which proves to be a very good technique against the
conventional methods.

Keywords Field-programmable gate array (FPGAs) · Multiplication · Array

multiplier

P. Nikita · S. Ramakrishna · P. Kumar (B)

Department of EC, BVB College of Engineering, Hubli 580031, India
e-mail: priyatam@bvb.edu
S. Ramakrishna
e-mail: ramakrishnasj444@gmail.com
A. Kakhandki
Department of EC, VDRIT College of Engineering, Haliyal 581329, India

© Springer Nature Singapore Pte Ltd. 2019 629

N. R. Shetty et al. (eds.), Emerging Research in Computing, Information, Communication
and Applications, Advances in Intelligent Systems and Computing 882,
https://doi.org/10.1007/978-981-13-5953-8_52
630 P. Nikita et al.

1 Introduction

Wireless Communication refers to the type of communication in which the data can
be transmitted, as well as received through wirelessly. Accessing the data through
wireless communication with large rate of bandwidth is one of the more competing
tasks compared to the wired communication technology. There are certain standards
given by IEEE for carrying out the wireless mobile communication which is widely
known as mobile WiMAX [1]. The channel interleaver/deinterleaver included in
the WiMAX Tx and Rx block plays a very important role in reducing the effect of
contiguous sequence of symbols that result in errors. The address generator circuit is
designed and implemented for the channel deinterleaver which is used in the WiMAX
Tx and Rx in such a way that requires high speed and less resources. The circuit is
designed with low complexity, as well as it invalidates the necessity of generating
floor function. There is a very small amount of work performed on the hardware
implementation part of the interleaver/deinterleaver used in a WiMAX system as
discussed in the literature review [2, 3].
In [4], the authors have described and demonstrated about grouping the incoming
data streams in the form of blocks to minimize the occurrence of accessing the
memory in a deinterleaver using a traditional LUT-based approach. The work is
realized by using Complementary Metal–Oxide–Semiconductor address generator
for WiMAX. In [5], the authors have carried out the work by implementing the
address generator for IEEE 802.16e channel interleaver with only a ½ code rate by
using a hardware description language. In [6], the authors have demonstrated with
the help of FSM-based address generator of the same interleaver for the different
information rates and modulation techniques. The authors of [5, 6] have implemented
on the FPGA platform. The authors of [7] have performed the two-dimensional
transformation of the functions which are used in the WiMAX channel deinterleaver
for using the hardware architecture efficiently. But the design issues have not been
discussed clearly for 64-QAM [8].
Implementation of the floor function in the hardware circuit is very complicated
since it requires more amount of resources [7]. One of the traditional techniques,
which were used previously, is the look up table-based approach. This technique
proved to be less efficient since it performed the operations slowly, utilization of
large amount of logic resources, and so on. The proposed design provides the impro-
visation with respect to the resources, operations to be carried out by the system com-
pared to the conventional look up table approach. Complex and lengthy expressions
were used for the modulation techniques, due to the two-dimensional transformation
of the functions used in the WiMax channel deinterleaver. The proposed system uses
the minimized mathematical expressions and the resulting algorithm is presented.
The mathematical equations have been proved using [7]. The proposed algorithm
can be realized with the help of hardware circuit, which results in the architecture for
address generation having less complexity, compared with the previous technique.
The design is optimized in such a way that it requires a common hardware circuit
among the modules for all the three modulation techniques [9]. The three modulation
Implementation of Modified Array Multiplier for WiMAX … 631

techniques that have been used are QPSK, 16-QAM, and 64-QAM. The proposed
algorithm consists of implementation of modified array multiplier, which helps in
the reduction of power along with less area and improving the delay of circuit. This
architecture is developed using hardware description language Verilog and imple-
mented on the Spartan-6 FPGA. The proposed algorithm is intended to produce the
address generated by the channel interleaver and the functioning of the hardware
circuit is verified using Isim.

2 Design Methodology

This section describes about the overview of WiMAX transreceiver and proposed
algorithm.

2.1 WiMAX System

Due to the advancement in the field of wireless communication technology, WiMAX

is one of the most emerging technologies that provide accessing for fixed and mobile
users. The overview of WiMAX transmitter and receiver block is shown in Fig. 1.
As seen in the below figure, the most important blocks of WiMAX are transmitter
and receiver in order to transmit as well as receive the data wirelessly.
The description of the transmitter section is as follows. Source is one of the most
important parts of the transmitter. It is used to transmit the information or data through
the channel to one or more receivers. The data received from the source is sent to
the randomizer. This operation is usually carried out for a certain set of data that can
be transmitted or received in a cyclic manner. This operation is performed on each

Fig. 1 Overview of WiMAX transreceiver

632 P. Nikita et al.

burst on each allocation in order to avoid lengthy sequence of continuous logical

ones and zeros. Data is further encoded by using both the coding techniques. The
coding techniques used are RS and CC. The encoded data is further applied to the
channel interleaver [10, 11]. The channel interleaver performs the permutation on
the encoded data to minimize the consequence of continuous sequence of symbols
which results in errors. The signals are further modulated and composed using the
other two consecutive blocks, such as mapper and inverse fast Fourier transformation
technique as shown in Fig. 1. The receiver block consists of the arrangement of the
blocks in the bottom-up approach so that it enables the data to be restored in the
elementary sequence at the output.
The functional representation of interleaver/deinterleaver is shown in Fig. 2. It pro-
vides the internal structure of the channel interleaver/deinterleaver in the WiMax sys-
tem. The channel interleaver/deinterleaver plays a very important role in the WiMAX
system. It consists of two memory blocks, multiplexers, and an address generator.
The read and write operations are performed by the memory blocks depending upon
the select lines. The data is written into the first memory block (M-1) when select
line is selected as one. The read operation is performed on the interleaved data from
the second memory block (M-2). Thus, read and write operations are performed
simultaneously on the memory blocks depending on the status of select lines. Once
the data is read/written up to the specified location as mentioned by the depth of
interleaver, the position of the select signal will be switched to alter the read as well
as write operations.
The interleaver/deinterleaver block accommodates distinct depth rates to include
different information rates and modulation schemes for IEEE 802.16e. The data

Fig. 2 Functional representation of interleaver/deinterleaver

Implementation of Modified Array Multiplier for WiMAX … 633

which is encoded with the help of coding techniques is processed by using the
Eqs. (1) and (2) which are noted below.
   
X cbps k
nk  · (k%m) + (1)
m m
    
nk m · nk
pk  r · + nk + X cbps − %r (2)
r X cbps

As seen in the above equations, m represents the number of columns. Here, it is

considered as (m  16/12 for WiMAX); the values of nk and pk, which are considered
as the result obtained as soon as encoding of data is performed. The value of k as seen
in the above equation can range from 0 to X cbps − 1; r is given by r  X cpc /2; basically
fixed for different techniques. It can be considered as two, four, or six for QPSK,
16-QAM, or 64-QAM, respectively. The inverse operation which is performed by
the deinterleaver is also defined by the equations which are mentioned below. The
values of np and kp represent the permutations obtained for the deinterleaver, where
p is considered as the index value of the bits received within a block of X cbps bits.
 p  
m.p

np  r . + p+ %r (3)
r X cbps
 
 m . np
kp  m . np − X cbps − 1 . (4)
X cbps

Table 1 discusses about the depth of interleaver/deinterleaver for various infor-

mation rates with modulation techniques.

Table 1 Addresses determined for channel interleaver

Row No. (p) Column No. (i) 0 1 2 3 4
0 X cbps  96 bits, ½ code rate, 0 16 32 48 64
1 QPSK 1 17 33 49 65
2 2 18 34 50 66
3 3 19 35 51 67
0 X cbps  192 bits, ½ code rate, 0 16 32 48 64
1 16-QAM 17 1 49 33 81
2 2 18 34 50 66
3 19 3 51 35 83
0 X cbps  192 bits, ½ code rate, 0 16 32 48 64
1 64-QAM 17 33 1 65 81
2 34 2 18 82 50
3 3 19 35 51 67
634 P. Nikita et al.

2.2 Proposed Algorithm

The mathematical analysis for generating the address using address generator for
the WiMAX deinterleaver has been shown in the above equations. The value of m is
chosen as 16. The number of rows (p) is predetermined which are equal to m for all
the various rates of interleaver depth which are in bits. The number of columns (i) is
obtained by dividing the interleaver depth by m. The equations used for generating
the addresses for all the three modulation techniques are as follows.

kn , Q P S K  m ∗ i + p for all the values of p and i (5)

⎫
m ∗i + p for p%2  0 and for i ⎬
kn , 16 − QAM  m ∗ (i + 1) + p for p%2  1 and for i%2  0 (6)
⎭
m ∗ (i − 1) + p for p%2  1 and for i%2  1
⎫
m ∗i + p for p%3  0 and for i ⎪
⎪
⎪
m ∗ (i − 2) + p for p%3  1 and for i%3  2 ⎪⎪
⎬
kn , 64 − QAM  m ∗ (i + 1) + p for p%3  1 and for i%3  2 (7)
⎪
m ∗ (i + 2) + p for p%3  2 and for i%3  0 ⎪⎪
⎪
⎪
m ∗ (i − 1) + p for p%3  2 and for i%3  0 ⎭

As seen in the Eqs. (5), (6), and (7), p considers the values from 0, 1, …, m
− 1 and i considers the values from 0, 1, …, (X cbps /m) − 1 represents the row
and column numbers, respectively, and k n represents the addresses of deinterleaver.
Using the above Eqs. (5), (6), and (7), the addresses have been determined for all the
three modulation schemes. Table 2 shows the addresses determined for all the three
modulation techniques with code rates.
The algorithms can be further transformed into the circuits as shown in Figs. 3
and 4, respectively. The hardware circuit for the Quadrature Phase Shift Keying is
shown in Fig. 3. It consists of various blocks such as row counter, comparator, column
counter, and multiplexer. The row counter initiates with generating the row numbers
between 0 and m − 1. The column counter which is built along with the Mux M0

Table 2 Depth of interleaver/deinterleaver for various information rates with modulation tech-
niques
Modulation scheme QPSK (s  1) 16-QAM (s  64-QAM (s  3)
2)
Code rate 1/2 3/4 1/2 3/4 1/2 2/3 3/4
Interleaver depth, X cbps in bits 96 144 192 288 288 384 432
192 288 384 576 576 – –
288 432 576 – – – –
384 576 – – – – –
Implementation of Modified Array Multiplier for WiMAX … 635

Fig. 3 Hardware structure of QPSK

Fig. 4 Hardware structure of 16-QAM and 64-QAM

and comparator C0 is used for generating the column numbers to implement the
allowable coded bits per second termed as X cbps . The multiplier and an adder unit
are used to perform the required operations to produce the value of k n (address of the
deinterleaver). The hardware circuits for the 16-QAM and 64-QAM are similar to
the circuit of the QPSK. The additional modules required for the design of 16-QAM
and 64-QAM are an incrementer, which increases the values by 1 and provides them
to the mux, an decrementer, which decreases the values by 1 and transmits them
to the mux, modulo blocks as shown in Figs. 4 and 5. The operation of modulo 2
is performed by the hardware circuit of 16-QAM and the operation of modulo 3 is
performed by the hardware circuit of 64-QAM as mentioned in the above part of the
Eqs. (6) and (7).
636 P. Nikita et al.

Fig. 5 Schematic structure

of deinterleaver address
generator

The Schematic structure of the complete deinterleaver address generator is shown

in Fig. 5. It consists of row counter (j), column counter (i), QPSK block, 16-QAM
block, 64-QAM block, and multiplexer. The multiplexer is used to select the mod-
ulation techniques depending upon the combination given to the select lines. The
combination of multiplier and adder units is used to generate the address for the
deinterleaver.

3 Simulation and Implementation Results

The functioning of the hardware circuit of the deinterleaver address generator is ver-
ified by programming using the Verilog with the help of Xilinx tool. The simulation
results have been obtained for all the three different modulation techniques using
Isim.
The simulation results obtained for the 16-bit modified array multiplier is shown
in Fig. 6. The results are generated for the six different combinations of data. This 16-
bit modified array multiplier is utilized in the hardware circuit of schematic structure
of deinterleaver address generator. The usage of modified array multiplier in this
circuit significantly reduces the power.
The simulation results obtained for the QPSK is shown in Fig. 7. The deinterleaver
address has been generated for the QPSK as shown in Table 2. The results have been
verified using Table 2.
The simulation results obtained for the 16-bit QAM is shown in Fig. 8. The
deinterleaver address has been generated for the 16-bit QAM as shown in Table 2.
The results have been verified using Table 2.
The simulation results obtained for the 64-bit QAM is shown in Fig. 9. The
deinterleaver address has been generated for the 64-QAM as shown in Table 2. The
results have been verified using Table 2.
Implementation of Modified Array Multiplier for WiMAX … 637

Fig. 6 Simulation results of 16-bit modified array multiplier

Fig. 7 Simulation results of QPSK

Fig. 8 Simulation results of 16-QAM

Fig. 9 Simulation results of 64-QAM

638 P. Nikita et al.

Table 3 Synthesis report of the proposed algorithm

Logic circuits Quantity
Adders/Subtractors 19
Counters 5
Registers 13
Comparators 21
Multiplexers 581

Table 4 Performance of the proposed algorithm with the existing algorithm

Different No. of registers No. of LUTs No. of bonded Max frequency
approaches IOs (MHz)
LUT-based 62 714 26 210.402
approach
16-bit modified 47 220 30 204.505
array multiplier

Fig. 10 Power analysis of the algorithm

The implementation details are discussed in Tables 3 and 4. Table 3 specifies

about the logic circuits required for the proposed algorithm and Table 4 specifies
about the performance of the proposed algorithm with the existing method. It shows
the comparison of parameters between the two different approaches. As per the com-
parison carried out between the two approaches, in terms of resources, the modified
array multiplier accommodates with less number of resources. The power analysis of
the algorithm is shown in Fig. 10. The dynamic power consumed is nearly 0.005 W
and the quiescent power consumed is nearly 0.020 W. The total amount of power
consumed is 0.025 W.

4 Conclusion

This paper represents the three different modulation techniques of address generation
using the 16-bit modified array multiplier. The proposed algorithm is transformed into
the hardware circuit for all three different modulation techniques. The results have
Implementation of Modified Array Multiplier for WiMAX … 639

been obtained using the Xilinx tool and implementation is performed using Spartan-6.
Thus, it is concluded that the address values for the channel interleaver/deinterleaver
are generated by using 16-bit modified array multiplier. The implemented results
discuss about the utilization of resources for the system. The comparison between the
two approaches such as LUT-based approach and by using modified array multiplier
is carried out in terms of resources and frequency. The power analysis is also carried
out for the system.

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