Es ZG626 Course Handout

BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI
WORK INTEGRATED LEARNING PROGRAMMES

Digital Learning
Part A: Content Design
Course Title HARDWARE AND SOFTWARE CO-DESIGN
Course No(s) AEL ZG626/ ES ZG626/MEL ZG651/SS ZG626/ SE ZG626
Credit Units 5
Credit Model Theory
Content Authors PAWAN SHARMA & PARESH JOSHI
Course Objectives
No
CO1 To provide an understanding of system-level design of embedded systems comprised of both

hardware and software
CO2 Introduction to hardware software implementation, Complex system modeling and simulation
CO3 To investigate topics such as Hardware Software partitioning, mapping and scheduling, Co-
simulation, synthesis and verification relevant to co-design
CO4 Introduction to hardware software partitioning and estimation, hardware software interfaces
CO5 To explore, analysis and optimization processes in support of algorithmic and architectural
design decisions; gain design experience with case studies using contemporary high-level
methods and tools.
Text Book(s)
T1 Daniel D Gajski, Frank Vahid, Sanjay Narayan, Jie Gong, Specification and Design of Embedded
Systems, Prentice Hall, 1994.
T2 Patrick R. Schaumont, A Practical Introduction to Hardware/Software Codesign, Springer, 2 nd
ed. 2013
Reference Book(s) & other resources

R1 Jorgen Staunstrup, Wayne Wolf, Hardware / Software Co-Design: Principles and Practice,
Kluwer Academic, 1997
R2 Peter Marwedel, Embedded System Design, Springer 2003
R3 G. DeMicheli, R. Ernst and W. Wolf, Readings in Hw/Sw Co-design, M. Kaufmann, 2002,
R4 Ahmed A. Jerraya and Jean Mermet eds.: System Level Synthesis, Kluwer 1999.
R5 Hardware/Software Codesign. G. DeMicheli and M. Sami (eds.), NATO ASI Series E, Vol. 310,
1996.
R6 Sanjaya Kumar, James H. Aylor, Barry W. Johnson, and Wm. A. Wulf. The Codesign of
Embedded Systems. Kluwer, 1995
R7 Proceedings of IEEE, IEEE Transactions, ACM Transactions
Content Structure
1. Introduction
1.1. Introduction to Embedded System Design
1.2. High Level Design
1.3. Introduction to Hardware/Software Codesign
1.4. Dualism of Hardware and Software designs
2. Specification and Modeling concepts
2.1. Concept of system modeling, Need for Concurrent Models,
2.2. State Oriented Models
2.2.1. FSM
2.2.2. Petri Net
2.2.3. HCFSM
2.3. Activity Oriented Models
2.3.1. DFG
2.3.2. Flowcharts
2.4. Structure Oriented Models
2.4.1. CCD
2.5. Data Oriented Models
2.5.1. Entity Relationship Diagram
2.5.2. Jackson’s Diagram
2.6. Heterogeneous Models
2.6.1. CDFG
2.6.2. Structure Chart
2.6.3. Programming Language Paradigm
2.6.4. PSM
2.6.5. Queuing Model
3. Modeling and implementation concepts
3.1. Analysis of Data Flow Graphs and Control Flow Graphs
3.2. Hardware Implementation and Software Implementation of Data Flow
3.3. Data and Control Edges of C Program
3.4. Translation C to Hardware
4. Introduction to Specification Languages
4.1. Characteristics of Conceptual Models
4.2. Survey of Specification Languages
4.2.1. System C or any other example can be considered
5. Architecture Taxonomy and Target Architecture
5.1. Application Specific Architectures
5.1.1. Controller Architecture
5.1.2. Datapath Architecture
5.2. Finite State Machine with Datapath (FSMD)
5.2.1. Simulation and Synthesis of FSMD
5.2.2. Language Mapping for FSMD
5.3. Microprogrammed Architectures
5.3.1. Microprogrammed Control
5.3.2. Microinstruction Encoding
5.3.3. Microprogrammed Datapath
5.3.4. Implementation
5.4. General Purpose Embedded Cores
5.4.1. CISC
5.4.2. RISC
5.4.3. Vector Machine
5.4.4. VLIW Computer
5.4.5. Parallel Processors
6. Hardware/Software Interfaces
6.1. System-on-Chip Concept
6.2. Connecting Hardware and Software
6.2.1. On-Chip Bus Systems
6.2.2. Bus Transfers
6.3. The Hardware/Software Communication
6.3.1. Synchronization schemes
6.3.2. Software/Microprocessor Interfaces
6.3.2.1. Memory-Mapped Interfaces
6.3.2.2. Coprocessor Interfaces
6.3.2.3. Custom Instruction Interfaces
6.4. Hardware Interface
6.4.1. Coprocessor Hardware Interface
7. System Partitioning
7.1. Partitioning Issues
7.2. Partitioning algorithms
7.3. Functional partitioning for Hardware
7.4. Hardware and Software Partitioning Algorithms
8. Hardware / Software Co-Synthesis
8.1. Introduction
8.2. Classification
8.3. Examples
8.3.1. Vulcan, Cosyma, SpecSyn, etc...
9. Design Quality Estimation
9.1. Quality Metrics
9.2. Hardware Estimation
9.3. Software Estimation
10. Recent Trends and Examples
Learning Outcomes:
No Learning Outcomes. Knowledge in the following areas
LO1 System modeling and simulation
LO2 hardware software implementation of complex systems
LO3 hardware software interfaces
LO4 hardware software partitioning and estimation techniques
LO5 hardware software co-synthesis
Part B: Learning Plan

Academic Term First Semester 2021-2022
Course Title HARDWARE AND SOFTWARE CO-DESIGN
Course No AEL ZG626/ ES ZG626/MEL ZG651/SS ZG626/ SE ZG626
Lead Instructor PAWAN SHARMA & PARESH JOSHI
Contact Hour 1
Type Content Ref. Topic Title Study/HW Resource Reference
Pre CH
During CH T1 Ch 1 Introduction to Embedded System

T2 Ch1 Design, High Level Design
Introduction to Hardware/
Software Codesign
Dualism of Hardware and Software
designs
Post CH
Contact Hour 2
Pre CH
During CH T1 Ch 2 Concept of system modeling, Need

T2 Ch1 for Concurrent Models
Post CH
Contact Hour 3
Pre CH
During CH T1 Ch2 State Oriented Models Petri Nets: Properties, Analysis and
R2 Ch2 FSM, Petri Net Applications by: Tadao MurataIn
Proceedings of the IEEE, Vol. 77, No.
4. (April 1989), pp. 541-580,
doi:10.1109/5.24143
Post CH
Contact Hour 4
Pre CH
During CH T1 Ch2 Petri Net Petri Nets: Properties, Analysis and

R2 Ch2 Applications by: Tadao MurataIn
Proceedings of the IEEE, Vol. 77, No.
4. (April 1989), pp. 541-580,
doi:10.1109/5.24143
Post CH
Contact Hour 5
Pre CH
During CH T1 Ch2 HCFSM or State Charts

R2 Ch2
Post CH
Contact Hour 6
Pre CH
During CH T1 Ch2 Activity Oriented Models, Data

T2 Ch2 Flow Graph
Post CH T1 Ch2 Flowcharts

Structure Oriented Models
CCD
Data Oriented Models
Entity Relationship Diagram
Jackson’s Diagram
Heterogeneous Models
CDFG, Structure Chart
Programming Language Paradigm
PSM, Queuing Model (Self study
components)
Contact Hour 7
Pre CH
During CH T2 Ch2 Analyzing Synchronous Data Flow

Graphs, Control Flow Modeling
and the Limitations of Data Flow
Models
Post CH
Contact Hour 8
Pre CH
During CH T2 Ch2 Adding Time and Resources, Data

Flow Transformations
Post CH
Contact Hour 9
Pre CH
During CH T2 Ch2 Data Flow Transformations
Post CH
Contact Hour 10
Pre CH
During CH T2 Ch3 Data Flow Implementation in

Software
Post CH
Contact Hour 11
Pre CH
During CH T2 Ch3 Data Flow Implementation in

Hardware
Post CH
Contact Hour 12
Pre CH
During CH T2 Ch4 Data and Control Edges of a C

Program, Implementing Data and
Control Edges, Construction of the
Control Flow Graph and Data Flow
Graph
Post CH
Contact Hour 13
Pre CH
During CH T2 Ch4 Construction of the Data Flow

Graph, Application: Translating C
to Hardware
Post CH
Contact Hour 14
Pre CH
During CH T1 Ch3 Introduction to Specification

Languages, Characteristics of
Conceptual Models, Survey of
Specification Languages
Post CH
Contact Hour 15
Pre CH
During CH -- System c or any other example
Post CH
Contact Hour 16
Pre CH
During CH -- System c or any other example
Post CH
Contact Hour 17
Pre CH
During CH T2 Ch5 Application Specific Architectures

T1 Ch2 Controller Architecture, Datapath
Architecture , Finite State Machine
with Datapath (FSMD)
Post CH
Contact Hour 18
Pre CH
During CH T2 Ch5 Simulation and Synthesis of FSMD

T1 Ch2 Language Mapping for FSMD
Post CH
Contact Hour 19
Pre CH
During CH T2 Ch6 Microprogrammed Architectures

Microprogrammed Control
Microinstruction Encoding
Microprogrammed Datapath
Implementation
Post CH T1 Ch2 General Purpose Embedded Cores

T2 Ch7 CISC
R1 Ch4 RISC
Vector Machine
VLIW Computer
Parallel Processors (self-study)
Contact Hour 20
Pre CH
During CH T2 Ch8, 10 System-on-Chip Concept

Connecting Hardware and
Software, On-Chip Bus Systems,
Bus Transfers
Post CH
Contact Hour 21
Pre CH
During CH T1 Ch9 The Hardware/Software

Communication, Synchronization
schemes
Post CH
Contact Hour 22
Pre CH
During CH T1 Ch11 Software/Microprocessor

Interfaces, Memory-Mapped
Interfaces
Post CH
Contact Hour 23
Pre CH
During CH T1 Ch11 Coprocessor Interfaces , Custom

Instruction Interfaces
Post CH
Contact Hour 24
Pre CH
During CH T1 Ch12 Hardware Interface

Coprocessor Hardware Interface
Post CH
Contact Hour 25
Pre CH
During CH T1 Ch6 Partitioning Issues, Partitioning

algorithms
Post CH
Contact Hour 26
Pre CH
During CH T1 Ch6 Partitioning Issues, Partitioning

algorithms
Post CH
Contact Hour 27
Pre CH
During CH T1 Ch6 Functional partitioning for

Hardware, Hardware and Software
Partitioning Algorithms
Post CH
Contact Hour 28
Pre CH
During CH T1 Ch6 Functional partitioning for

Hardware, Hardware and Software
Partitioning Algorithms
Post CH
Contact Hour 29
Pre CH
During CH T1 Ch 6 Hardware / Software Co-Synthesis

Introduction, Classification
Examples: Vulcan, Cosyma,
SpecSyn, etc...
Post CH T1 Ch 6 Examples: Vulcan, Cosyma,

SpecSyn, etc... (Self-Study)
Contact Hour 30
Pre CH
During CH T1 Ch7 Design Quality Estimation , Quality

Metrics, Hardware Estimation,
Software Estimation
Post CH
Contact Hour 31
Pre CH
During CH T1 Ch7 Design Quality Estimation , Quality

Metrics, Hardware Estimation,
Software Estimation
Post CH
Contact Hour 32
Pre CH
During CH -- Recent Trends and Examples
Post CH
Post CH
Laboratory Details:
Evaluation Scheme:
Legend: EC = Evaluation Component; AN = After Noon Session; FN = Fore Noon Session
No Name Type Duration Weight Day, Date, Session, Time
EC-1 Assignment-I Online - 10% February 14-24, 2022
Assignment-II Online - 10% March 14-24, 2022
EC-2 Mid-Semester Test Open Book 2 hours 30% Friday, 11/03/2022 (AN)
2 PM – 4 PM
EC-3 Comprehensive Exam Open Book 2 hours 50% Friday, 20/05/2022 (AN)
2 PM – 4 PM
Syllabus for Mid-Semester Test (Open Book): Topics in Session Nos. 1 to 14

Syllabus for Comprehensive Exam (Open Book): All topics (Session Nos. 1 to 32)
Important links and information:
Elearn portal: https://elearn.bits-pilani.ac.in
Students are expected to visit the Elearn portal on a regular basis and stay up to date with the latest announcements and
deadlines.
Contact sessions: Students should attend the online lectures as per the schedule provided on the Elearn portal.
Evaluation Guidelines:
1. EC-1 consists of either two Assignments. Students will attempt them through the course pages on the Elearn portal.
Announcements will be made on the portal, in a timely manner.
2. For Closed Book tests: No books or reference material of any kind will be permitted.
3. For Open Book exams: Use of books and any printed / written reference material (filed or bound) is permitted. However,
loose sheets of paper will not be allowed. Use of calculators is permitted in all exams. Laptops/Mobiles of any kind are
not allowed. Exchange of any material is not allowed.
4. If a student is unable to appear for the Regular Test/Exam due to genuine exigencies, the student should follow the
procedure to apply for the Make-Up Test/Exam which will be made available on the Elearn portal. The Make-Up
Test/Exam will be conducted only at selected exam centres on the dates to be announced later.
It shall be the responsibility of the individual student to be regular in maintaining the self study schedule as given in the course
handout, attend the online lectures, and take all the prescribed evaluation components such as Assignment/Quiz, Mid-Semester
Test and Comprehensive Exam according to the evaluation scheme provided in the handout.

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BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI

WORK INTEGRATED LEARNING PROGRAMMES

CO1 To provide an understanding of system-level design of embedded systems comprised of both

Reference Book(s) & other resources

LO1 System modeling and simulation

LO2 hardware software implementation of complex systems

LO3 hardware software interfaces

LO4 hardware software partitioning and estimation techniques

LO5 hardware software co-synthesis

Part B: Learning Plan

During CH T1 Ch 1 Introduction to Embedded System

During CH T1 Ch 2 Concept of system modeling, Need

During CH T1 Ch2 Petri Net Petri Nets: Properties, Analysis and

During CH T1 Ch2 HCFSM or State Charts

During CH T1 Ch2 Activity Oriented Models, Data

Post CH T1 Ch2 Flowcharts

During CH T2 Ch2 Analyzing Synchronous Data Flow

During CH T2 Ch2 Adding Time and Resources, Data

During CH T2 Ch2 Data Flow Transformations

During CH T2 Ch3 Data Flow Implementation in

During CH T2 Ch3 Data Flow Implementation in

During CH T2 Ch4 Data and Control Edges of a C

During CH T2 Ch4 Construction of the Data Flow

During CH T1 Ch3 Introduction to Specification

During CH -- System c or any other example

During CH -- System c or any other example

During CH T2 Ch5 Application Specific Architectures

During CH T2 Ch5 Simulation and Synthesis of FSMD

During CH T2 Ch6 Microprogrammed Architectures

Post CH T1 Ch2 General Purpose Embedded Cores

During CH T2 Ch8, 10 System-on-Chip Concept

During CH T1 Ch9 The Hardware/Software

During CH T1 Ch11 Software/Microprocessor

During CH T1 Ch11 Coprocessor Interfaces , Custom

During CH T1 Ch12 Hardware Interface

During CH T1 Ch6 Partitioning Issues, Partitioning

During CH T1 Ch6 Partitioning Issues, Partitioning

During CH T1 Ch6 Functional partitioning for

During CH T1 Ch6 Functional partitioning for

During CH T1 Ch 6 Hardware / Software Co-Synthesis

Post CH T1 Ch 6 Examples: Vulcan, Cosyma,

During CH T1 Ch7 Design Quality Estimation , Quality

During CH T1 Ch7 Design Quality Estimation , Quality

During CH -- Recent Trends and Examples

Syllabus for Mid-Semester Test (Open Book): Topics in Session Nos. 1 to 14

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