BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI

WORK INTEGRATED LEARNING PROGRAMMES

COURSE HANDOUT
Part A: Content Design
Course Title COMPUTER ORGANIZATION AND ARCHITECTURE
Course No(s) SEWP ZC353
Credit Units 4
1-1-2, (total 4 units or credits) ie 1 unit for class room hours, 1 unit for lab
hours, 2 units for student preparation.
Typically 1 unit translates to 32 hours
Course Author
Version No
Date September 2019

Course Objectives
No Objective

CO1 To understand the structure, function, organization and architecture of modern day computing
systems.

CO2 To learn the major components of a computer and their interconnections, both with each other
and the outside world with detailed discussion of internal and external memory and of input–
output (I/O) devices.

CO3 To examines the internal architecture and organization of the processor with an extended
discussion of computer arithmetic and the instruction set architecture.

CO4 To give an introduction of parallel organization, including symmetric multiprocessing, clusters,

and multicore architecture.

CO5 To learn the Hardware Description Language and simulator to design and verify the basic
components of a computing system.

Text Book(s)
T1 Stallings William, Computer Organization & Architecture, Pearson Education, 8th Ed., 2010.

Reference Book(s)
R1 C Hamacher, Z Vranesic and S Zaky, Computer Organization by McGrawHill, 5th Ed. 2002
R2 Hennenssy& D.A. Patterson, Computer Organization & Design, Morgan Kaufmann 4th Ed.,
2009
R3 The Essentials of Computer Organization and Architecture, Linda Null and Julia Lobur, Jones
and Bartlett publisher, 2003 [24x7 Online Book]
Modular Content Structure

1. Computer System Components and Interconnections

 1.1. Introduction
1.1.1. Organization and Architecture
1.1.2. Structure and Function
1.2. Computer Evolution and Performance
1.2.1. A Brief History of Computers
1.2.2. Designing for Performance
1.2.3. The Evolution of the Intel x86 Architecture
1.2.4. Performance Assessment
1.3. Top-Level View of Computer Function and Interconnection
1.3.1. Computer Components
1.3.2. Computer Function
1.3.3. Interconnection Structures
1.3.4. Bus Interconnection
1.3.5. PCI
2. Central Processing Unit - Computer Arithmetic
2.1. The Arithmetic and Logic Unit (ALU)
2.2. Integer Representation
2.3. Integer Arithmetic
2.4. Floating-Point Representation
2.5. Floating-Point Arithmetic
3. Instruction Set Architecture (8086 ARM as an example)
3.1. Instruction Sets: Characteristics and Functions
3.1.1. Machine Instruction Characteristics
3.1.2. Types of Operands
3.1.3. Intel x86 and ARM Data Types
3.1.4. Types of Operations
3.1.5. Intel x86 and ARM Operation Types
3.2. Instruction Sets: Addressing Modes and Formats
3.2.1. Addressing
3.2.2. x86 and ARM Addressing Modes
3.2.3. Instruction Formats
3.2.4. x86 and ARM Instruction Formats
3.2.5. Assembly Language
4. Cache Memory Organization
4.1. Computer Memory System Overview
4.2. Cache Memory Principles
4.3. Elements of Cache Design
5. Internal and External memory
5.1. Internal Memory Technology
5.1.1. Semiconductor Main Memory
 5.1.2. Error Correction
5.1.3. Advanced DRAM Organization
5.2. External Memory
5.2.1. Magnetic Disk
5.2.2. RAID
6. Input/Output Organization
6.1. I/O Modules
6.2. Programmed I/O
6.3. Interrupt-Driven I/O
6.4. Direct Memory Access
6.5. I/O Channels and Processors
7. Scalar and Super Scalar Instruction Pipeline
7.1. Processor Structure and Function
7.1.1. The Instruction Cycle
7.1.2. Instruction Pipelining
7.1.3. The ARM Processor
7.2. Reduced Instruction Set Computers
7.2.1. Instruction Execution Characteristics
7.2.2. The Use of a Large Register File
7.2.3. Reduced Instruction Set Architecture
7.2.4. RISC Pipelining
7.2.5. SPARC / ARM7TDMI
8. Micro-operations and Control Unit
8.1. Control Unit Operation - Micro-operations
8.2. Control of the Processor
8.3. Hardwired Implementation
8.4. Micro programmed Control - Basic Concepts
8.5. Microinstruction Sequencing
8.6. Microinstruction Execution
9. Multiprocessor Organizations
9.1. The Use of Multiple Processors
9.2. Symmetric Multiprocessors
9.3. Cache Coherence and the MESI Protocol
9.4. Multithreading and Chip Multiprocessors
9.5. Clusters
9.6. Non uniform Memory Access Computers

Learning Outcomes:
No Learning Outcomes
 LO1 To apply the knowledge of performance metrics to find the performance of systems.
LO2 To Build an assembly language program to program a microprocessor system.

LO3 To Investigate high performance architecture design for X86 system

LO4 To Examine different computer architectures and hardware

LO5 To design a hardware component for an embedded system

Part B: Contact Session Plan

Academic Term I Semester 2019 - 20

Course Title COMPUTER ORGANIZATION AND ARCHITECTURE
Course No SEWP ZC353
Lead Instructor

Glossary of Terms
1. Contact Hour (CH) stands for a hour long live session with students conducted either in a
physical classroom or enabled through technology. In this model of instruction, instructor led
sessions will be for 22 CH.
a. Pre CH = Self Learning done prior to a given contact hour
b. During CH = Content to be discussed during the contact hour by the course instructor
c. Post CH = Self Learning done post the contact hour
2. Contact Hour (CS) stands for a two-hour long live session with students conducted either in a
physical classroom or enabled through technology. In this model of instruction, instructor led
sessions will be for 11 CS.
a. Pre CS = Self Learning done prior to a given contact session
b. During CS = Content to be discussed during the contact session by the course
instructor
c. Post CS = Self Learning done post the contact session
3. RL stands for Recorded Lecture or Recorded Lesson. It is presented to the student through an
online portal. A given RL unfolds as a sequences of video segments interleaved with
exercises
4. SS stands for Self-Study to be done as a study of relevant sections from textbooks and
reference books. It could also include study of external resources.
5. LE stands for Lab Exercises
6. HW stands for Home Work.
7. M stands for module. Module is a standalone quantum of designed content. A typical course
is delivered using a string of modules. M2 means module 2.

Teaching Methodology (Flipped Learning Model)

The pedagogy for this course is centered around flipped learning model in which the traditional class-
room instruction is replaced with recorded lectures to be watched at home as per the student’s
convenience and the erstwhile home-working or tutorials become the focus of classroom contact
sessions. Students are expected to finish the home works on time.
 Contact Session Plan
o Each Module (M#) covers an independent topic and module may encompass more
than one Recorded Lecture (RL).
o Contact Sessions (2hrs each week) are scheduled alternate weeks after the student
watches all Recorded Lectures (RLs) of the specified Modules (listed below) during
the previous week
o In the flipped learning model, Contact Sessions are meant for in-classroom
discussions on cases, tutorials/exercises or responding to student’s
questions/clarification--- may encompass more than one Module/RLs/CS topic.
o Contact Session topics listed in course structure (numbered CSx.y) may cover several
RLs; and as per the pace of instructor/students’ learning, the instructor may take up
more than one CS topic during each of the below sessions.

Detailed Structure
Introductory Video/Document: << Introducing the faculty, overview of the course,
structure and organization of topics, guidance for navigating the content, and expectations
from students>>

 Each of the sub-modules of Recorded Lectures (RLx.y ) shall delivered via 30 –

60mins videos followed by:
 Contact session (CSx.y) of 2Hr each for illustrating the concepts discussed in the
videos with exercises, tutorials and discussion on case-problems (wherever
appropriate); contact sessions (CS) may cover more than one recorded-lecture (RL)
videos.

Course Contents

Contact Hour 1
Time Type Description Content Reference

Pre CH RL1.1 Computer Organization and Architecture, T1 – 1.1, 1.2

Functional and Structural View of Computer
System, Brief History of Computers, Evolution
of Intel x86 Architecture

RL1.2 Concept of Computer Program and Instruction, T1 – 2.1, 2.2

Internal Structure of CPU, Instruction Execution
Cycle With and Without Interrupt

During CH CH1 CH1.1 =A brief summary of recorded lectures,

CH1.3 =T1: IAS Computer Architecture (Page
No. 37-42)

Post CH SS1 T1: Section 2.1, 2.2

HW1 T1: Problem 2.10, 3.4, 3.12, 3.16;

LE1 NA
 QZ1

Lab Reference

Contact Hour 2
Time Type Description Content Reference

Pre CH RL1.3 Computer Performance Assessment, CPI, MIPS T1- 2.3, 2.5, 3.1 to 3.3
Rate, Benchmark Programs

RL1.4 Computer System Modules and T1 – 3.4, 3.5

Interconnections; Concept of BUS: Types,
Arbitration, Timing; PCI BUS Operation

During CH CH2 Text Book Problem solving on MIPS, CPI

Post CH SS2 R2: Section 1.2

HW2 R2: Exercise 1.3, 1.4

LE2 NA

QZ2

Lab Reference

Contact Hour 3
Time Type Description Content Reference

Pre CH RL2.1 Arithmetic and Logic Unit, Integer T1 – 9.1 to 9.3

Representation, Integer Arithmetic: Addition,
Subtraction, Multiplication, Division

During CH CH3 CH3.1 =A brief summary of recorded lectures

CH3.2 =T1: Section 9.3 (in summarized form),
CH3.3 =, R2: Example on Page 236-237, 241-
242

Post CH SS3 T1: Section 9.1,

HW3 T1: Problem 9.14, 9.20, 9.38;

LE3

QZ3

Lab Reference

Contact Hour 4

Time Type Description Content Reference

Pre CH RL2.2 Floating Point Representation, IEEE-754
Standard, FP Arithmetic: Addition, Subtraction,
Multiplication and Division, Precision
Consideration: Rounding & Guard Bits, De-
normalized Numbers

During CH CH4 Text Book Problem Solving on floating point

numbers

Post CH SS4 Slides on Verilog Programming

HW4 R1: Problem 6.1, 6.25, 6.26

LE4 NA

QZ4

Lab Reference

Contact Hour 5
Time Type Description Content Reference

Pre CH RL3.1 Elements of Instruction Set Architecture (ISA), T1 – 10.1 to 10.5

Instruction Formats, Instruction Design Issues,
Programming Model of 8086, Addressing
Modes: Register, Direct, Immediate

During CH CH5 CH5.1 =A brief summary of recorded lectures,

CH5.2 =T1: Problem Solving

Post CH SS5 R1: Section 3.16 to 3.20

HW5 T1: Problem 11.1, 11.5,

LE5

QZ5

Lab Reference

Contact Hour 6
Time Type Description Content Reference

Pre CH RL3.2 Instruction Addressing Modes: Indirect T1 – 11.1, 11.2

Addressing, Base Plus Index, Base Plus Offset,
and Scaled Index Addressing, Assembly to
Machine Instruction Conversion (for 8086
ISA ), 8086 Instruction Summary

RL3.3 8086 machine Instruction format and encoding T1 – 11.3, 11.4

8086 Instruction types and description

During CH CH6 Problem Solving from Text Book

Post CH SS6 R1: Section 3.21 to 3.23

HW6 T1: Problem 11.16, 11.17,

LE6 NA

QZ6

Lab Reference

Contact Hour 7
Time Type Description Content Reference

Pre CH RL4.1 Computer Memory Hierarchy, Concept of

Locality of Reference, Two Level Memory
System, Direct Cache Mapping Function

During CH CH7 CH7.1 =A brief summary of recorded lectures,

CH7.2 = Text Book Problem Solving

Post CH SS7 T1: Section 4.1, 4.4

HW7 T1: Problem 4.8, 4.9, 4.15

LE7

QZ7

Lab Reference

Contact Hour 8
Time Type Description Content Reference

Pre CH RL4.2 Fully Associative and Set Associative Mapping,

Cache Line Replacement Algorithms (LRU,
LFU, FIFO, Random)

During CH CH8 CH8.1 =R1: Section 5.3

Post CH SS8 T1: Section 4.5

HW8 R1: Problem 5.6, 5.10, 5.11

LE8 NA

QZ8

Lab Reference

Contact Hour 9
Time Type Description Content Reference
Pre CH RL4.3 Cache Performance Measurement , Cache Miss
Types, Hit Ratio, Block Size vs. Hit Ratio,
Write Policy, Multilevel Caches and
Performance

During CH CH9 Text Book Problem Solving

Post CH SS9 R1: Section 5.7, 5.8

HW9 R1: Problem 5.12, 5.15, 5.18,

LE9 NA

QZ9

Lab Reference

Contact Hour 10
Time Type Description Content Reference

Pre CH RL5.1 Internal Memory: Semiconductor memory

Types (RAM, ROM, PROM, EPROM,
EEPROM), Static and Dynamic RAM, Cell
Organization, Chip Organization, Module
Organization, SDRAM and DDR RAM

RL5.2 External memory, Magnetic Disks, Disk

Characteristics, Disk Performance Parameters

During CH CH10 CH10.1 =A brief summary of recorded lectures,

CH10.2 = T1: Problem Solving

Post CH SS10 T1: Section 6.3, 6.4

HW10 T1: Problem 5.8, 6.3, 6.4, 6.8

LE10

QZ10

Lab Reference

MID SEMESTER EXAMINATION

Contact Hour 11

Time Type Description Content Reference

Pre CH RL5.3 Performance Improvement in Secondary

storage: RAID levels
During CH CH11 CH11.1 =A brief summary of recorded lectures,
CH11.2 = T1: Problem Solving

Post CH SS11 R1: Section 5.2.4, 5.2.6, 5.2.7, 5.3

HW11 R1: Problem 5.25,

LE11 NA

QZ11

Lab Reference

Contact Hour 12
Time Type Description Content Reference

Pre CH RL6.1 I/O Modules: Function and Structure I/O

Methods: Programmed and Interrupt Driven I/O

During CH CH13 CH13.1 =A brief summary of recorded lectures,

CH13.2 =T1: Section 7.6, 7.7;

Post CH SS13 T1: Section 7.4;

HW13 T1: Problem 7.13, 7.14;

LE13

QZ13

Lab Reference

Contact Hour 13
Time Type Description Content Reference

Pre CH RL6.2 Direct Memory Access (DMA), DMA

Configurations

During CH CH14 CH14.1 =A brief summary of recorded lectures,

CH14.2 = T1: Problem Solving

Post CH SS14 R1: Section 4.2.5, 4.2.6

HW14 R1: Problem 4.3, 4.23, 4.35

LE14 NA

QZ14

Lab Reference

Contact Hour 14
Time Type Description Content Reference

Pre CH RL7.1 RISC and CISC Architectures, Instruction

Pipelining, Six Stage Pipeline Example, Pipeline
Performance Parameters and Speedup Ratio

During CH CH15 CH15.1 =A brief summary of recorded lectures,

CH15.2 =T1: Section 13.2

Post CH SS15 T1: Section 12.5

HW15 T1: Problem 12.8, 12.9

LE15

QZ15

Lab Reference

Contact Hour 15
Time Type Description Content Reference

Pre CH RL7.2 Pipeline Hazards: Data Hazards(RAW),

Resource Hazards, Control Hazards, RISC
Pipeline as an example

During CH CH16 CH16.1 = A brief summary of recorded lectures

CH16.2=Problem Solving

Post CH SS16 T1: Section 13.1;

HW16 T1: Problem 13.7, 14.3

LE16 NA

QZ16

Lab Reference

Contact Hour 16
Time Type Description Content Reference

Pre CH RL7.3 Superscalar Pipelining, Machine and Instruction

Level Parallelism, Superscalar Processor Design
Issues, Instruction Issue Policies, Data Hazards
(WAR, WAW), Register Renaming to eliminate
WAR and WAW Hazards

During CH CH17 CH17.1 = A brief summary of recorded lectures

CH17.2=Problem Solving

Post CH SS17 R1: Section 8.4

 HW17 R1: Problem 8.1, 8.13, 8.15

LE17 NA

QZ17

Lab Reference

Contact Hour 17
Time Type Description Content Reference

Pre CH RL8.1 Instruction Cycles: Fetch, Indirect, Interrupt,

Execution, Micro Operations and Micro
Instructions, Control Unit Design

During CH CH18 CH18.1 =A brief summary of recorded lectures,

CH18.2 =T1: Problem Solving

Post CH SS18 R1: Section 7.4

HW18 T1: Problem 15.2,

LE18 NA

QZ18

Lab Reference

Contact Hour 18
Time Type Description Content Reference

Pre CH RL8.2 Control Unit Implementation: Hardwired and

Micro-programmed, Micro-instruction Type
and Sequencing

During CH CH19 CH19.1 =T1: Problem Solving

Post CH SS19 R1: Section 7.5

HW19 T1: Problem 15.3

LE19 NA

QZ10

Lab Reference

Contact Hour 19

Time Type Description Content Reference

Pre CH RL9.1 Parallel Processor Architectures (Flynn

 Classification), SMP

RL9.2 Cache Coherence Problem and Solutions

(Directory Protocols and Snoopy Protocols)

During CH CH20 CH20.1 = Basics of Multicore processors

Post CH SS20 T1: Section 18.4 (Basics of Multicore

processors)

HW20 T1: Problem 17.4, 17.5

LE20 NA

QZ20

Lab Reference

Contact Hour 20
Time Type Description Content Reference

Pre CH RL9.3 Clusters

Cluster vs. SMPs
Non Uniform Memory Access (NUMA)
Architecture
Cache Coherence in NUMA

During CH CH21 CH21.1 = A brief summary of recorded lectures

Post CH SS21 R1: Section 12.5, 12.6

HW21 T1: Problem 17.6

LE21 NA

QZ21

Lab Reference

Detailed Plan for Lab work/Design work:

Ref: CPU-OS simulator (http://www.teach-sim.com)

Lab Lab Objective Lab Sheet Content

No Access URL Reference

1 Introduction to CPU-OS Simulator Unit 1

2 Lab to investigate CPU instructions Unit: 3

3 Lab to investigate Instruction Pipelines Unit: 7

4 Lab to investigate Cache Technology Unit: 4

 5 ARM based assembly language programming using Unit: 3
ARM-SIM

Access to Lab Resources : More information will be provided through TAXILA and online lectures
on this.
Lab Sheets : Course Page on TAXILA for accessing information.
Lab Server / Source to Softwares: ModelSim available at http://www.altera.com
Note: You need to download ModelSim starter edition which is free.

Important Information:
Syllabus for Mid-Semester Test (Closed Book): Topics in CS 1-5.
Syllabus for Comprehensive Exam (Open Book): All topics given in plan of study
Evaluation Guidelines:
1. For Closed Book tests: No books or reference material of any kind will be permitted.
Laptops/Mobiles of any kind are not allowed. Exchange of any material is not allowed.
2. For Open Book exams: Use of prescribed and reference text books, in original (not
photocopies) is permitted. Class notes/slides as reference material in filed or bound form is
permitted. However, loose sheets of paper will not be allowed. Use of calculators is permitted
in all exams. Laptops/Mobiles of any kind are not allowed. Exchange of any material is not
allowed.
3. If a student is unable to appear for the Regular Test/Exam due to genuine exigencies, the
student should follow the procedure to apply for the Make-Up Test/Exam. The genuineness of
the reason for absence in the Regular Exam shall be assessed prior to giving permission to
appear for the Make-up Exam. Make-Up Test/Exam will be conducted only at selected exam
centres on the dates to be announced later.
It shall be the responsibility of the individual student to be regular in maintaining the self-study
schedule as given in the course handout, attend the lectures, and take all the prescribed evaluation
components such as Assignment/Quiz, Mid-Semester Test and Comprehensive Exam according to the
evaluation scheme provided in the handout.