Microprocessors

Module 10
Data Processing
1. Orient the students on how data is actually
processed.
2. Orient the students on how branching is achieved on
the microprocessor level.
EXECUTION OF A COMPLETE
INSTRUCTION
Assume the following instruction:
R1  [R1] + [[R2]]
The contents of register R1 are added to the contents of
a memory location (the address of which is in register
R2) and store the results in register R1.
Executing this instruction requires the following actions:
1. Fetch the instruction.
2. Fetch the first operand (the contents of the memory
location pointed to by R2).
3. Perform the addition.
4. Load the result into R1.
Control Sequence for R1  [R1] + [[R2]]
1. PCout, MARin, Read, Select1, Add, Zin
2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. R2out, MARin, Read
5. R1out, Yin, WMFC
6. MDRout, SelectY, Add, Zin
7. Zout, R1in, End
Step 1.
The instruction fetch operation is initiated by loading the
contents of the PC into the MAR and sending a Read
request to the memory. The select signal is set to
Select1, which causes the multiplexer MUX to select the
constant 1. This value is added to the operand at input B,
which is the contents of the PC, and the result is stored
in register Z (the PC is incremented by 1).
Step 2.
The updated value of the PC (which is in register Z) is
moved back to the PC. Note that step 2 begins
immediately after the memory Read is requested, without
waiting for the memory function to be completed. Step 3,
however, has to be delayed until the MFC signal is
received.
Step 3.
The word fetched from the memory is loaded into the IR.
The instruction decoding circuit interprets the contents
of the IR at the beginning of step 4. This enables the
control circuitry to choose the appropriate signals for
the remainder of the control sequence.
Steps 1 through 3 constitute the instruction fetch phase,
which is the same for all instructions. Steps 4 through 7
constitutes the execution phase.
The contents of register R3 are transferred to the MAR in
step 4, and a memory read is initiated.
Then the contents of R1 are transferred to register Y in
step 5, to prepare for the addition operation.
When the Read operation is completed, the memory
operand is available in register MDR, and the addition
operation is performed in step 6. The contents of the
MDR are gated to the bus, and thus also to the B input of
the ALU, and register Y is selected as the second input
to the ALU by choosing SelectY. The sum is stored in
register Z.
The sum is then transferred to R1 in step 7. The End
signal causes a new instruction fetch cycle to begin by
returning to step 1.
Take note that in step 2, the updated contents of PC are
also loaded to register Y. This has no purpose in the
execution of the Add instruction. But in Branch
instructions the updated value of PC is needed to
compute the Branch target address. To speed up the
execution of Branch instructions, this value is copied
into register Y in step 2. Since step 2 is part of the fetch
phase, the same action will be performed for all
instructions. This does not cause any harm because
register Y is not used for any other purpose at that time.
Assume the following instruction:
R1  [R1] + [LOC]
Executing this instruction requires the following actions:
1. Fetch the instruction.
2. Fetch the first operand (the contents of the memory
location pointed to by the address field of the
instruction).
3. Perform the addition.
4. Load the result into R1.
Control Sequence for R1  [R1] + [LOC]
1. PCout, MARin, Read, Select1, Add, Zin
2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. Offset-field-of-IRout, MARin, Read
5. R1out, Yin, WMFC
6. MDRout, SelectY, Add, Zin
7. Zout, R1in, End
Branching
Branching
Branching is accomplished by replacing the current
contents of the PC by the branch address, that is, the
address of the instruction to which branching is
required.
This branch address is usually obtained by adding an
offset X, which is given in the branch instruction, to the
updated value of the PC.
Control Sequence for Unconditional Branching
1. PCout, MARin, Read, Select1, Add, Zin
2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. Offset-field-of-IRout, SelectY, Add, Zin
5. Zout, PCin, End
For conditional branching, the only difference is the
need to check the status of the condition codes before
loading a new value into the PC.
Example:
Branching on Negative Instruction (Jump if the sign flag
= 1)
1. PCout, MARin, Read, Select1, Add, Zin
2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. Offset-field-of-IRout, SelectY, Add, Zin, if SF = 0 then
End
5. Zout, PCin, End
S. Mathur(2016), Microprocessor and Microcontrollers,
PHI Learning and Private Limited
Taylor and Francis Group. Essentials of Computer
Architecture. CRC Press, Comer, D. (2017).
Jones and Bartlett Learning, Computer Organization And
Architecture (10th Ed.), Stallings, (2016)
Microprocessors
 Module 10
Data Processing
1. Orient the students on how data is actually
processed.
2. Orient the students on how branching is achieved on
the microprocessor level.
EXECUTION OF A COMPLETE
INSTRUCTION
Assume the following instruction:
R1  [R1] + [[R2]]
The contents of register R1 are added to the contents of
a memory location (the address of which is in register
R2) and store the results in register R1.
Executing this instruction requires the following actions:
1. Fetch the instruction.
2. Fetch the first operand (the contents of the memory
location pointed to by R2).
3. Perform the addition.
4. Load the result into R1.
Control Sequence for

R1  [R1] + [[R2]]

1. PCout, MARin, Read,

Select1, Add, Zin
2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. R2out, MARin, Read
5. R1out, Yin, WMFC
6. MDRout, SelectY, Add, Zin
7. Zout, R1in, End
Step 1.
The instruction fetch operation is initiated by loading the
contents of the PC into the MAR and sending a Read
request to the memory. The select signal is set to
Select1, which causes the multiplexer MUX to select the
constant 1. This value is added to the operand at input B,
which is the contents of the PC, and the result is stored
in register Z (the PC is incremented by 1).
Step 2.
The updated value of the PC (which is in register Z) is
moved back to the PC. Note that step 2 begins
immediately after the memory Read is requested, without
waiting for the memory function to be completed. Step 3,
however, has to be delayed until the MFC signal is
received.
Step 3.
The word fetched from the memory is loaded into the IR.
The instruction decoding circuit interprets the contents
of the IR at the beginning of step 4. This enables the
control circuitry to choose the appropriate signals for
the remainder of the control sequence.
Steps 1 through 3 constitute the instruction fetch phase,
which is the same for all instructions. Steps 4 through 7
constitutes the execution phase.
The contents of register R3 are transferred to the MAR in
step 4, and a memory read is initiated.
Then the contents of R1 are transferred to register Y in
step 5, to prepare for the addition operation.
When the Read operation is completed, the memory
operand is available in register MDR, and the addition
operation is performed in step 6. The contents of the
MDR are gated to the bus, and thus also to the B input of
the ALU, and register Y is selected as the second input
to the ALU by choosing SelectY. The sum is stored in
register Z.
The sum is then transferred to R1 in step 7. The End
signal causes a new instruction fetch cycle to begin by
returning to step 1.
Take note that in step 2, the updated contents of PC are
also loaded to register Y. This has no purpose in the
execution of the Add instruction. But in Branch
instructions the updated value of PC is needed to
compute the Branch target address. To speed up the
execution of Branch instructions, this value is copied
into register Y in step 2. Since step 2 is part of the fetch
phase, the same action will be performed for all
instructions. This does not cause any harm because
register Y is not used for any other purpose at that time.
S. Mathur(2016), Microprocessor and Microcontrollers,
PHI Learning and Private Limited
Taylor and Francis Group. Essentials of Computer
Architecture. CRC Press, Comer, D. (2017).
Jones and Bartlett Learning, Computer Organization And
Architecture (10th Ed.), Stallings, (2016)
Microprocessors
 Module 10
Data Processing
1. Orient the students on how data is actually
processed.
2. Orient the students on how branching is achieved on
the microprocessor level.
Branching
Branching
Branching is accomplished by replacing the current
contents of the PC by the branch address, that is, the
address of the instruction to which branching is
required.
This branch address is usually obtained by adding an
offset X, which is given in the branch instruction, to the
updated value of the PC.
PARTS OF AN INSTRUCTION

OP CODE OFFSET FIELD

Control Sequence for Unconditional Branching
1. PCout, MARin, Read, Select1, Add, Zin
2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. Offset-field-of-IRout, SelectY, Add, Zin
5. Zout, PCin, End
For conditional branching, the only difference is the
need to check the status of the condition codes before
loading a new value into the PC.
Example:
Branching on Negative Instruction (Jump if the sign flag
= 1)
1. PCout, MARin, Read, Select1, Add, Zin
2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. Offset-field-of-IRout, SelectY, Add, Zin, if SF = 0 then
End
5. Zout, PCin, End
S. Mathur(2016), Microprocessor and Microcontrollers,
PHI Learning and Private Limited
Taylor and Francis Group. Essentials of Computer
Architecture. CRC Press, Comer, D. (2017).
Jones and Bartlett Learning, Computer Organization And
Architecture (10th Ed.), Stallings, (2016)
In executing a complete instruction

- The first three steps are always the same

o 1. PCout, MARin, Read, Select1, Add, Zin
o 2. Zout, PCin, Yin, WMFC
o 3. MDRout, IRin
- Steps 4 and onwards are what you call the execution phase, this is the part where the CPU
actually executes the instruction
- During the first three steps, the contents of the program counter are updated and also
stored in Y register in order to prepare for a branch instruction