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Input Output: Always If (A B)
Input Output: Always If (A B)
begin
greater = 0; equal = 0; lower = 1;
end
else if (a == b)
begin
greater = 0; equal = 1; lower = 0;
end
else
begin
greater = 1; equal = 0; lower = 0;
end
end
endmodule
output equal ;
output greater ;
output lower ;
input [1:0] a ;
input [1:0] b ;
endmodule
Gate Level
input a0,a1,b0,b1;
output f0,f1,f2;
wire x,y,u,v,p,q,r,j,k,c,f,g;
not(x,a0);
not(y,a1);
not(u,b0);
not(v,b1);
and(p,x,y,b0);
and(q,x,b0);
and(r,b0,b1,y);
or(f0,p,q,r);
and(j,a1,b1);
and(k,y,v);
or(f1,j,k);
and(c,a1,u,v);
and(f,a0,u);
and(g,v,x,y);
or(f2,c,f,g);
endmodule
STRUCTURAL
module comparator2BitStruct(
input wire[1:0] a, b,
output wire eq
);
4 BIT COMPARATOR
Behave
module comparator(
Data_in_A, //input A
Data_in_B, //input B
less, //high when A is less than B
equal, //high when A is equal to B
greater //high when A is greater than B
);
Data Flow
module comparator_4_bit (a_gt_b, a_lt_b, a_eq_b, a,b);
input [3 : 0] a,b;
output a_gt_b, a_lt_b, a_eq_b;
endmodule
ONE BIT
Gate Level
module comparator_1_bit(
input x,
input y,
output a, //x>y
output b, //x=y
output c //x<y
);
not(xn,x),(yn,y);
and(a,x,yn),(c,xn,y);
nor(b,a,c);
endmodule
Data
module comparator_1bit ( a ,b ,equal ,greater ,lower );
output equal ;
output greater ;
output lower ;
input a ;
input b ;
assign equal = a ~^ b;
assign lower = (~a) & b;
assign greater = a & (~b);
endmodule