MICROELECTRONIC

FABRICATION
1 3. Photolithography

In the last chapter, we discussed about BEOL process.

We have seen BEOL process involves fabrication of metal interconnects

(Metallization). The interconnects are needed to connect the active devices and for
power distribution. The interconnects are classified as local, intermediate and global
interconnects based on the dimension.

We discussed what are the materials being considered for interconnects. Previously,
we used Al and then we moved to Cu. What are the issues we faced and how we
overcame them when we moved to Cu? These were also discussed in the previous
chapter. Mainly, we have seen, Cu cannot be removed by etching process and hence
CMP process was introduced. The Cu patterning was done by damascene technique.
This is classified in to single and dual type. Again, in dual type, we have trench first
and via first process.

What are the various process steps in Cu and Al patterning? We have discussed the
process flow sheet for both the materials. Here onwards, we will discuss the
processes involved in BEOL in detail one by one.

The first process technique , we are going to discuss is photolithography.

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 OVERVIEW
 Layout
 Mask

 Photolithography
 Its figure of merit
 Types of Lithography
 Basic
 Advanced
 Limitations and Applications

The overview of this chapter is given in this slide. First we will discuss layout followed
by mask and then photolithography.

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 LAYOUT, MASK AND LITHO
❑ Layout
❑ Convert electrical design to physical design
❑ 2D ‘picture’ of the final chip (quantitative)
❑ Mask
❑ hard copy of the physical layout (similar to photo
negative)
❑ Can be used to generate many chips (similar to
obtaining many copies from a negative)
❑ Photo (Lithography)
❑ Process of obtaining a ‘picture’ from a ‘negative’
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❑ the transferring of patterns from the mask to the wafer

The sequence for making chips is creating physical layout followed by mask making
and then eventually making chips from mask using photolithography technique. So
before discussing photolithography, we will discuss about layout first.

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 LAYOUT, MASK AND LITHO
❑ Layout
❑ Convert electrical design to physical design
❑ 2D ‘picture’ of the final chip (quantitative)

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Picture: Physical design for system on a chip by Y. Chang at al , 2006
DOI:10.1007/1-4020-5352-5_9

As I said before, Once the device is fixed, the electrical design should be made for the
same. From this electrical design, physical layout should be created i.e. the circuit
representation (electrical design) is converted into geometric representation (physical
layout) as shown in the above picture. For example, if you look at the electrical
design, you know how many transistors are required and how to connect them. The
physical layout shows how everything will look (top view) on an actual chip. It also
provides quantitative information i.e. what is the length and width of a, b, c, d and e,
what is the distance between c and a, a and b and so on., what is the length and
width of yellow and green rectangular block. In short, it gives you 2D picture of the
final chip.

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 LAYOUT
 Soft copy file
 MS file – doc file; Acrobat portable file –pdf
 Layout file -GDS
 IC chips- many layers (transistors, Gate , metal
layers)
 GDS file have info about all the layers
 But each layer must be specified separately
 If the circuit in the chip is repetitive, then storing the
one circuit in file is sufficient.
 Group level information vs. individual level
information
 Hierarchical file (to reduce the size of file) vs. flat file
(have complete info) 5

All the information about physical layout is stored in a soft copy file where the
information for all the layers (FEOL, BEOL) are available. Basically, this is stored in a
magnetic tape. Then this will be feed to pattern generator (mask masking machine)
to create masks. Using these masks, we will create actual chips. Before moving onto
masks and making chips, we will discuss little more about layout.

The physical layout file format is GDS. (just similar to referring word file as .doc and
acrobat reader file as .pdf)

IC chips have many layers (transistors, Gate , metal layers) GDS file have info
about all the layers
But each layer must be specified separately
If the circuit in the chip is repetitive, then storing the one circuit in file is
sufficient.

In some cases, we need detailed info about all the layers (i.e. individual level
information). For example, if we want to perform optical proximity correction (OPC)
for the given layout, then we must know the details of this layout. I will discuss about
OPC later. Right now you assume, it is one of the correction techniques performed to
get the patterns right on the chip.

However in some cases, group level info is sufficient. It can be understand by the

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following analogy. In a company, we have one CEO, two GM, 4 mangers and 8
workers. 2 workers are working under one manger (first level) that is referred as Team
1. Every two managers are controlled by one GM (Second level) and both GMS are
controlled by CEO (third level). There are different levels (this is called hierarchy). If
we want to compute the salary of the company it is sufficient if we know the salary of
team 1 in level 1(assume the salary is same for the given post). No need to worry
about individual salary. But if someone is absent for a particular day, then if other
person works for extra time, then we must know the individual salary details to
compute the salary.

Same thing here. Hierarchical file contains overall info (to reduce the size of file) and
flat file has complete information about all the layers.

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 LAYOUT (CONTD…)

Example
A sample part of a
chip

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M1
Via 12

M2

The file has different layers (numbered from 1 to...)

A table which correlates the layers to numbers is also
provided Layer Number
M1 11
V12 12
M2 21
V23 22
M3 31
V33 32
M4 41

As mentioned, layout contains information about all the individual layers. Here in this
slide, you can see the information about M1 layer, via 12 and M2 layer. Please note
here via12 (black squares) has to be align properly w.r.t to M1 and, similalrly M2
(green squares) should be aligned with via12 (how to align – we will see in
photolithography section under “ alignment”). Do remember, all these information
are quantitative.

A table which correlates the layers to numbers is also provided in the file as shown in
the slide.

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 LAYOUT (CONTD…)
❑ Via and contacts are shown as squares/ rectangles
(rare cases) in the layout. Others are in rectangular
geometry
❑However, the mask will have circular (or in rare
cases elliptical) holes
❑ Completely filling rectangular features (with metal) in high
aspect ratio is difficult
❑ Aspect ratio: Depth/width (or diameter)

Dia width
Dia width

height height
7

Low aspect ratio High aspect ratio

Read the slide. It is self explanatory.

I am trying to explain aspect ratio using the figures.

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 LAYOUT (CONTD…)

This depth size (Z) will not be

in layout file. It is provided in
the process flow sheet.
Layout have info on X and Y

Picture courtesy: http://www.eetimes.com/document.asp?doc_id=1262098

As mentioned earlier, the layout gives 2D (X and Y information) view of the chip. The
third dimension (depth, marked as “Z” ) information will not be there in the layout
file. This info will be available in process flow sheet and could be controlled during
manufacturing process.

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 LAYOUT, MASK AND LITHO
❑ Layout
❑ Convert electrical design to physical design
❑ 2D ‘picture’ of the final chip (quantitative)
❑ Mask
❑ hard copy of the physical layout (similar to photo
negative)
❑ Can be used to generate many chips (similar to
obtaining many copies from a negative)
❑ Photo (Lithography)
❑ Process of obtaining a ‘picture’ from a ‘negative’
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❑ the transferring of patterns from the mask to the wafer

Now , moving to how to make masks using the information available in layout file.

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 MASK
 Layout for mask is designed using CAD tools
(Magic, cadence). This is stored in magnetic tape.
 This will be feed to the pattern generator.
 Emulsion coated glass plate
 Chrome plate glass plate
 Composite mask (one layer needs to be defined
with other layer
 Separate level of mask for each layer

 Magnification higher

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Once the physical layout is ready , we have to create mask. Now let discuss about Mask:

Physical Layout for mask, which we discussed so far, is designed using CAD tools (Magic,
cadence). This is stored in a magnetic tape.
This will be feed to the pattern generator (Mask Making machine). Mask is something like
hardcopy of the physical layout.

What is the material used for making masks?

1. Emulsion coated glass plate

2. Chrome plate glass plate

So either emulsion or chromium is coated on the glass substrate and the patterns are written
on this emulsion/chromium. Substrate is glass as the substrate being used in
photolithography must allow the light of given wavelength to pass through and should have
zero defects ideally. Otherwise, it may alter the light travelling path. Cost also counts here.

We have two types of mask:

1. Emulsion coated – cheaper, resolution is lower, coating quality will be poor. Usually we
use this when the dimension size is bigger. Ex: if actual feature size is 5 micron, we will
be getting 5.5 micron. This is allowable as it won’t affect the chip performance
significantly. But if the actual size itself is 1 micron, then getting 1.5 micron may affect
chip function. So we have to move chrome plated glass plate.
2. Chrome coating – expensive, good resolution, can obtain good coating quality. In IC
fabrication, we are using this currently.

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Here resolution means what is the minimum size that we could print on the wafer.
We will discuss in detail later.

As we already discussed in slide no. 5, the one layer needs to be aligned w.r.t other,
initially a composite mask is prepared with all the structures
aligned w.r.t one another. Then, this composite mask is broken into separate mask for
each layer.

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 MASK (CONTD..)
❑ The layout file is given as ‘input’ the mask making
machine
❑ Mask may be a plate of glass, coated with chromium.
On top of chromium, a photosensitive coating is
applied
❑ A mask is often referred to as ‘chrome’
❑ E-Beam, ‘sensitizes’ the areas
❑ E-beam writer (electron beam)
❑ Scans the “blank” mask
❑ Develop the resist
❑ Remove chromium on the ‘exposed’ areas 11

How the mask is created physically? It is explained in this slide.

The layout file is given as ‘input’ to the mask making machine. We have to take the
blank mask. Mask may be a plate of glass, coated with chromium as discussed in the
previous slide. On top of chromium, a photosensitive coating (e-beam resist) is

applied. A mask is often referred to as ‘chrome’.

Then, We have to use E-beam writer (electron beam). E-beam is act like a pen. We
can write patterns directly on the given mask. For this, we scan the blank mask using
e-beam. E-beam moves pixel to pixel. At some pixels, e-beam is in ON state and
sensitize the e-beam resist (meaning e-beam resist is softened and hence could be
removed easily in developer solution). At some pixels, e-beam is in OFF state and
won’t sensitize the e-beam resist.

So, E-Beam, ‘sensitizes’ the areas and develop the

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resist. It means e-beam resist is removed in certain
region (exposes the underneath Cr layer) and not
removed in remaining region (does not expose the
underneath Cr layer). Then the chromium will be
removed on the ‘exposed’ areas. I will post a video
on this for better understanding.

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 MASK (CONTD..)
❑ Relatively slow process
❑ beam goes to each ‘pixel’ which has to be written ‘on’
❑ switches “on” and then “off”
❑ moves to the next pixel which has to be written on

❑ Mask has to be very clean.

❑ Any particle on the mask will cause incorrect ‘feature’
in all the chips
❑ ==> chips will to fail

❑ A mask is then coated with a clear film, to

protect it.
❑ Eg. If a particle falls on the mask, then you can remove
the clear film and put a new film. (Easy to ‘repair) 12

During scanning(writing), it goes pixel by pixel. So very slow process. Sometimes, it

may take even one day to write a mask. So the cost of the mask will also be high. The
cost varies from lakhs to crores depending upon complexity involved in the chip
design. However, we need one mask for making many chips. So this method is
preferable in semiconductor industry for making masks.

Once the mask is made, it has to be very clean. Any particle on the
mask will cause incorrect ‘feature’ in all the chips.
So, the chips will fail.
So, the mask is then coated with a clear film, to protect it. Eg. If a particle

falls on the mask, then you can remove the clear

film and put a new film. (Easy to ‘repair).

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 MASK (CONTD..)
❑ If a mask gets dirty in a particular location,
❑ with in a ‘field’, a die will always fail

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White region- chips; violet region – space b/w chips. If some particle fall on violet
region, it won’t affect the chip function. But if particle falls on white region, it will
affect the chip performance.

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 MASK (CONTD..)
❑ A mask may be 100 mm x 100 mm (for example)
❑ The size is decided by the size of the lens in the lithographic tool
❑ A mask is usually 4 to 5 times larger than the actual feature. The
features are ‘reduced/ zoomed out’ during the lithographic process
❑ Correspondingly, a mask is referred to as ‘4x mask’ or ‘5x mask’
❑ Example: If you want a 100 nm wide line on the wafer
❑ layout file will show 100 nm wide line on the screen
❑ mask making machine will enlarge everything by 4
❑ Actually, layout file will be converted to another file which will enlarge
it by 4 and then the mask making machine will use it.
❑ The process is sometimes called MDP (Mask Data Preparation)
❑ Mask will have 400 nm wide opening and
❑ Lens in the litho process will ‘shrink’ the image to 100 nm. 14

Read this slide. It is self explanatory.

Why we are zoomed out? Because,in this case, the resolution of lithography is not
limited by the resolution of the mask. For example, if there is a slight variation in the
mask pattern dimension, it will get zoomed out (i.e. variation will decrease) when it is
printed on the wafer.

We will discuss about resolution in detail in the upcoming slides.

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 MASK (CONTD..)
❑ A mask may be 100 mm x 100 mm (for example)
❑ So, one ‘print’ will be about 25 mm by 25 mm, on
the wafer.
❑ A chip may be only 5 mm by 4 mm

❑ So, one mask will have perhaps 20 chips, if the

chip is small

❑ The gaps between the ‘real chips’ are

used for
❑ alignment marks (TBD)
❑ test structures (TBD)
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TBD- to be discussed later

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 MASK (CONTD…)

Mask

Patterns in mask to be transferred

to wafer

Wafer
with PR
coating
16

This slide just show how the mask is used in lithography process. Green color – glass
substrate black color –chromium patterns

Yellow-color –photoresist
Grey – wafer

The patterns in mask have to be transferred to wafer. How? Using photolithography

technique. So, we will see next the same.

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LAYOUT, MASK AND LITHO
❑ Layout
❑ Convert electrical design to physical design
❑ 2D ‘picture’ of the final chip (quantitative)
❑ Mask
❑ hard copy of the physical layout (similar to photo
negative)
❑ Can be used to generate many chips (similar to
obtaining many copies from a negative)
❑ Photo (Lithography)
❑ Process of obtaining a ‘picture’ from a ‘negative’
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❑ the transferring of patterns from the mask to the wafer

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 LITHOGRAPHY

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Litho means stone. In the olden days , the patterns are engraved on the stone and
then some ink will be applied on to these patterns. Finally, patterns are transferred
to the paper as shown in the slide. In semiconductor industries also, the patterns are
transferred from mask to wafer using light. That’s why it got the name
photolithography.

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 LITHOGRAPHY
Coat the wafer with light
sensitive material (photo-
resist)

Place mask over the wafer,

align the mask w.r.t wafer,
focus the light through the
mask
Exposure for a precise
amount of time

Developing and Etching

Move (Step) to the next ‘Field’

Stepper
Actually, the wafer moves, not the litho system 19

Repeat the above procedure

Read the slide. I will post a short video on this for better understanding. This is the
overall process sequence. The details of each step will be discussed later in this
chapter.

Developer: Once the photoresist is exposed to radiation, it is either

hardened/softened. Then we have to dip the wafer in the developer solution. The
relatively softened region will be removed in the developer solution. This stage is
called developing.

Stepper: wafer size is larger than mask. So, when we transfer patterns from mask to
wafer, it is one “print” as highlighted by green color square. Then we have to move to
other grey square and repeat the same procedure.

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 LITHOGRAPHY: BASIC STEPS
After the whole wafer is exposed....
Repeat for other wafers in the lot
Crude schematic below

Develop the lot

Etch the open areas

Remove the remaining

photo resist and the etch
products

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Note: Etch product forms a thin film or ‘veil’. Removal of the veil is
called ‘de-veil’

Read the slide. Self explanatory.

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 FIGURES OF MERITS OF LITHOGRAPHY

 Resolution
 Minimum feature size
 Precision with which minimum feature size can be
incorporated in the wafer
 Minimum size and accuracy are interrelated
 Throughput
 How many wafers can be processed in a given time
 Cost
 E-beam lithography –slower process
 Depth of focus
 Many layers of mask
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 Mask 1 has to be aligned with Mask 2

Before seeing the types of lithography process in detail, let first discuss figures of
merit associated with lithography.

Resolution means, what is the minimum feature size that can be incorporated in the
wafer. For example, if we have a line of width 0.1 micrometer in mask, then, whether
that can be transferred to wafer as same or as 0.12/0.8 micrometer (20% variation) or
0.14/0.6 micrometer (40% variation). We want this variation to be small i.e.
resolution to be better. So, the resolution refers the precision with which minimum
feature size can be incorporated in the wafer. How accurately we are transferring the
patterns from the mask to the wafer. So the minimum size and accuracy are
interrelated.

Throughput – Read the slide.

Depth of focus – As we have many layers of mask, we have to align the mask of
particular layer with mask of other layer. Then we have to focus the light. Focusing on
particular layer? or focusing on other layer? Read the next slide for better
understanding.

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 DEPTH OF FOCUS

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In LHS photo, you could clearly see the batsman (first layer), wicket keeper (second layer) but
not audience (third layer). In RHS photo, you could clearly see bowler (First layer), but not
wicket keeper (second layer) and audience (third layer). Here the cameraman focusing on
first layer , that’s why third layer is blurred. If the depth of focus is better for camera, then
you could see first and second layer clearly. If it is not good, then second layer might also get
blurred.

Here in photolithography process, as we are dealing with many layers and focusing, the
depth of focus needs to be good.

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 LITHOGRAPHY: RESOLUTION
Resolution and other parameters


 = k1
NA
 = Minimum Feature Size  = Wavelength of light used
D
k1 = Raleigh Constant NA = Numerical Aperture=
2f
f – focal length of lens
D- diameter of the lens
Depth of Focus or Depth of Field (DOF)

DOF = k2
NA2
We need small  and large DOF 23

Better resolution = smaller sigma value.

So decrease the wavelength to reduce the sigma value. But it also affect depth of
focus(DOF). DOF has to be higher.

So we cannot reduce the wavelength to a much smaller value.

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 PHOTORESIST
 Positive
 Throughput is lower
 Resolution is higher
 Resin + photosensitive material+ solvent
 Negative
 Resolution is lower
 Polymer + photosensitive material + solvent
 Swelling up decreases resolution
 Cross-linking not possible if oxygen is present

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We have seen photoresist has to be coated on top of the wafer during

photolithography process. There are two types of photoresist (1) positive and (2)
negative photoresist.

In positive resist, we have a mix of resin and photosensitive material as a photoresist.

Upon exposure to radiation, the photosensitive material absorbs light and transfers to
resin molecules. Thus, the chemical bonds of the molecules get broken in exposed
regions, hence property changes. Here, the exposed regions are softened. We have
to make sure that the photoresist material is fully developed during exposure. So we
need relatively more time for exposure. Hence throughput is lower in positive
photoresist.

In negative photoresist, we use a mix of monomer chains and photosensitive

material. Upon absorption of radiation, monomer chains likely to crosslink and hence
molecular weight goes up. So it gets hardened upon receiving radiation. In this case,
as polymers usually swelling up when we put wafer in the developer solution, the
resolution might not be better as in the case of positive photoresist. Also, cross
linking will not occur if oxygen is present. So we need oxygen-free environment
(preferably nitrogen environment) to perform this operation.

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 PHOTORESIST (CONTD..)

❑ Mostly positive resists used now

❑ More resistance to pinhole formation

❑ Easier removal (stripping)

❑ More expensive

-ve resist; most area open +ve resist; most area blocked

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As the resolution is better in positive resist, we are mostly using positive resists now.

Few more advantages of using positive photoresist.

Look at the figure: In the positive resist, most of the areas on the mask are blocked
compared to –ve resist. So chips are not more likely to fail in the presence of dirt
particles if we use +ve resist. Hence positive resist has more resistance to pinhole
formation.

In positive resist, in the developed areas, the resist becomes softened unlike in
negative photoresist where it is hardened. So stripping is easier here.

On the other hand, the disadvantage of positive photoresist is

Very expensive compared to negative photoresist.

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 PHOTORESIST (CONTD..)

Photo Resist properties

❑Response to a given wavelength (spectral response)

❑ Solubility differential between unexposed vs exposed regions
❑ Etch/ Implant resistance
❑ Resolution

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These are some of the properties of photoresist that one has to consider while
choosing for photolithography process.

Solubility differential: The difference in dissolution rate of softened and hardened

part of resist in the developer solution. This should be high like 100:1

After lithography, we will be performing many operations such as etching,

implantation and harsh conditions will be employed during these steps. The
photoresist has to withstand those harsh environment.

Read the slide for other properties and those are easy to understand.

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 LITHOGRAPHY : DETAILS

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To get the same pattern on the wafer, we have different masks for +ve and –ve
photoresist.

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 TYPES OF LITHOGRAPHY
 Optical
 Photoresist
 UV light
 E-Beam
 E-Beam Resist
 No need of Mask
 E- Beam is acting like a pen
 X-ray
 Same as Optical
 Instead of UV light, X-rays will be used
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So far we discussed, the principle of photolithography technique and how the

patterns are written on the wafer.

Now, we will discuss the various types of lithography.

There are mainly three types as shown in the slide.

The principle of optical and x-ray lithography is the same. The only difference is that,
as the name suggests, in X-ray lithography, we will use X-rays instead of UV light. In
both the cases, the resist what we are using is called photoresist.

The E-beam lithography technique, we have already discussed it during mask making
process.

Here in this technique, we don’t use any mask. The resist what we are used is called
as E-beam resist. Here patterns are directly written on the wafer.

The pros, cons and applications of these processes are discussed in the upcoming
slides.

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 OPTICAL
 Oldest and still in use (popular)
 Steps are already defined
 Sub- Classification
 Contact Printing
 Wafer – Mask in Contact with each other
 Resolution will be good
 Mask life will be shorter
 Wafer contamination is possible
 Proximity Printing
 Close to each other (10- 25 micron)
 Resolution is sacrificed minimally
 But life of wafer will be improved

 Projection Printing
 Image if focused on the wafer using suitable optic technique
 Penalty-cost
 Resolution could be limited by diffraction limit which in
turn depends on wavelength of light. (as discussed before) 29

The optical lithography are further classified based on the distance b/w mask and
wafer.

Please see the next slide for figure.

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 OPTICAL LITHOGRAPHY

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The images for contact, proximity and projection coating are given in this slide.

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