DDH MCQs

Unit No. 1

1. What is the full form of VHDL?

a) Verilog Hardware Description Language
b) Very High speed Description Language
c) Variable Hardware Description Language
d) Very high speed Hardware Description Language
2. What is the basic use of EDA tools?
a) Communication of Electronic devices
b) Fabrication of Electronics hardware
c) Electronic circuits simulation and synthesis
d) Industrial automation
3. After compiling VHDL code with any EDA tool, we get __________
a) Final device
b) FPGA
c) Optimized netlist
d) Netlist
4. Which of the following is not an EDA tool?
a) Visual C++
b) Quartus II
c) Xilinx ISE
d) MaxPlus II
5. The process of transforming a design entry information of the circuit into a set of
logic equations in any EDA tool is known as _________
a) Simulation
b) Synthesis
c) Optimization
d) Verification
6. Place and Route EDA tools are used to take the design netlist and implement the
design in the device.
a) True
b) False
7. Which of the following is not a back end EDA tool?
a) Floor planning tools
b) Placement tools
c) Routing tools
d) Simulators
8. Difference between simulation tools and Synthesis tool is _________
a) Simulators are used to check the performance of circuit and Synthesis tools are for the
fabrication of circuits
b) Simulators and Synthesis tools works exactly same
c) Simulators are used just to check basic functionality of the circuit and Synthesis tools
includes timing constraints and other factors along with simulation
d) Simulation finds the error in the code and Synthesis tool corrects the code
9. What is the extension of the Netlist file; input to the place and route EDA tools?
a) EIDF
b) SDF
c) TXT
d) CPP
10. Which of the following is the basic building block of a design?
a) Architecture
b) Entity
c) Process
d) Package
11. A package in VHDL consists of _________
a) Commonly used architectures
b) Commonly used tools
c) Commonly used data types and subroutines
d) Commonly used syntax and variables

12. Complete description of the circuit to be designed is given in _________

a) Architecture
b) Entity
c) Library
d) Configurations

13. An entity can have more than one architecture.

a) True
b) False
14. Predefined data for an VHDL object is called ________
a) Generic
b) Constant
c) Attribute
d) Library
15. A process is the basic unit of execution in VHDL.
a) True
b) False
16. Which of the following describes the structure of VHDL code correctly?
a) Library Declaration; Entity Declaration; Architecture Declaration; Configurations
b) Entity Declaration; Configuration; Library Declaration; Architecture Declaration
c) Configuration; Library Declaration; Entity Declaration; Architecture Declaration
d) Library Declaration; Configuration; Entity Declaration; Architecture Declaration
17. Which of the following statement is true?
a) Package is a collection of Libraries
b) Library is a collection of Packages
c) Entity is a collection of Packages
d) Architecture is a collection of Entities
18. What does modeling type refer to?
a) Type of ports in entity block of VHDL code
b) Type of description statements in architecture block of VHDL code
c) Type of data objects
d) Type of Signals
19. Which of the following is not a type of VHDL modeling?
a) Behavioral modeling
b) Dataflow modeling
c) Structural modeling
d) Component modeling

20. In behavioral modeling, what do descriptive statements describe?

a) How the system performs on given input values
b) How the design is to be implemented
c) Netlist
d) Concurrent execution

21. Which of the following statement is used in structural modeling?

a) portmap
b) process
c) if-else
d) case
22. What is the basic unit of behavioral description?
a) Structure
b) Sequence
c) Process
d) Dataflow