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https://doi.org/10.1007/s12633-021-01366-z

REVIEW PAPER

Review of FinFET Devices and Perspective on Circuit

Design Challenges
Ravindra Kumar Maurya 1 & Brinda Bhowmick 1

Received: 15 December 2020 / Accepted: 30 August 2021

# Springer Nature B.V. 2021

Abstract
In recent technology, the demand for 3D multiple-gate MOSFETs such as FinFETs increase. In this paper, FinFETs are explored
and reviewed. The scaling of planar MOSFET below 32nm technology increases the short channel effects (SCE). To improve the
concert in low-power VLSI logic circuits and reduced the SCEs, we need enhanced gate controlling over the channel by using
multigate technology. Here, we have discussed numerous architecture of FINFET, the threshold voltage (Vth) and supply voltage
(Vdd) optimization, optimization of fin configuration, and low power technique for FinFET domino circuits.

Keywords Short Channel Effects (SCE) . Patterning and shape of Fin . Design of SRAM and circuit challenges .
FinFET domino circuits

1 Introduction low power consumption, smaller SCE effects and higher

Scaling of planar MOS increases the SCEs like hot carrier
effects, gate induced drain leakage (GIDL), leakage currents
such as subthreshold S/D leakage, gate direct tunnelling leak-
age, and drain induced barrier lowering (DIBL). The impres-
sion of short channel effects (SCE) goes down the perfor-
mance of planar MOS device [1–3]. So the planar MOS tech-
nology moves towards the multi-gate MOSFETs for increased
the device performance.
FinFETs one of the types of Multi-gate Field Effect
Transistor (MGFET), are predicted as one of the best promis-
ing device to substitute bulk MOSFET due to its improved the
SS slope, better stability, higher (ION/IOFF) ratio, better short-
channel performance, smaller intrinsic gate capacitance. The
various FinFET such as double gate FinFET (DG FinFET)
and Tri gate FinFET transistors have good SC characteristics.
These advantages are due to (1). Use of thin Si-film (2)
Lightly doped channel and (3) Double gates for better channel
control [4]. The FinFETs are 3D based emerging device. It has
* Ravindra Kumar Maurya
ravindrakumarmaurya1992@gmail.com
1
Department of Electronics and Communication Engineering, NIT
Silchar, Silchar, Assam, India
speed of operation [5, 6]. The main purpose of this paper is
to share a better knowledge of FinFETs technology. This pa-
per has six sections. In Section 2 discussed the history and
classification of FinFET, Section 3 is based on the device
doping, fin orientation and FinFETs capacitances. Section 4
deals with the circuit domain issues; Section 5 is based on
SRAM cell design, Section 6 is based on Low power tech-
nique for FinFET domino circuits design and the last Section 7
is the conclusion of the review paper.
2 History and Classification of FinFETs
This section presents the past and categorization of FinFETs.
2.1 History of FinFET Technology
In 1987, Hieda et al. was developed the first multi-gate tran-
sistor [7]. According to this author, a fully depleted silicon
transistor has better switching due to the smaller body bias
effect. In 1989, Hisamoto et al. explained the first double gate
transistor called DELTA [8]. The structure of this delta was
similar to the FinFET structures. Due to degrading of SCEs
behavior of FinFET, it has increasing the attention over the
past decade planar MOSFETs [5, 9–13]. Figure 1 demon-
strates the superior SCEs performance of FinFETs over planar
MOSFETs with the similar channel length.

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Fig. 1 Drain induced barrier lowering (DIBL) and subthreshold swing
( ) as a function of effective channel length for double-gate (DG) n-type
FinFETs [14]
Vertical channels exist in FinFETs known as FIN whereas
planar MOSFETs are having horizontal channels as exposed
in Fig. 2. So width of channel of FinFETs is called Fin height.
Increase the number of fins corresponding charge density in-
creases in the channel. For the stability purposed, the height of
the fin is an important parameter means fin height should be
small. It provides a elastic composition measure up to to a
long fin structure [15, 16].
2.2 FinFET Classification
Based on the terminal, FinFET is classified into two main
classes: (1) shorted gate (SG) or 3T (terminals) FinFETs and
(2) independent-gate (IG) or 4T FinFETs. In SG FinFEs, both
gates are actually shorted but in IG FinFETs, the front gate and
back gate are physically isolated as shown in Fig. 3. In SG
FinFET, both gates are joined together and used to manage the
electrostatics of the channel. Therefore, higher ION and IOFF
flow in SG as compared to IG FinFETs. In IG FinFETs, we
can apply two different signals or voltages at the terminals.
That’s why it takes more area on the chip. IG FinFETs enables
the start voltage of the front gate (G1) to be increased or de-
creased by back gate (G2) to reach a higher range of ION/IOFF
Fig. 2 Structure of (a) Planar
MOSFET and (b) FinFET
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ratio (Fig. 4). For power management application, we can be
used IG FinFETs structure.
Equation 2.1 defined the relation of front gate (G1) thresh-
old voltage (VtG1) and back gate voltage. In this relationship,
we used charge sheet approximation [17].
V tG1 C Fin C ox2 3t ox1
¼  ð2:1Þ
V G2 C ox1 ðC Fin þ C ox2 Þ 3t ox2 þ FinWIDTH
Where Cox1 and Cox2 indicate the front and back gate oxide
capacitances and CFin = εsi /FinWIDTH is called depletion
capacitance.
FinFETs can be further categorized based on dielectric
thickness. (1) Double-gate (DG) FinFET and (2) Tri-gate
FinFET. Structure of DG and Tri-gate FinFETs are almost
same expect for the fact that in DG FinFET, the hardmask is
used at top portion of fin so that only two gate remains effec-
tive for the channel control as shown in Fig. 5(a).The effective
channel width off DG-FinFET is equal to [17].
Weff ¼ 2nFinheight ð2:2Þ
Where n indicate the total number of fin.
In Tri-gate, the third gate will be formed when the thick-
ness of dielectric on the top of the silicon fin is reduced as
shown in Fig. 5(b). So the Weff of the device is increased due
to the presence third gate. So that the effective channel width
of Tri-gate is equal to
Weff ¼ 2nFinheight þ Wfin ð2:3Þ
Where Wfin is the width of fin. Hence, Tri-gate FinFET has
smaller gate to source capacitance as compared to DG
FinFETs [18, 19].
3 Manufacturing Challenge of FinFETs
Due to the transitioning of the planar device technology to
FinFET technology, some important aspect of device
Silicon
Fig. 3 Design evaluation within (a) SG and (b) IG FinFET
technology is affected. Here some important aspects described
in this section.
3.1 Device Doping
Generally, no doping is required in FinFET channel. However
light doping is required for better control over the leakage
current and set the alternative threshold voltage. These doping
are done by implantation techniques. A high dopant requires
on the Source/Drain region. Due to the high dopant, the series
resistance of FinFET device is increased. So in this situation,
epitaxial growth is required to overcome this problem.
3.2 Crystal Orientation for Fin Surface
Mobility of the electrons and holes depend on surface orien-
tation as well as direction of current flow [20–22]. The rela-
tionship between electrons, holes mobility, and inversion lay-
er charge density are shown in Fig. 6. On the (100) orientation,
the electrons have the highest surface mobility and lowest
Fig. 4 Drain current of IG FinFET as a function of gate voltage (VG1) and
gate voltage (VG2). VG2 affects the ID vs. VG1 curves [11]
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surface mobility in (110) orientation. For holes have the
highest mobility in the (110) orientation and lowest in the
(100) orientation. For (111) surface orientation, mobility of
electrons and holes are lying between the (100) and (110)
surface orientation. The mobility variations are comes due to
surface scattering [21, 22].
3.3 Parasitic Capacitance of FinFETs
More number of parasitic capacitance is existing in FinFET
device as compared to the planar device. For smaller capaci-
tance fin height play an important role here means the increase
in the fin height and decrease in the fin pitch helps to reduce
the parasitic capacitance of FinFET [24, 25].
4 Approaches for Circuit Design of FinFETs
Conversion of planar device layout to three dimensional
FinFETs faces many challenges likes describing the
FinFETs width for digital style. In general we can say wider
devices have large number of fins. So effective width (Weff) of
FinFETs has to face redesign challenge. The height of all
FinFETs should be same on the wafer for ease of processing.
Taller fins provide more effective width as compared to planar
devices. Since we are using taller fins, parasitic capacitance
reduced.
For a DG-FinFETs, three configuration is indentified: (1)
Shorted gate (SG) mode (2) Low power (LP) mode, in this
mode back gate is biased in reverse mode to reduce the leak-
age power (3) Independed gate (IG) mode. In IG mode, dif-
ferent signals are used to drive the two gates of FinFETs. The
combination of LP and IG mode is also possible. In LP mode,

Fig. 5 (a) Double-gate FinFET
on SOI and (b) Tri-gate FinFET
on SOI
back gates are connected to positive voltage for P-FinFET and
to negative voltage for N-FinFET which reduces the leakage
and hence, subthreshold conduction. In this section, here four
types of digital logic structures are considered using FinFETs
and data or signals applied at input terminals of NAND gates
for evaluating the utility of the FinFET modes. The circuit
diagram of CMOS is shown in Figs. 7, 8, 9, 10, and 11 shown
the different type of FinFET modes based circuit diagram of
NAND gates.
Designing of NAND logic gate with the help of four dif-
ferent modes of FinFET, first the circuit diagrams replaced by
it’s layout styles and then estimating all parameters utilizing
the Microwind 2.6a tool. In the Microwind 2.6a tool, the func-
tion of layout styles can be drawn easily. First checked all
design rules before input connection. Lamda based design rule
is used for model. The parameters are explained likes ION
current and power dissipation respectively, thus they got low
power consumption in various modes and compared to the
CMOS NAND gate. The power dissipated values are exposed
in Table 1 at supply voltage vary from 0 to 5 V and the
equivalent graph is exposed [26].
Graph 1 Comparisons of ordinary CMOS, SP, LP, IG and IG/LP modes
logic circuits [26]
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5 Issues and Optimization Techniques
of SRAM Circuits
This section is very important for design the circuit based on
FinFET device. In this section we discussed the issues for
circuit design and also discussed the optimization techniques
likes threshold voltage optimization, fin shape and fin height
optimization etc.
5.1 Optimization of Supply and Threshold Voltage
For good SRAM cells, taking a fitting value of threshold and
supply voltage is a deciding factor. The supply voltage of
FinFET SRAM can be less than 0.5 volts because we want
to overcome the dynamic power without no discussed
delay parameter. But, the VDD scaling is directly linked
to the Vth scaling. OFF-current of the FinFET device is
increased when the Vth of the device is decreased. Also,
the stability of SRAM circuits declines when a decrease
in the Vth and VDD.
The variation in the threshold voltage of FinFET SRAM
device depends on the change in device fabrication, method
variety, the thickness of the body, line edge roughness, etc.
Changes in Vth of a pass-gate transistor, pull-up, and pull-
down can change the stationary noise margin (SNM) and
cause of route break. The Vth of dopingless channel FinFET
is calculated with the help of gate work function. With the
help of the inter-diffusion method, we can achieve a twin-
metal gate combination and a small threshold voltage [27].
Apply this method to the design of FinFET SRAM provides
a good noise margin (NM) when supply voltage (VDD) is
reduced. Regarding the power-performance optimization, we
can use particular method such as with unlike fin thickness, or
unlike channel materials [28].
Silicon
Fig. 6 Mobility of electrons and holes verses inversion layer charge density at different surface orientations [23]
5.2 Optimization of Fin Thickness and Fin Heights
For SRAM cell design, FinFETs offers the some advantage
over the planar device technology. Increased in drain current
would be good for SRAM circuits. Therefore increase the Weff
and fin height of the FinFET device.
In a mutual optimization reading of the supply voltage, fin
height, and Vth, the author achieved 87.0 % lower subthresh-
old leakage, 50.0 % gate outflow, 25.0 % active power, and
13.0 % larger SNM by applying 69.0 % taller fins [29]. Also,
this design gives 18.0 % lower supply voltage and 35.0 %
higher Vth. And this design also provides lower read stability
when we increased the fin thickness (Tfin). But write ability
voltage increases due to increase in fin thickness (Tfin). When
fin height (Hfin) is increases, we can say read stability are
decreases. If we want to neglect the effects of fin height on
read stability then fin thickness should be smaller.
Fig. 7 CMOS NAND gate [26]
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5.3 SRAM Based Others FinFETs
In this section, we will discuss the advantages of other types of
FinFET SRAM cells. In the case of supply voltage scaling,
Tunnel FinFET based SRAM circuit is better as compared to
other FinFETs SRAM circuits without increasing the static
power consumption [30]. For the studied of nonvolatile
SRAM cell, pseudo-spin-FinFET (PS-FinFET) is good as
compared to other types of SRAM cells [31]. The other types
of FinFET are called Junction less FinFET (JL FinFET). The
beauty of this FinFET is less process complexity than inver-
sion mode FinFET (IM FinFET). And the other beauty of JL
FinFET is good SCE and higher ON-OFF current ratio
[32]. In [33], the authors reported that in SRAM design
by JL FinFETs is required twice it has minimum Vcc as
compared with IM FinFETs SRAM. So we can say that
Fig. 8 SG mode NAND gate [26]

Fig. 9 LP mode NAND gate [26]
JL FinFET SRAM provides better performance when the
device scales down.
6 FinFET Domino Circuits for Low Power
Application
Due to high speed and smaller area compared to the CMOS
logic gates, domino circuits are found to be useful. Therefore,
large fan-in domino technology is available for huge memo-
ries and high‐speed processors applications. This technology
provides high speed and low noise margin (NM) as compared
to CMOS logic. The sensitivity of domino logic circuit is
increases due to low noise margin. By down-scaling the tech-
nology, we can be increased the noise immunity of this cir-
cuits. Domino OR gates are considered and simulated for
existing technology but projected techniques are used for
CMOS and FinFET technology. Simulation is shown on the
32 nm pre-dictive technology model (PTM) node using
Fig. 10 IG mode NAND gate [26]
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HSPICE (http://ptm.asu.edu/modelcard/2006/32nm_bulk.
pm, http://ptm.asu.edu/modelcard/32nm_finfet.rar).
The proposed circuit are divided in two modes likes, short
gate (SG) mode, and low power (LP) mode as exposed in
Figs. 12 and 13 correspondingly. This proposed circuit have
two phases. (1) Precharge phase and (2) Evaluation phase.
(1) Precharge phase - Working on this phase, first, we apply
the active low clock. So transistor P1 is turned on. Then
the dynamic node gets charged up to Vdd with help of P1
and due to the inverter gets low output. The output is
connected to another transistor P2 means keeper transis-
tor. So P2 is ON and transistor N1 is turned OFF. At this
time input is not affected by the output because N1 is
OFF. If more than one inputs of the evaluation block are
high, then we can say voltage at node N is the same as
Vdd or dynamic node voltage. This time N3 becomes
OFF and N2 turned ON because of the node N has high
voltage. Therefore we can say no contact between
ground (GND) and dynamic node means noise margin
(NM) of proposed domino circuit is increases and power
consumption decreases.
(2) Evaluation phase - In this phase clock is active high. The
working of this phase is opposite to the precharge phase.
If inputs of evaluation block are high. N channel FinFET
is turn ON. We can say a dynamic node is directed con-
nected to the GND therefore voltage of the dynamic node
goes down and it becomes low. At this time output be-
comes high. Then N3 is turn ON and N2 becomes OFF
due to node N is low voltage. So leakage current reduces
with help of dynamic node and ground.
The SG mode of proposed domino logic circuit has highest
power drop is 43.45 % compared to conditional stacked
Fig. 11 IG/LP mode NAND gate [26]
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Table 1 Observations of power

(in mw) for ordinary CMOS Voltage CMOS SG-mode LP-mode IG-mode IG/LP-mode
NAND gate and NAND gate of NAND NAND NAND NAND NAND
different mode of FinFET [26] Vdd (v) Power (in mw) Power (in mw) Power (in mw) Power (in mw) Power (in mw)

0.5 0.000 0.000 0.007 0.002 0.001

1.0 0.006 0.001 0.005 0.003 0.001
1.5 0.006 0.002 0.004 0.004 0.001
2.0 0.007 0.002 0.004 0.006 0.001
2.5 0.009 0.003 0.004 0.007 0.002
3.0 0.011 0.004 0.004 0.008 0.002
3.5 0.012 0.004 0.004 0.009 0.002
4.0 0.014 0.005 0.004 0.010 0.002
4.5 0.015 0.005 0.004 0.011 0.002
5.0 0.016 0.005 0.004 0.012 0.003

keeper domino logic (CSK-DL) and LP mode of this tech-
nique has maximum delay reduction is 38.66 % as compared
to coarse-mesh finite difference (CMFD) technique at fre-
quency of 200 MHz [34].
7 Conclusions
In this review paper, we have explained the benefits of
FinFET technology over the planar MOSFET technology,
such as FinFET has smaller SCEs as compared to planar de-
vices. This paper also discussed manufacturing challenges like
Fin orientation, doping of FinFET device, and parasitic capac-
itances. SRAM-based circuits design, issues, and important
optimization like Fin thickness, supply, and threshold voltage
optimization are also addressed in this review paper. For low
power application we have discussed FinFET domino circuits.
In SG mode, the highest power drop is 43.45 % as compared
to CSK-DL technique and in LP mode, the maximum delay
reduction is 38.66 % as compared to CMFD technique.

Fig. 12 Proposed logic circuit using SG mode of FinFET technology

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Fig. 13 Proposed logic circuit using LP mode of FinFET technology
Acknowledgements The authors acknowledge the Microelectronics
Computational Laboratory, Department of Electronics and
Communication Engineering, National Institute of Technology Silchar,
India for providing all necessary facilities to carry out the research work.
Author Contributions The first author has written and documented the
paper and the second author collected the research material, checked, and
modified the technical content.
Funding Young Faculty Research Fellowship scheme under Digital
India Corporation.
Data Availability All sources of data are from reference cited in the paper.
Declarations The work has maintained ethical standard.
Conflict of Interest There is no conflict of interest.
Consent to Participate The authors agree to participate.
Consent for Publication The authors agree with the copyright policy of
the journal.
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