VLSI Technology and Device Modeling: Text and Reference Books

EEE 6404
VLSI Technology and Device

Modeling
EEE 6404 Dr. Apratim Roy 1
Text and Reference Books
1) S. M. Sze, VLSI Technology, 2nd Edition.
2) S. A. Campbell, The Science and Engineering of

Microelectronic Fabrication, 2nd Edition.
3) R. C. Jaeger, Introduction to Microelectronic Fabrication,

1st/2nd Edition.
4) D. A. Neaman, Semiconductor Physics & Devices: Basic

Principles, 3rd Edition.
5) Weste, Harris & Banerjee, CMOS VLSI Design, 3rd Edition.
1
EEE 6404
Introduction (Industry
Trend)
Introduction (Industry Trend)

 The factory sales for the electronic industry has increased
by a factor of 15 between 1960-1990 and the trend has continued
in this century.
 The integrated circuit (IC) market has increased at an even

higher rate.
Samsung Electronics Annual

Sales Trend (in Korean Won)
2
 Reasons behind this trend: pervasiveness of electronic
products and technological breakthroughs in integrated circuits.
 In many cases, electronic sales volume has surpassed the

automobile, chemical and steel industries.

 In earlier times, the IC market was dominated by bipolar
transistors.
 In recent times, digital MOS ICs have dominated the

market due to available device miniaturization, low power
requirement and high yield.
3
Industry Trend:
Device Miniaturization
 Since 1960, the annual rate of reduction of feature size has
been around 13% which has led to shrinking of feature length
from 1 μm to 0.1 μm and beyond.
Industry Trend:
 Device miniaturization results in reduced cost per function
and cost per bit of memory chips has dramatically reduced over
the years.
4
Industry Trend:
 Device miniaturization also

leads to reduction in power
consumption.
 Device speed has improved

which has expanded IC
throughput rates.
 Therefore, energy dissipated

per logic gate (power delay
product) has decreased over
the years.
Industry Trend:
 Movement in level of IC integration:
SSI to MSI to LSI to VLSI to ULSI
5
Industry Trend:
EEE 6404
Wafer Preparation
Ref: S M Sze, Online Resources
6
VLSI Technology
Semiconductor Technology:
Why Si?
 Silicon (Si) accounts for over 95% of all semiconductor
devices.
 Silicon is found naturally in abundant amounts in the form

of silica (quartz, SiO2) and silicates ( [SiO4]4− [Si2O7]6− etc).
Quartz is the second most-abundant mineral in Earth's
continental crust (behind Feldspars: KAlSi3O8 – NaAlSi3O8 –
CaAl2Si2O8).
 Si is one of the most studied elements in the periodic

table.
7
Semiconductor Technology:
Why Si over Ge?
 Si (band gap 1.1eV) can be better than Ge as Ge is
unsuitable for certain applications (has high junction
leakage currents due to narrow band gap 0.66eV).
 Si can operate up to 150°C and Ge can operate up to

100°C.
 Undoped (intrinsic) resistivity of Ge is about 47 Ω-cm and

for Si it is about 230,000 Ω-cm.
 Electronic grade germanium is more expensive than

silicon. The mentioned reasons also contributed behind Si’s
dominance over compound semiconductors.
Raw Material for Wafer:

Electronic-Grade Silicon (EGS)
 Electronic-grade silicon (EGS) is a polycrystalline
material of high purity
 Its is the raw material for preparing single-crystal silicon

(base material for silicon chips)
 Its major impurities are boron (B), carbon (C) and

residual donors. Pure EGS requires dopants in parts per
billion range (ppb) and carbon in <2 ppm range
 Obtaining EGS from natural silicon sources is a multistep

process
8
EGS Production:
Quarzite/Sand to MGS
First Step of EGS Production:

Quarzite/Sand to Metallurgical-grade silicon (MGS) 1.
SiO2 + C  SiO + C
 A submerged-electrode arc furnace is used. It is charged with SiO + 2C  SiC + C
quartzite (white/grey quartz sandstone), a relatively pure form of
SiO + CO  SiO2 +
sand (SiO2), and carbon (in the form of coal, coke & wood chips)
SiC + SiO2  Si + S
 SiC (solid) + SiO2 (solid) → Si (liquid) + SiO (gas) + CO (gas) SiC (solid) + SiO2 (s
(liquid) + SiO (gas)
2.
 The produced MGS is drawn SiO2(solid) + 2C(sol
off and solidified (at 98% purity) Si(liquid) + 2CO(gas
9
EGS Production:
MGS to EGS
2nd Step of EGS Production:

MGS to Trichlorosilane
 The MGS is pulverized mechanically and reacted with
anhydrous HCl to form Trichlorosilane (SiHCl3).
Si (solid) + 3HCl (gas) → SiHCl3 (gas) + H2 (gas) + heat
 SiHCl3 is liquid at room temperature (boiling point 32°C)

and has many unwanted chlorides. So, purification is done
by fractional distillation.
 EGS is prepared from purified SiHCl3 in a chemical

vapor deposition (CVD) process.
2SiHCl3 (gas) + 2H2 (gas) → 2Si (solid) + 6HCl (gas)

10
3rd Step of EGS Production:
Trichlorosilane to EGS (via CVD Reactor)
 A heated rod of
silicon (called a slim
rod, ~4mm diameter)
serves as the
nucleation point for the
deposition of Si. Si slim rods
 A complete process
results in rods of
polycrystalline EGS
(up to 0.2m or more in
diameter and meters in
length). A polycrystalline EGS
rod made by the
Siemens process
Summary of Preparation of
EGS from Trichlorosilane
11
EGS Production Summary:
A Multistep Process
 Quartzite, sand, coal/coke/wood-chips → MGS →
Trichlorosilane (SiHCl3) → Distillation → CVD with
Recovery → EGS
Wafer Production:
 Worldwide consumption of EGS was 5×106 kg in the

nineties.
Important Crystal Properties
12
Important Crystal Properties:
Crystal Structure (Orientation)
 Many of a single crystal's structural and electronic properties are highly
anisotropic (orientation dependent). So, material properties of Si wafers often
depend on crystal structures and their orientation. (100) or (111) oriented
materials are commonly used for silicon.
 The {111} planes have the highest atomic density on the surface, therefore,
crystals grow most easily on these planes.
 The {111} planes oxidize faster than

{100} planes.
 Ion implantation depth depend on

the wafer's crystal orientation.
 Historically, bipolar devices have

preferred <111> oriented materials
whereas MOS devices have preferred
<100> oriented materials.

Defects in Real Crystal
 Real crystals may manifest four types of defects:
1) Point Defects
2) Line Defects (Dislocations)
3) Area (Planar) Defects
4) Volume Defects
13
Forms of Point Defects
 Any non-silicon atoms incorporated into the lattice at either a

substitutional site or an interstitial site is considered a point defect.
 Missing atoms create a vacancy which is called a “Schottky defect”.
 A silicon atom at an interstitial site associated with a vacancy is

called a “Frenkel defect”.

Point Defects
 Using principles of thermodynamics, defect concentration can
be given as a function of temperature (Arrhenius Relation):
N d  A exp(  Ea / kT )
 Point defects are important in the kinetics of diffusion and
oxidation (more about this later).
14
Line Defects (Dislocations)
 A missing line or an
additional line of atoms is
called a line defect
(dislocation).
 There are two typical

forms of dislocations:
edge dislocations and
screw dislocations.
 The figure shows an

edge dislocation in a
cubic crystal.

Line Defects (Dislocations)
 Dislocations in a lattice are dynamic defects. That is, they

can diffuse under applied stress, dissociate into two or more
dislocations, or combine with other dislocations.
 Crystals for IC usage are generally free of dislocations but may

contain small dislocations loops from excess point-defect
condensation.
 Edge type dislocations are also introduced by thermal stress

on the wafer during processing.
 Dislocations in devices are generally undesirable, because

they act as sinks for metallic impurities and alter diffusion profiles.
15
Edge Dislocations (Cubic Crystal)

Screw Dislocations (Cubic Crystal)
16
Glide of a Dislocation
(Dynamic Defect)

Area Defects (Planar Defects)
 There are two typical forms of area or planar defects:

Twins and Grain Boundaries.
 Grain boundaries are more disordered than twins.
 Planar defects appear during crystal growth, but crystals

having such defects are not considered usable for
integrated circuits and discarded.
17
Area Defects (Crystal Twinning)
 Twinning represents
a change in the
crystal orientation
across a twin plane,
such that a certain
symmetry exists
across the plane.
Twinned pyrite (FeS2) crystal

Area Defects (Grain Boundaries)
 A grain boundary
represents a
transition between
crystals having no
particular orientation
relationship to one
another, that is the
crystal structure on
either side of a grain
boundary is different.
Grain boundaries in SrTiO3
18
Volume Defects
 In silicon, volume
defects typically result from
precipitates of impurity or
dopant atoms.
 Most impurities have a

retrograde solubility in Si,
which is defined as a
solubility that decreases
with decreasing
temperature.
Volume Defects
 Thus, if an impurity is introduced (at a

temperature T1) at the maximum
concentration allowed by its solubility and the
crystal is then cooled (to a lower temperature
T2), a supersaturated condition is said to
exist.
 The crystal achieves an equilibrium state

by precipitating the impurity atoms in excess
of the solubility level as a second phase, that
is, as a material of different composition and
structure.
 These precipitates are generally

undesirable because they act as sites for
dislocation generation.
EEE 6404 Dr. Apratim Roy

38
19
Wafer Production:
EGS to Si Crystal (Ingot)
EGS to Si Crystal:
Crystal Growing (Czochralski Process)
 The Czochralski (CZ) process is a method of crystal growth used to
obtain crystals of semiconductors.
 It is named after Polish chemist Jan Czochralski and is used to grow

most of the crystals from which Si wafers are produced.
 It involves dipping a small single-crystal seed into molten silicon

(named melt) and slowly withdrawing the seed while rotating it
simultaneously.
Jan Czochralski
20
Czochralski Process (Overview)
Czochralski Process (Crystal Growing)
 The growth of a CZ
crystal involves
solidification of atoms
from a liquid phase at an
interface.
 The figure shows the

transport process and
temperature gradients.
21
Czochralski Process
(Temp Gradient in a grown Crystal)
Czochralski Process (Crystal Growing)
 The macroscopic heat transfer

condition at the interface is modelled
as
dm dT dT
L  kl A1  k s A2
dt dx1 dx2
Here,
 L=latent heat of fusion (J/gm),
 dm/dt=mass solidification rate,
 Kl, Ks=thermal conductivity of liquid
and solid [W/(mm. K)],
 dT/dx1 and dT/dx2=temperature
gradients at points 1 and 2,
 A1 and A2=area of the isotherms at
points 1 and 2
22
Czochralski Process (Pull Rate)
 Maximum pull rate of a crystal

k s dT
Vmax 
Ld dx
Here,
 d=density of solid Si
(gm/mm3),
 L=latent heat of fusion (J/gm),
 Ks=thermal conductivity of
solid [W/(mm. K)],
 dT/dx=temperature gradient,
 Vmax= maximum pull rate
(pull speed, mm/min)
Czochralski Process (Pull Rate)
 Pull rate influences the

incorporation of
impurities into the
crystal and is a factor
in defect generation.
 Generally, pull rate

inversely varies with
the diameter and
experimental pull rates
are slower that
theoretical predictions.
23
Czochralski Process (Impurities)
 In the Czochralski Process, impurities are introduced to the silicon
ingot both intentionally and as a by-product.
 Intentionally added dopants are mixed into the melt during crystal
growth.
 Unintentionally added impurities may originate from the crucible.
 All impurities have a solid solubility in silicon and a different

equilibrium solubility in the melt.

 An equilibrium segregation coefficient K0 is defined as
K0=Cs/Cl,
where Cs and Cl are the equilibrium concentrations of the impurity in
the solid and liquid near the interface, respectively.
 The coefficients in the table are below unity, implying that the
impurities are left in the melt during growth and, therefore, the melt
becomes progressively enriched with these impurities.
24
 The distribution of an impurity in the grown crystal can be

described by the normal freezing relation:
Cs  k0C0 (1  X ) k0 1
Here,
 X is the fraction of the melt solidified,
 C0 is the initial melt impurity concentration,
 Cs is the solid impurity concentration and
 k0 is the segregation coefficient.
Cs  k0C0 (1  X ) k0 1
Impurity profiles for different

values of k0 with C0= 1
25
Impurity profiles for
B, P, As and Sb
Cs  k0C0 (1  X ) k0 1
Cs
  k0 (1  X ) k0 1
C0
Note the relatively flat profile

produced by boron with a
ko close to 1. Dopants with
ko << 1 (like Sb) produce
much more doping variation
along the crystal.
 Experimental segregation coefficients differ from equilibrium

values, so the effective segregation coefficient is defined
as:
k0
ke 
k0  (1  k0 ) exp(VB / D)
Here,
 V is the growth velocity (pull rate),
 D is the diffusion coefficient of dopant in melt, and
 B is the boundary layer thickness.
26
Czochralski Apparatus (Puller)
A Czochralski crystal growth

apparatus (a “puller”) may be made
with four subsystems:
1. Furnace: crucible, susceptor

(crucible support) and rotation
mechanism, heating element,
power supply, chamber
2. Crystal pulling mechanism:
seed shaft, rotation mechanism,
and seed chuck
3. Ambient control: gas source,
flow control, purge tube, and
exhaust/vacuum system
4. Control system:
microprocessor and sensors
Czochralski Apparatus (Puller)
27
Czochralski Apparatus and Products
A commercial CZ puller Early in the growth process Later in the growth process
Czochralski Products
(Ingots/Boules)
28
Czochralski Apparatus (Crucible)
 Crucible is the most important

component of the Czochralski
Apparatus.
 The crucible material should be

chemically inert with molten
silicon.
 It should have high melting

point, thermal stability, and
hardness. It should also be
inexpensive and reusable.
Czochralski Apparatus (Crucible)
 The crucible materials in use

are silicon nitride (Si3N4), graphite
and fused silica (SiO2).
 Fused silica can react with

silicon and lead to dissolution of
crucible.
29
Dissolution of Crucible:
Oxygen in Silicon
 As mentioned, CZ-Si crystals are grown
typically in a fused silica (SiO2)
crucible.
 The crucible reacts with hot silicon and
releases oxygen into the melt. So,
oxygen in Si arises from dissolution of
crucible.
 Typical values of oxygen concentration
is 5*1017 to 1018 atoms/cm3.
 The axial distribution of oxygen is
governed by the amount of oxygen in
the melt. Less dissolution of the
crucible occurs as the melt volume
diminishes, and less oxygen is
available for incorporation (see the
figure).
Axial distribution of O2 in a Cz-Si ingot
Oxygen in Silicon
 Oxygen impurity in Si can have three effects:
(1) Oxygen forms a thermal donor in silicon (donor

formation).
(2) Oxygen increases the mechanical strength of silicon
(yield strength improvement).
(3) Oxygen precipitation leading to defect generation which
provides gettering sites for unintentional impurities.
30
Oxygen in Silicon:
Yield Strength Improvement and Oxygen Precipitation
 Over 95% of oxygen atoms in Si

occupy interstitial lattice sites
which act to increase the yield
strength of Si (by up to 25%
compared to O2 free Si).
 This beneficial effect increases

until oxygen begins to precipitate
which typically occurs when the O2
concentration exceeds the
threshold of 6.4*1017 atoms/cm3.
 Precipitation is a function of crystal

doping level. At sufficient doping
levels, oxygen precipitation is
suppressed.
Oxygen in Silicon:
Donor Formation
 A smaller percentage of oxygen in Si polymerizes into

complexes such as SiO4 in the temperature range of
400°C to 500°C.
 They act as a thermal donor and change the resistivity of

the crystal.
31
Oxygen in Silicon (Defect Generation)
 Oxygen precipitates represent a strain on the lattice which is

relieved by a variety of defects which may include stacking
faults (a type of crystal defect).
Oxygen in Silicon (Defect Generation)

 These defects can capture harmful mobile impurities (which may
increase junction leakage currents) by a process called gettering.
 Defects formed in the interior of the wafer getter unintentional

impurities (internal gettering) from the surface region where device
junctions are located.
32
Carbon in Silicon
 The CZ growth process inherently introduces oxygen in Si from

the SiO2 crucible. It may also introduce carbon in Si from
graphite susceptor/supporter and graphite crucible.
 Typically, amount of C in Si is smaller than amount of oxygen in

Si. Generally, CO ≈ 1017 ~1018 cm-3 and CC ≈ 1016 cm-3.
Crystal Characterization
33
Crystal Characterization:
Evaluation of Crystals
 Routine evaluation of ingots or boules involves
1. testing the resistivity,
2. evaluating their crystal perfection,
3. examining their mechanical properties, such as size and mass.
 Less routine tests include the measurement of carbon, oxygen,

and heavy metals in the crystal.
 The crystal is inspected visually where gross crystalline

imperfections (like twinning) are detected and defective sections
are cut from the boule. Si loss at this step can reach up to 50%.
 Defects like dislocations can be revealed by preferential etching

for a section of the ingot.
Four point probe Measurement
 Resistivity measurements are made
on the flat ends of the crystal by the
four-point probe technique.
 Current I (mA) is passed through the

outer probes and voltage V (mV) is
measured between the inner probes.
 If S is probe spacing (in cm), the

measured resistance (V/I) is
converted to resistivity (Ω-cm) using
the formula:
ρ= (V/I)2πS
34
Four point probe Measurement
Relation between resistivity and doping density
 The resistivity of a material is
related to the doping density
through the carrier mobility.
  q( n n   p p)
1 1
 
 q ( n n   p p )
 Dopant atoms (donors and

acceptors) increase the number
of negative or positive charge
carriers which increases the
material's conductivity (and
decreases its resistivity).
35
Crystal Characterization: Example
Problem: A boron doped crystal is measured at its seed end with a four point probe of spacing 1 mm. The reading
(V/I) is 10 ohms. What is the seed end doping and the expected reading at 0.95 fraction solidified?
Solution:
Here, S=1 mm=0.1 cm, V/I = 10 ohms
Resistivity reading, ρ
= (V/I)2πS = 10×2×π×0.1 = 6.3 Ω-cm
The figure shows doping at this

resistivity is 2×1015 atoms/cm3
For B, k0 (segregation coefficient)=0.8
Cs  k0C0 (1  X ) k0 1
2×1015 = 0.8×C0×(1−0)0.8−1
So, C0= 2.5×1015 atoms/cm3
When X=0.95
Cs  k0C0 (1  X ) k0 1
= 0.8× 2.5×1015 ×(1−0.95)0.8−1
So, Cs= 3.6×1015 atoms/cm3 (Ans)
The figure shows at this doping

resistivity is ~5 Ω-cm and V/I = (5/2×π×0.1)=7.95 ohms (Ans) EEE 6404 Dr. Apratim Roy
71
Wafer Production:
Si Ingot to Si Wafer (Silicon Shaping)
36
Wafer Preparation:
Silicon Shaping
 Silicon is a hard and brittle material. The most suitable material for
shaping and cutting silicon is industrial-grade diamond.
 Conversion of silicon ingots into polished wafers typically requires

6 machining, 2 chemical, and 1~2 polishing operations.
Wafer Preparation:
Silicon Shaping (Ingots to Wafer)
37
Silicon Shaping (Step 1: End Cutting)
 In the 1st shaping step, the ingot is cut mechanically to remove

seed and tang ends. Portions that fails resistivity and perfection
evaluation are also cut away.
Silicon Shaping (Step 2: Grinding)
 Surface grinding defines the diameter of the material. A

rotating cutting tool makes multiple passes down a rotating
ingot until the chosen diameter is achieved.
38
Silicon Shaping (Step 3: Flats)
 After diameter grinding, one or more flats
are grounded along the length of the
ingot.
 The largest flat, called the "major" or

"primary" flat, is usually relative to a
specific crystal orientation. The flat is
located by x-ray diffraction techniques.
 The primary flat serves as a mechanical

locator in automated processing
equipment to position the wafer, and also
serves to orient the IC device relative to
the crystal.
 Other smaller flats are called "secondary"

flats which serve to identify the orientation
and conductivity type of the wafer.
Silicon Shaping (Step 3: Flats)
P type <111>
No secondary Flat
P type <100>
90°±5° Clockwise from Primary Flat
N type <111>
N type <100>
39
Silicon Shaping (Step 4: Slicing)
 Slicing determines four important
wafer parameters:
1) Wafer thickness (depends on wafer

diameter)
2) Taper (variation in wafer thickness

from one end to another)
3) Bow (surface curvature of the wafer

measured from the center of the
wafer to its edge)
4) Surface orientation
 Wafer thickness (depends on wafer diameter)
 Taper (variation in wafer thickness)
40
 Bow (curvature of wafer surface measured from wafer center

to wafer edge)
 Surface orientation: <100>  <111> silicon are typically cut

wafers are typically cut “on axis”. as “off-axis” wafers.
Industry conventions for cutting off-axis wafers.
41
Silicon Shaping (Step 5: Lapping)
 During slicing, approximately

one-third of the crystal may be
lost as sawdust.
 If the cut wafer varies enough

in thickness it may warrant an
additional mechanical two-
sided lapping operation.
 It is performed under pressure

using a mixture of Al2O3 and
glycerine. It produces a
flatness uniform to within 2 μm
and removes around 20 μm
per side.
Silicon Shaping
(Step 6: Edge Contouring)
 The final shaping step is edge contouring where a radius is
ground on the rim of the wafer.
 Edge rounded wafers develop fewer edge chips during device

fabrication. At chip locations, dislocation and fracture can be
introduced.
42
Silicon Etching
 The silicon shaping operations leave

the surface and edges of the wafer
damaged and contaminated.
 These regions (on the order of 10 μm

deep) can be removed by chemical
etching.
 Acidic etching may use mixtures of

hydrofluoric, nitric and acetic acids and
alkaline etching may use potassium or
sodium hydroxide.
 It typically removes around 20 μm per

side.
Silicon Polishing (CMP)

 Polishing is often the final step of wafer production. Its purpose is to provide a
smooth, mirror-like surface on which device features can be photoengraved.
 Polishing can take the form of CMP which is both a chemical and mechanical
process. Wafers are mounted on a fixture, pressed against a polishing pad
(made with artificial fabric) under high pressure, and rotated relative to the
pad. During the process, a mixture of polishing slurry and water is dripped
onto the pad.
43
Final Product:
Si Wafers
Silicon wafers:
Diameter: typically
50~300 mm (2~12 inches)
Thickness: ~300-800μm
2-inch (51 mm), 4-inch (100 mm), 6-inch

(150 mm), and 8-inch (200 mm) wafers
Process Considerations
44
Process Considerations: Impurities
 Process considerations are necessary to maintain the purity of

the wafer material.
 Many VLSI circuits require low junction leakage current. But

metallic impurities may act as conductive impurities and
provide shorts between emitter and collector of bipolar
transistors (“pipe effect”). The precipitated form of these
impurities are usually silicides (silicides are silicon and metal
compounds which are conductive similar to metals).
Process Consideration: Gettering

 “Gettering” is the process that removes harmful impurities or defects from
device regions of the wafer.
 Gettering Technique (1): Intentionally damaging wafer surface (by
mechanical abrasion methods or focused heat beam). It creates dislocation
centers during thermal processing which work as trapping sites for fast-
diffusing impurities.
 Gettering Technique (2): “Intrinsic gettering” uses defects generated by
oxygen precipitation as trapping sites. It uses thermal cycles to promote the
formation of precipitates and defects in the interior of the wafer.
45
Process Consideration: Gettering
 Gettering Technique (3): Depositing around 1um of polysilicon

on the wafer after etching and prior to polishing. The grain
boundaries of polysilicon is able to retain metallic
contamination.
 Gettering improves junction leakage current and influences

gate oxide quality.
Process Consideration: Thermal Stress
 When the wafer is removed from a hot furnace, the wafer

edges cool rapidly by radiation but the wafer center remains
hot. This temperature gradient creates a thermal stress (S):
S  aET
 Here, a=coefficient of thermal expansion (℃−1)
 E = Young’s modulus (N/m2), Δ(T)=temperature difference (℃)
 If this stress exceeds the yield strength (critical shear stress) of

material, dislocations are formed.
 Stress is kept acceptable by slow withdrawal of wafers from

furnace or by lowering furnace temperature.
46
Process Consideration: Thermal Stress
 Oxygen precipitates
can reduce the critical
shear stress (yield
strength) of wafers.
Wafer Preparation:
Visualization of Different Steps
47
Wafer Preparation: Summary
Assignment
S. M. Sze, VLSI Technology, Chapter 1, Problem 1

48

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EEE 6404

VLSI Technology and Device

EEE 6404 Dr. Apratim Roy 1

Text and Reference Books

1) S. M. Sze, VLSI Technology, 2nd Edition.

2) S. A. Campbell, The Science and Engineering of

3) R. C. Jaeger, Introduction to Microelectronic Fabrication,

4) D. A. Neaman, Semiconductor Physics & Devices: Basic

5) Weste, Harris & Banerjee, CMOS VLSI Design, 3rd Edition.

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Introduction (Industry Trend)

 The integrated circuit (IC) market has increased at an even

Samsung Electronics Annual

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 In many cases, electronic sales volume has surpassed the

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Introduction (Industry Trend)

 In recent times, digital MOS ICs have dominated the

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 Device miniaturization also

 Device speed has improved

 Therefore, energy dissipated

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 Silicon is found naturally in abundant amounts in the form

 Si is one of the most studied elements in the periodic

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 Si can operate up to 150°C and Ge can operate up to

 Undoped (intrinsic) resistivity of Ge is about 47 Ω-cm and

 Electronic grade germanium is more expensive than

Raw Material for Wafer:

 Its is the raw material for preparing single-crystal silicon

 Its major impurities are boron (B), carbon (C) and

 Obtaining EGS from natural silicon sources is a multistep

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First Step of EGS Production:

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2nd Step of EGS Production:

Si (solid) + 3HCl (gas) → SiHCl3 (gas) + H2 (gas) + heat

 SiHCl3 is liquid at room temperature (boiling point 32°C)

 EGS is prepared from purified SiHCl3 in a chemical

2SiHCl3 (gas) + 2H2 (gas) → 2Si (solid) + 6HCl (gas)

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 Worldwide consumption of EGS was 5×106 kg in the

Important Crystal Properties

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 The {111} planes oxidize faster than

 Ion implantation depth depend on

 Historically, bipolar devices have

Important Crystal Properties:

 Real crystals may manifest four types of defects:

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 Any non-silicon atoms incorporated into the lattice at either a

 Missing atoms create a vacancy which is called a “Schottky defect”.

 A silicon atom at an interstitial site associated with a vacancy is