2/22/2022

Palestine Polytechnic University

College of IT and Computer Engineering
Computer Systems Engineering

Embedded Systems
Ch5: AVR and ARM Architectures
Other MCU Architectures
Dr. Mohammed Aldasht
Spring 2022

AVR ARCHITECTURE
• AVR stands for Alf and Vegard's RISC processor
• AVR MCUs are popular MCUs used in project prototyping and embedded
devices.
• AVR is a 8-bit RISC architecture microcontroller in market since 1996
• Having on-chip: Programmable flash memory, SRAM, IO data space & EEPROM.
• AVR is the first MCU in market which has on-chip flash storage.

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Block Diagram
According to The
Datasheet

• 32 KB flash memory, 32K

× 8B (32768 Bytes) flash
is organized in 16K ×
16B (32768 Bytes).
•a PC (which stores
address of the currently
executing location of the
flash) of 14 bits is
sufficient.

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• GPRs, I/O Space & SRAM

memory space: These memories
are different in nature but having
a continuous space
(logically) inside the MCU.
• GPRs have special names as R0
up to R3; the last 6 register in this
series of registers (R26 up to
R31) have special names XL, XH,
YL, YH, ZL & ZH

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PROGRAM EXECUTION & CLOCK

• During a single clock pulse, the following things happen:
• Step 1. Fetches the command/Instruction at the address of the flash memory
pointed by PC.
• Step2. The binary machine code then gets decoded by a "Instruction
Decoder".
• Step 3. After figuring out the command/Instruction, the ALU starts
performing the operation corresponding to the machine code.
• Step 4. The ALU increases the PC by 1.
• Step 5. Goto Step 1.

ATMEGA328P
• ATmega328P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
(RISC) architecture, has the following:
• 32 KBytes of In-System Programmable (ISP) flash to store programs
• 2 KBytes SRAM to hold run-time variables,
• 1 Kbytes EEPROM to store any data that programs may wish to retain after power is cycled,
• 23 general purpose input/output (GPIO) lines,
• 32 general purpose working registers,
• 3 Timer/Counters with compare modes,
• Internal and external interrupts,
• Universal Synchronous/Asynchronous Receiver/-Transmitter (USART),
• 2-wire Serial Interface (TWI) serial port,
• Serial Peripheral Interface (SPI) serial port,
• 6-channel 10-bit Analog/Digital Converter (ADC).

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ATMEGA328P BLOCK DIAGRAM

AVR CPU CORE

• AVR uses a Harvard architecture
with physically separate storage
and buses for program and
data.
• von Neumann architecture
operates with a single storage
structure to hold both program
and data.

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AVR ARCHITECTURE

• Harvard architecture
• Flash – program memory
• 32K

• SRAM – data memory

• 2K

• EEPROM
• For long-term data
• On I/O data bus

MEMORY

• Flash (32K) (15-bit addresses)

• Program memory – read only
• Non-volatile
• Allocate data to Flash using PROGMEM keyword
• SRAM (2K)
• Temporary values, stack, etc.
• Volatile
• Limited space!
• EEPROM (1K)
• Long-term data

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AVR CPU

• Instruction Fetch and

Decode
• ALU Instructions
• I/O and special
functions

AVR REGISTER FILE

• 32 8-bit GP
registers
• Part of SRAM
memory space

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SPECIAL ADDRESSING REGISTERS

• X, Y and Z registers
• 16-bit registers made using registers 26 – 31
• Support indirect addressing

AVR MEMORY

• Program memory – Flash

• Data memory - SRAM

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ADDRESSING MODES

• Direct register addressing

ADDRESSING MODES

• Direct I/O
addressing

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ADDRESSING MODES

• Direct data
memory
addressing

ADDRESSING MODES

• Direct data
memory with
displacement
addressing

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ADDRESSING MODES

• Indirect data
memory
addressing

SRAM READ/WRITE TIMING

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STACK POINTER REGISTER

• Special register in I/O space [3E, 3D]
• Enough bits to address data space
• Initialized to RAMEND (address of highest memory address)

• Instructions that use the stack pointer

PROGRAM STATUS REGISTER (SREG)

• Status bits set by instructions/Checked by Branch/Skip instructions

• I – Global interrupt enable
• T – Flag bit
• H – Half carry (BCD arithmetic)
• S – Sign
• V – Overflow
• N – Negative
• Z – Zero
• C – Carry

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SREG - AVR STATUS REGISTER

• I: Global Interrupt Enable

• T: Bit Copy Storage
• H: Half-Carry.
• S: Sign Bit. The S-bit is always an exclusive-
OR between N and V.
• V: Two’s Complement Overflow.
• N: Negative. The N-bit indicates a negative
result.
• Z: Zero. The Z-bit indicates a zero result

SIMPLE 2-STAGE PIPELINE

• Branch/Skip??

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SINGLE-CYCLE ALU INSTRUCTIONS

• Most instructions execute in one cycle
• Makes program timing calculations (relatively) easy
• No cache misses
• 1 clock/instruction

ADDRESSING MODES

• JMP, CALL – Direct Program

Memory Addressing

• IJMP, ICALL – Indirect

program memory addressing

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ADDRESSING MODES

• RJMP, RCALL –
Relative program
memory addressing

APPENDICES A, B AND C

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ATMEGA328P PIN CONFIGURATIONS

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ATMEGA328P PIN
CONFIGURATIONS

ATMEGA328P
ASSEMBLY
INSTRUCTIONS

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ATMEGA328P ASSEMBLY INSTRUCTIONS

ATMEGA328P
ASSEMBLY
INSTRUCTIONS

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ATMEGA328P
ASSEMBLY
INSTRUCTIONS

ATMEGA328P
ASSEMBLY
INSTRUCTIONS

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ATMEGA328P
ASSEMBLY
INSTRUCTIONS

ARM ARCHITECTURE
• ARM (Advanced RISC Machines)
• Arm Ltd. develops the architecture which includes system on a
chip (SoC) design, that incorporate different components such as
memory, and interfaces.
• ARM1 used a 32-bit internal structure, had a 26-bit address
lines (Max main memory size 64 MB).
• ARMv3 up to ARMv7 series, have a 32-bit address space.
• ARMv8-A architecture added support for a 64-bit address space and
64-bit arithmetic with its new 32-bit fixed-length instruction set.

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ARM PROCESSORS WIDELY USED

• ARM processors are desirable due to the following:
• Low costs
• Low power consumption
• Lower heat generation.

• ARM processors best fit for light, portable, battery-powered devices,

including smartphones, laptops and tablet computers, and
other embedded systems.
• With over 200 billion ARM chips produced, ARM processors also used
for desktops and servers, including the world's fastest supercomputer.

ANY QUESTIONS?

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