College of Engineering, Pune

Dept. of Electronics and Telecommunication Engineering

Course : RTL Simulation and Synthesis (M.Tech FY VLSI & ES)

Year : 2020-21

Theory Assignment No. 2 :

Topic : Basic Constructs in Verilog

MIS No :
Q1.

Q.2. Construct Johnson counter and Ring counter separate 2 verilog modules
using instantiation of DFFs.

Q3.
Q4.

Q5. Design a 8bit even-odd parity checker verilog code where it will have 8bit
input and two outputs named “evn” and “odd” will be at appropriate logic level
according to the parity of the input vector.

(Don’t write TB for any.)

Q6.

Q7.
Q8.

Q9.

Q10.