Basic Digital Electronics

2/13/2018 MADE EASY ONLINE TEST SERIES
BASIC : DIGITAL ELECTRONICS - REPORTS
OVERALL ANALYSIS COMPARISON REPORT SOLUTION REPORT
ALL(33) CORRECT(25) INCORRECT(5) SKIPPED(3)
Q. 1
The sum of product (SOP) form of logic expression is most suitable for designing logic circuit using only
FAQ Solution Video Have any Doubt ?
A
AND gates
B
NAND gates
Correct Option
Solution :
(b)
The SOP form can be implemented easily by using only NAND gates.
C
EX-OR gates
D
NOR gates
Your answer is Wrong
QUESTION ANALYTICS
Q. 2
The maximum positive and negative decimal numbers that can be represented in two’s compliment using n-bits
are
A
(2n –1 – 1) and (2n – 1 – 1)
B
https://onlinetestseriesmadeeasy.in/madeeasy/index.php?pageName=timeManagementReport&testid=298&t=a&testType=2 1/25
B
(2n –1 – 1) and –2n – 1
Your answer is Correct
Solution :
(b)
C
2n –1and –2n – 1
D
2n – 1 and –(2n – 1 – 1)
QUESTION ANALYTICS
Q. 3
Which of the following statements is not correct about a multiplexer (MUX) circuit?
A
A MUX is a combinational circuit.
B
A 2n input lines MUX has n-output lines.
Solution :
(b)
(a) A MUX is a combination circuit since it has no feedback element present.
(b) A MUX has only 1 output line.
(c) An AND and a NOT gate can form a complete set and can be used as a universal gate.
(d) A MUX can be used to construct any logic gate.
C
A MUX circuit can be designed using AND and NOT gates
D
A MUX circuit can be used as a universal logic gate.
QUESTION ANALYTICS
Q. 4
A function f (A, B, C) is to be implemented using an 3 × 8 decoder, where A is the MSB of the function and C is the
LSB of the function at the output. If the connections of the input to the decoder are as shown in the figure below,
then the function f (A, B, C ) can be expressed as
Correct Option
Solution :
(d)
QUESTION ANALYTICS
Q. 5
A programmable ROM consists of a decoder circuit followed by a series of OR circuit which can be fused by
programming, thus forming a 32 × 10 ROM circuit. The size of the decoder circuit is
A
5 × 32
Correct Option
Solution :
(a)
In a ROM circuit a decoder circuit is used to create all the possible minterms possible at the output and
these minters are then used to implement the required logic operation. Thus to create 32 minterms we
require a 5 × 32 decoder circuit.
B
32 × 32
C
32 × 10
D
10 × 32
QUESTION ANALYTICS
Q. 6
A counter is constructed whose output count is given by the sequence diagram shown in the figure below.
The minimum number of flip-flops required to construct such type of counter is

A
6
B
3
Solution :
(b)
C
2
D
5
QUESTION ANALYTICS
Q. 7
A ripple counter is made with three positive edge triggered flip-flops. If the output of previous lower significant bit
flip-flop is used as a triggering clock pulse of the next higher significant bit flip-flop, then the resultant counter is a
A
MOD 3 up counter
B
MOD 3 down counter
C
MOD 8 up counter
D
MOD 8 down counter
Solution :
(d)
QUESTION ANALYTICS
Q. 8
A weighted resistor type DAC is formed as shown in the figure below. The input voltage is equal to 0 V for logic
input ‘0’ and is equal to 5 V for logic input ‘1’. If the resolution of the DAC is equal to –0.1 V, then the value of RF is
equal to
FAQ Have any Doubt ?
A
2.6 kΩ
B
160 Ω
Solution :
(b)
C
10 kΩ
D
8Ω
QUESTION ANALYTICS
Q. 9
The advantage of using a flash-type ADC is that

A
the conversion time is the fastest.
Solution :
(a)
The flash-type ADC is the fastest ADC.
B
the circuit complexity is low.
C
the number of hardware components decreases with increase in number of bits.
D
none of these
QUESTION ANALYTICS
Q. 10
The logic family with the highest packing density is

A
CMOS family
B
N-MOS family
Correct Option
Solution :
(b)
N-MOS can be fabricated with the required area less then that of P-MOS and RTL logic family. Thus an N-
MOS logic family has the highest packing density.
C
P-MOS family
D
RTL family
QUESTION ANALYTICS
Q. 11
The r ’s compliment of an n-digit decimal number N in base r is defined for all values of N except for N = 0. If the
given number is (247)9, then its 9’s compliment will be equal to ( _____ )9.
642
Correct Option
Solution :
642
Your Answer is 752
QUESTION ANALYTICS
Q. 12
The minimum number of NOR gates required to implement an Ex-OR gate is _______.
5 5
Solution :
5
QUESTION ANALYTICS
Q. 13
A 32 : 1 MUX has to be designed using a 16 : 1 MUX. It was found that for this task we require “X ” number of 16 :
1 MUX and “Y ” number of two input OR gates, then the value of X + Y = __________.
3 3
Solution :
3
QUESTION ANALYTICS
Q. 14
The sequence diagram of a counter is shown in the figure below.
If the state values shown in the sequence diagram are the decimal equivalents of the corresponding states of the
counter, then the minimum number of flip-flops required to design this counter is _______.
3 3
Solution :
3
QUESTION ANALYTICS
Q. 15
A MOD-2 ripple counter is cascaded with a MOD-8 synchronous counter. The resulting circuit will form a counter
of MOD = ___________.
16
Correct Option
Solution :
16
Your Answer is 8
QUESTION ANALYTICS
Q. 16
For a certain 6-bit successive approximation type A-to-D converter, if the conversion time for an input of 1.5 V is
75 μsec, then the conversion time for an input of 2 V will be ________ μsec.
75 75
Solution :
75
QUESTION ANALYTICS
Q. 17
Consider an n-variable boolean function f (A, B, C,......). If the boolean function is represented as
then the alternative representation of the above function can be given
as
Solution :
(a)
C
C
1
D
0
QUESTION ANALYTICS
Q. 18
A three variable boolean function is defined as, f (A, B, C) = Σm(1, 2, 5, 6).If denotes the compliment of
the function f (A, B, C), then the simplified expression of can be given as
Solution :
(c)
QUESTION ANALYTICS
Q. 19
A 8 × 1 multiplexer is used to realize a four variable function, f (A, B, C, D) = Σm(0, 2, 4, 6, 7, 9, 14, 15). A is taken as
MSB and it is used as the input to the multiplexer. The select line inputs are given supply from the variables B, C,
D, where B is at the MSB and D is at the LSB of the select line, then the input to
the MUX from I0 to I7 respectively are
Solution :
(d)
QUESTION ANALYTICS
Q. 20
A logic function ‘f ’ is implemented by the circuit shown in the figure below. The circuit consists of one 2 ×4
decoder, two 2 × 1 multiplexers and a two input OR gate connected in cascade. Then the function ‘f ’ is equal to
Solution :
(b)
QUESTION ANALYTICS
Q. 21
A ROM chip has to be created with a capacity of 16K × 8. If the available ROM chip is of the size 2K × 4, then the
number of such chips required to construct a 16K × 8 ROM chip is
A
16
Solution :
(a)
To create a 16K × 8 ROM chip we require eight 2K × 4 chips in series and two such block of 8 chips to be
connected in parallel to make the output line of 8 bits.
Hence, a total number of 16 chips are required.
B
8
C
32
D
64
QUESTION ANALYTICS
Q. 22
A new flip-flop is designed with inputs A and B and output of the flip-flop being Q. The characteristic table of the
flip-flop is shown below.
If Q+ represents the next state output of the flip-flop, then the expression for Q+ will be
Solution :
(d)
QUESTION ANALYTICS
Q. 23
A MOD 6 ripple up-counter is to be designed using three flip-flops. The flip-flops can be reseted to their initial
condition by providing an active low external trigger to the CLR input. If the counter starts counting the sequence
from (Q2Q1Q0) = (000), then the combinational circuit that is shown in the figure below can be constructed by
using
A
an OR gate followed by a NOT gate
B
an EX-OR gate followed by a buffer gate
C
an AND gate followed by a NOT gate
Solution :
(c)
D
an EX-OR gate followed by a NOT gate
QUESTION ANALYTICS
Q. 24
Q. 24
A certain 6-bit DAC has full-scale output current of 2 mA and an error of ±0.5% on full scale. The range of possible
values of output current for a digital input “100000” is
A
1000 μA to 1026 μA
B
950 μA to 1015 μA
C
1016 μA to 1026 μA
D
1006 μA to 1026 μA
Solution :
(d)
QUESTION ANALYTICS
Q. 25
A dual-slope A/D converter has a resolution of 4 bits. If the input clock rate is 3.2 kHz, then the worst case
conversion rate at which the analog samples can be converted into their digital equivalent is
FAQ Have any Doubt ?
A
200 samples/sec
B
400 samples/sec
C
100 samples/sec
Correct Option
Solution :
(c)
D
50 samples/sec
QUESTION ANALYTICS
Q. 26
The circuit shown in the figure below is constructed using MOS circuits and PASS transistors. For S = 1, the output
F is equal to
C
A
Correct Option
Solution :
(d)
QUESTION ANALYTICS
Q. 27
The K-map of a boolean function is shown in the figure below. The number of essential prime implicants of this
function is __________.
4 4
Solution :
4
QUESTION ANALYTICS
Q. 28
A 1-bit full adder takes 10 ns to generate output carry bit and 20 ns to generate the output sum bit. If four such full
adders are cascaded to form a 4-bit parallel adder, then the maximum number of 4-bit additions per second that
can be performed by the parallel adder is _________ × 106.
20 20
Solution :
20
QUESTION ANALYTICS
Q. 29
Consider the circuit shown in the figure below:
If the three bit input to the circuit is (X2X1X0) = 101, then the decimal equivalent of the corresponding output of
the circuit (Y2Y1Y0) will be equal to _________.
3 3
Solution :
3
QUESTION ANALYTICS
Q. 30
A binary ripple counter is required to count from 0 to (16383)10. If the clock with a frequency of 8.192 MHz is
applied as input clock to the LSB flip-flop, then the frequency at the output of the MSB flip-flop will be equal to
Hz
________ Hz.
500
Your answer is Correct500
Solution :
500
QUESTION ANALYTICS
Q. 31
Consider a four bit D-to-A converter. If the output analog values corresponding to digital inputs “0000” and “0001”
are 0 V and 0.05 V respectively, then the output analog value corresponding to the digital input “1010” will be
equal to __________ V.
0.50 (0.49 - 0.51) 0.5

Solution :
0.50 (0.49 - 0.51)
QUESTION ANALYTICS
Q. 32
The state diagram of a digital synchronous circuit is shown in the figure below. The machine has four states
named as A, B, C and D. The input to this system is given by a bit stream of 0’s and 1’s. If the starting state of the
circuit is A, then the number of times the output goes to 1, for an input bit stream of 010011, is ________.
2 2
Solution :
2
QUESTION ANALYTICS
Q. 33
A four bit serial in parallel out shift register is constructed as shown in the figure below. The register is a right shift
register i.e. A → B, B → C, C → D and D is connected to the output. If the initial state (ABCD) of the shift register is
(1000), then the minimum number of clock cycles after which the state (ABCD) of the
shift register will be again equal to (1000) is __________ .
4 4
Solution :
Solution :
4
QUESTION ANALYTICS

Basic Digital Electronics

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2/13/2018 MADE EASY ONLINE TEST SERIES

BASIC : DIGITAL ELECTRONICS - REPORTS

OVERALL ANALYSIS COMPARISON REPORT SOLUTION REPORT

ALL(33) CORRECT(25) INCORRECT(5) SKIPPED(3)

FAQ Solution Video Have any Doubt ?

Your answer is Wrong

The minimum number of flip-flops required to construct such type of counter is

FAQ Have any Doubt ?

The advantage of using a flash-type ADC is that

The logic family with the highest packing density is

Your Answer is 752

The sequence diagram of a counter is shown in the ﬁgure below.

Your answer is Correct

Your answer is Correct

FAQ Solution Video Have any Doubt ?

Your answer is Correct

FAQ Solution Video Have any Doubt ?

Your answer is Correct

Your answer is Correct

FAQ Solution Video Have any Doubt ?

FAQ Solution Video Have any Doubt ?

FAQ Solution Video Have any Doubt ?

Consider the circuit shown in the ﬁgure below:

0.50 (0.49 - 0.51) 0.5

FAQ Solution Video Have any Doubt ?

FAQ Solution Video Have any Doubt ?

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