DIGITAL CIRCUITS-1 - REPORTS

OVERALL ANALYSIS COMPARISON REPORT

SOLUTION REPORT

ALL(16) CORRECT(3) INCORRECT(8) SKIPPED(5)

Q. 1

The circuit shown below is used to implement the function

The values of P and Q are

FAQ Have any Doubt ?

B Your answer is Wrong

D Correct Option

Solution :
(d)

QUESTION ANALYTICS

Q. 2

The irredundant minimised logic expression corresponding to the K-map shown

below is
 FAQ Have any Doubt ?

B Your answer is Correct

Solution :
(b)

QUESTION ANALYTICS

Q. 3

The circuit shown below implements a two input NOR gate by using two 2 × 1
multiplexers. The values of A, B, and C are respectively.

FAQ Have any Doubt ?

Correct Option
 A Correct Option

Solution :
(a)

B Your answer is Wrong

QUESTION ANALYTICS

Q. 4

The logical expression for the output of the CMOS circuit shown below can be
represented as

FAQ Have any Doubt ?

A Y = Σm(1, 2, 4, 7)
 B Y = Σm(2, 3, 4, 5, 6, 7)

C Correct Option

Solution :
(c)

D Your answer is Wrong

QUESTION ANALYTICS

Q. 5

If (211)x = (152)8, then the value of x is __________.

FAQ Have any Doubt ?

7 Correct Option

Solution :
7

Your Answer is 9

QUESTION ANALYTICS

Q. 6

If X and Y logic inputs are available and their respective complements

are not available, then the minimum number of two input NAND
gates required to implement X ⊕ Y is __________.
g __________
FAQ Have any Doubt ?

4 Your answer is Correct4

Solution :
4

QUESTION ANALYTICS

Q. 7

The minimum number of 2 input NAND gates required to implement the

Boolean function is ____________.
FAQ Have any Doubt ?

4 Your answer is Correct4

Solution :
4

QUESTION ANALYTICS

Q. 8

Consider the combinational logic circuit shown below.

The output Q can be expressed as
FAQ Have any Doubt ?

A Σm(0, 1, 2, 3, 4, 5, 6)

B Correct Option

Solution :
(b)

C Your answer is Wrong

D Σm(1, 2, 3, 4, 5, 6)

QUESTION ANALYTICS

Q. 9

A half adder is implement with XOR and AND gates. A full adder is
implemented with two half adders and one OR gate. The propagation delay of
an XOR gate is twice that of an AND/OR gate. The propagation delay of an
AND/OR gate is 1.2 μsec. A 4-bit ripple carry binary adder is implemented by
using full adders. The total propagation delay of this 4-bit binary adder is
FAQ Have any Doubt ?

A 19 μsec

B 19.2 μsec Correct Option

Solution :
(b)
 C 38 μsec Your answer is Wrong

D 38.4 μsec

QUESTION ANALYTICS

Q. 10

Which of the following circuits function as a J-K flip-flop?

FAQ Have any Doubt ?

Correct Option

Solution :
(a)

B
 C

Your answer is Wrong

QUESTION ANALYTICS

Q. 11

A 2-bit magnitude comparator is designed using two 1-bit magnitude

comparators as shown below:
Determine the boolean function for the combinational circuit G?
FAQ Have any Doubt ?

D Correct Option

Solution :
(d)

QUESTION ANALYTICS

Q. 12

If the logical expressions of the outputs in the circuits shown in

Figures A and B are same, then select the correct combination of signals to be
connected to the inputs of multiplexer (i.e. I0, I1, I2, I3) using the codes given
below the Figures.
 FAQ Have any Doubt ?

A a Your answer is Wrong

B b

C c Correct Option

Solution :
(c)

D d

QUESTION ANALYTICS

Q. 13

An n -bit carry look ahead adder is designed using only Ex-OR, AND, OR gates.
The propagation delay of each Ex-OR gate is 20 ns and that of each AND, OR
gates is t0 ns. If the total propagation delay of the adder circuit is 60 ns, then the
value of t0 will be ____________ ns.
(given that t0 ≤ 20 ns)
FAQ Have any Doubt ?

10 Correct Option

Solution :
10
 QUESTION ANALYTICS

Q. 14

In the multiplexer based circuit shown below, the average propagation delay of
each multiplexer is 25 ns. The frequency of the output signal V0is ___________
MHz.

FAQ Have any Doubt ?

4 Correct Option

Solution :
4

QUESTION ANALYTICS

Q. 15

The number of 4 line to 16 line decoders with enable inputs required to make an
8 line to 256 line decoder is __________.
FAQ Have any Doubt ?

17 Correct Option

Solution :
17

QUESTION ANALYTICS

Q. 16

Consider the 4 : 1 MUX based circuit as shown in the figure. A and B are two
periodic signals with duty cycles 25% and 50% respectively as given in the
figure. If +5 V and 0 V are used to represent logic-1 and logic-0 respectively,
then the average power dissipated by the resistor RL will be _________ mW.

FAQ Have any Doubt ?

6.25 (6.20 - 6.30) Correct Option

Solution :
6.25 (6.20 - 6.30)
QUESTION ANALYTICS