VALLIAMMAI ENGINEERING COLLEGE

SRM Nagar, Kattankulathur – 603 203

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING

QUESTION BANK

II SEMESTER M.E COMMUNICATION SYSTEMS

CU5073 – VLSI FOR WIRELESS COMMUNICAITON

Regulation – 2017

Academic Year 2018 – 19

Prepared by

Mr.C.SARAVANAKUMAR, Assistant Professor/ECE

 VALLIAMMAI ENGINEERING COLLEGE
SRM Nagar, Kattankulathur – 603 203.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

QUESTION BANK
SUBJECT : CU5073 VLSI FOR WIRELESS COMMUNICATION
SEM / YEAR: II / I

UNIT I COMMUNICATION CONCEPTS

Introduction – Overview of Wireless systems – Standards – Access Methods – Modulation schemes – Classical
channel – Wireless channel description – Path loss – Multipath fading – Standard Translation.
PART A

BT
Q.No Questions Competence
Level
1. Draw the block diagram of typical communication system. BTL 2 Understanding
2. What is the need of Communication Engineering for IC engineers? BTL 2 Understanding
3. Discuss about portable radio? BTL 1 Remembering
4. Point out the reasons for sudden change in signal quality of a mobile phone BTL 1 Remembering
while travelling.
5. List the different modulation schemes. BTL 1 Remembering
6. Give the diagram of QPSK coherent modulator. BTL 2 Understanding
7. Write the expressions for possible correlator outputs in Binary PSK? BTL 1 Remembering
8. With a path diagram discuss about the global reflector? BTL 4 Analyzing
9. Define envelope fading? BTL 2 Understanding
10. Show the Characteristics of path loss phenomenon. BTL 1 Remembering
11. How would you describe Friis equation? BTL 4 Analyzing
12. Summarize the DECT requirements. BTL 5 Evaluating
13. Simplify the expression for Rayleigh Distribution. BTL 4 Analyzing
14. Determine the SNR for DECT with given specifications: Pe = 10-3, δ=0.68. BTL 5 Evaluating
15. Compare frequency and space diversity approach. BTL 1 Remembering
16. A car drives with v = 120 km/h on the highway. The driver uses a DECT BTL 3 Applying
mobile phone. What is the maximum Doppler frequency shift?.
17. Demonstrate the frequency selective fading BTL 3 Applying
18. Elaborate the NLOS path loss. BTL 6 Creating
19. Discuss the expression for minimum separation of channels. BTL 6 Creating
20. Illustrate the impact of Doppler effect. BTL 3 Applying
PART –B
1. Describe the standards of DECT requirements. (13) BTL 1 Remembering
2. Demonstrate the Binary Frequency shift keying with necessary diagrams. BTL 2 Understanding
(13)
3. Develop the points to explain about the Binary Phase shift keying. (13) BTL 3 Applying
4. Summarize the general philosophy of Quadrature Phase shift keying with BTL 2 Understanding
relevant diagrams. (13)
5. Illustrate the following with neat diagrams. BTL 2 Understanding
 (a) Offset quadrature Phase shift keying (7)
(b) Minimum Shift keying (6)
6. Show the probability distribution function with respect to additive white BTL 1 Remembering
Gaussian Noise. (13)
7. Explain the concepts of Finite channel Bandwidth with necessary BTL 4 Analyzing
expressions? (13)
8. Write in detail the expressions for Friis Equation? (13) BTL 1 Remembering

9. Discuss the Global Reflection and Local Reflection in Path Environment. BTL 6 Creating
(13)
10. Determine the impact of the doppler effect in multipath fading. (13) BTL 5 Evaluating

11. Analyze the operation of Time Varying Channel Model with expressions. BTL 4 Analyzing
(13)
12. Solve for Pr min. Assume d0 = 3m (for minimum cell radius), n = 3, d = BTL 3 Applying
400m(for maximum cell radius). PT = 24dBm. (13)
13. Write in detail about BTL 4 Analyzing
(a) Frequency diversity approach. (7)
(b) Space diversity approach. (6)
14. Summarize the standard translation for DECT. (13) BTL 1 Remembering
PART –C
1. Describe any 3 the different modulation schemes with necessary diagrams? BTL 5 Evaluating
(15)
2. With the help of neat diagram, describe about the classical channel? (15) BTL 6 Creating
3. Compare Flat/Frequency selective and Slow/Fast Fading. (15) BTL 5 Evaluating
4. Formulate the multipath fading with illustrations. (15) BTL 6 Creating

UNIT II RECEIVER ARCHITECTURE & LOW NOISE AMPLIFIERS

Receiver front end – Filter design – Non-idealities – Design parameters – Noise figure & Input intercept point.
LNA Introduction – Wideband LNA design – Narrow band LNA design: Impedance matching & Core amplifier.
PART A
BT
Q.No Questions Competence
Level
1. Summarize the reasons for interference in channel. BTL 2 Understanding
2. Define SNR ? BTL 2 Understanding
3. Write the general design philosophy of receiver architecture? BTL 1 Remembering
4. Estimate the inter modulation. BTL 2 Understanding
5. Point out the specifications of LNA for DECT. BTL 1 Remembering
6. List the issues which should be consider while designing wideband BTL 4 Analyzing
amplifier.
7. Point out the noise sources. BTL 2 Understanding
8. Give the generalized LNA topology. BTL 1 Remembering
9. Examine noise figure. BTL 4 Analyzing
10. Summarize the distortion due to non linearites. BTL 5 Evaluating
11. Analyze the expression for power dissipation in Narrow band LNA. BTL 4 Analyzing
12. Write the expression for transducer gate power GT? BTL 1 Remembering
13. Compare Narrow band and wide band LNA. BTL 1 Remembering
14. Identify the objectives of Matching networks. BTL 3 Applying
15. Demonstrate the analogy and relationship between lumped parameters and BTL 3 Applying
S parameters.
16. Elaborate on Q factor. BTL 6 Creating
17. Determine the importance of automatic gain control amplifier. BTL 5 Evaluating
18. Illustrate amplifier and power amplifier. BTL 3 Applying
19. Name the various applications of LNA circuit. BTL 1 Remembering
20. Discuss the reverse isolation. BTL 6 Creating
PART –B
1. Describe the design of image rejection filter with necessary expressions? BTL 1 Remembering
(13)
2. Demonstrate the various Non lineraties that arise in design of receiver front BTL 2 Understanding
end. (13)
3. Develop the design of noisy cascaded design. (13) BTL 3 Applying
4. Derive the expression for Noise Figure and IIP3 of receiver front end? (13) BTL 2 Understanding
5. Analyze the operation of Matching networks with respect to LNA. (13) BTL 4 Analyzing
6. Examine the design of Wideband LNA with a neat diagram and necessary BTL 4 Analyzing
equations. (13)
7. Illustrate the Wideband LNA design by considering DC bias, Gain and BTL 2 Understanding
frequency response and Noise figure. (13)
8. Show how would you match the Imaginary & real part in Narrowband LNA BTL 1 Remembering
impedance matching. (13)
9. Explain the following in Narrowband LNA impedance matching. BTL 4 Analyzing
(a) Interpretation of power matching. (7)
(b) Similarity between “Q” & “n”. (6)
10. Write in detail the expressions of noise figure for Narrowband LNA Core BTL 1 Remembering
amplifier? (13)
11. Discuss the following BTL 6 Creating
(a) Trade-off between Noise figure and power. (7)
(b) Noise contribution from other sources. (6)
12. Determine the Gain of Narrowband LNA Core amplifier with necessary BTL 5 Evaluating
illustrations. (13)
13. Solve the expression of power dissipation for Narrowband LNA core BTL 3 Applying
amplifier. (13)
14. Sketch the diagram for Narrowband LNA core amplifier and explain in BTL 1 Remembering
detail. (13)
PART –C
1. Formulate the expression for third order intercept point in receiver front BTL 5 Evaluating
end.? (15)
2. With the help of neat diagram, describe the filter design techniques (15) BTL 6 Creating
3. Evaluate a narrow band LNA with the given specifications: BTL 5 Evaluating
f0 = 1.9GHz
Input matching:S11<-10dB
Noise factor: <3dB
Voltage Gain: 20dB
Power at 3.3V: 40mW (15)
 4. Examine the expression of power dissipation for Narrowband design? (15) BTL 6 Creating

UNIT III MIXERS

Balancing Mixer - Qualitative Description of the Gilbert Mixer - Conversion Gain – Distortion – Noise - A
Complete Active Mixer. Switching Mixer – Distortion, Conversion Gain & Noise in Unbalanced Switching
Mixer - A Practical Unbalanced Switching Mixer. Sampling Mixer - Conversion Gain, Distortion, Intrinsic &
Extrinsic Noise in Single Ended Sampling Mixer
PART A

BT
Q.No Questions Competence
Level
1. Describe the mixer modeled as variable gain amplifier. BTL 4 Analyzing
2. Define unbalanced mixer. BTL 1 Remembering
3. What is quad mixer? BTL 1 Remembering
4. Why double balanced mixer is commonly used? Justify? BTL 1 Remembering
5. List the two levels of subscript and superscript distinctions. BTL 1 Remembering
6. Estimate the conversion gain. BTL 5 Evaluating
7. Show the distortion in Gilbert mixer. BTL 1 Remembering
8. Explain about NLTI. BTL 2 Understanding
9. Conclude the properties of Bilinear system. BTL 5 Evaluating
10. Develop the circuit representation1 of an NLTI system. BTL 6 Creating
11. Examine G1 from the first order term id. BTL 4 Analyzing
12. Identify the noise in mixers. BTL 3 Applying
13. Discuss about the mixer topology. BTL 3 Applying
14. Write about mixer linearization? BTL 1 Remembering
15. Outline the block diagram of an unbalanced mixer for noise calculation. BTL 2 Understanding
16. Choose the two scenarios which is used in analysis of noise in unbalanced BTL 3 Applying
mixer.
17. Compare linearity and nonlinearity. BTL 2 Understanding
18. Distinguish between low frequency and high frequency mixers. BTL 4 Analyzing
19. How intrinsic noise and extrinsic noise could be related in mixers? BTL 2 Understanding
20. Compile the assumptions which will consider during intermodulation BTL 6 Creating
distortion switching mixer?
PART B
1. Define the following BTL 1 Remembering
(a) Mixer (2)
(b) Unbalanced mixer (4)
(c) Single balanced mixer (4)
(d) Double balanced mixer (3)
2. Explain the qualitative description of the Gilbert mixer. (13) BTL 2 Understanding
3. Point out the detailed analysis of Gilbert mixer for the following BTL 4 Analyzing
(a) Distortion. (7)
(b) Low frequency case. (6)
4. Illustrate the Gilbert Mixer distortion in high frequency case. (13) BTL 2 Understanding
5. Describe the following factors of Noise in balanced mixer BTL 1 Remembering
(a) Vlo not switching case. (7)
(b) Vlo switching case. (6)
6. Develop the theory of linear periodic LPTV system. (13) BTL 3 Applying
7. Calculate the noise in unbalanced mixer in the scenario of Vlo not switching BTL 3 Applying
case and Vlo switching case and calculate the following.
(a) Sn2 (2)
(b) HLTI (5)
(c) NF (6)
8. Conclude a detailed note on special Vlo switching case mixers. (13) BTL 5 Evaluating
9. Write the following factors of switching mixer. BTL 1 Remembering
(a) Unbalanced switched mixer. (7)
(b) Single and double balanced switching mixer. (6)
10. List the non idealities of switching mixers and their impact. (13) BTL 4 Analyzing
11. (a) List the assumptions made on model for distortion in unbalanced
switching mixer. (4) BTL 1 Remembering
(b) Show the distortion in unbalanced switching mixer in the condition
of low frequency case. (9)
12. Measure the conversion gain in unbalanced switching mixer with diagrams. BTL 6 Creating
(13)
13. Derive the Intrinsic noise in single ended sampling mixer. (13) BTL 4 Analyzing
14. Compare Sample & hold circuit and Sampling mixer with necessary BTL 2 Understanding
diagrams. (13)
PART C
1. Estimate the equivalent input-referred voltage and current noise sources at BTL 6 Creating
the input with feedback Vi 2 * Ii 2 in terms of the equivalent input referred
voltage and current noise sources without feedback Vi Ii. (15)
2. Compare the different LNA architectures according to their gain, NF and BTL 5 Evaluating
matching performances. (15)
3. With the help of Gilbert / Quad mixer assume that M-M6 all have a W/L of BTL 6 Creating
50µm/0.6µm and make Vgs1 – Vt = 0.387V, assuming that kʹ = 7.5uA/V2.
Then k=6250uA/V2 and gm1=k(VGS-Vt) = 2.4mΩ-1. Design for a
conversion gain of 10dB. Assume that a Gilbert mixer operates under the
following conditions. VGS1 – Vt = 0.387 V Arf = Ainterference = 0.316 V or 0dB.
Assume that the LO is not switching. Find the mixers distortion behavior
HD3, IM3 and IIP3.The mixer is assigned as IIP3 of -10dBm. Design this
mixer with some safety margin. Consider the specification arbitrarily. (15)

4. Evaluate Gc.IM3 and NF of both a 100MHZ IF single-ended sampling mixer BTL 5 Evaluating
and a 1.9GHz RF single-ended sampling mixer in a DECT application for the
following architecture shown in figure. (15)
 UNIT IV FREQUENCY SYNTHESIZERS
PLL – Phase detector – Dividers – Voltage Controlled Oscillators – LC oscillators – Ring Oscillators – Phase
noise – Loop filters & design approaches – A complete synthesizer design example (DECT) – Frequency
synthesizer with fractional divider.
PART A

BT
Q.No Questions Competence
Level
1. Draw the block diagram of a PLL. BTL 1 Remembering
2. Mention the purpose of phase detector. BTL 2 Understanding
3. List the types of phase detector. BTL 1 Remembering
4. Outline the state diagram of phase frequency detector. BTL 2 Understanding
5. Show the types of VCO. BTL 1 Remembering
6. Analyze the key characteristics of charge pump. BTL 4 Analyzing
7. Name the two approaches to analyze resonator based oscillator. BTL 1 Remembering
8. Define PLL based frequency synthesizer. BTL 1 Remembering
9. Categorize the different types of oscillators. BTL 4 Analyzing
10. Explain the ring oscillator? BTL 4 Analyzing
11. List the uses of frequency divider. BTL 5 Evaluating
12. Evaluate the phase noise. BTL 5 Evaluating
13. Analyze the loop filter. BTL 3 Applying
14. What is Figure of Merit.? BTL 1 Remembering
15. Elaborate the applications of digital phase detector. BTL 6 Creating
16. Develop the structure for multi feedback ring oscillator. BTL 6 Creating
17. Write the role of analog phase detector circuit. BTL 2 Understanding
18. Construct the LC oscillator model. BTL 3 Applying
19. Generate a report on the participation of frequency divider in frequency BTL 2 Understanding
synthesizer circuit.
20. Point out the applications of DECT. BTL 3 Applying
PART B
1. Write the design and function of PLL based frequency synthesizer. (13) BTL 1 Remembering
2. Describe the Phase frequency detector with suitable diagrams. (13) BTL 2 Understanding
3. Examine the XOR phase detector circuit with necessary illustrations? (13) BTL 1 Remembering
4. Describe the different types of Dividers used in frequency synthesizer (13) BTL 2 Understanding
5. Evaluate a complete divider for DECT application. (13) BTL 5 Evaluating
6. Explain the positive feedback theory of VCO with the required expressions. BTL 1 Remembering
(13)
7. Derive the solution for voltage gain of LC oscillator with a neat diagram? BTL 3 Applying
(13)
8. Demonstrate the following oscillators with a simplified diagram BTL 3 Applying
(a) Common Gate Oscillator (7)
(b) Colpitts Oscillator (6)
9. Analyze the operation of a Ring oscillator with a neat diagram. (13) BTL 4 Analyzing
10. Describe the Delay cells in Ring oscillator with waveforms. (13) BTL 6 Creating
11. What is phase noise and write about its interpretation with respect to BTL 4 Analyzing
oscillator design? (13)
12. Sketch the circuit diagram and its response for a BTL 1 Remembering
(a) First Order filter. (7)
(b) Second Order filter. (6)
 13. Point out the detailed design of Phase Noise based approach for Loop filter. BTL 4 Analyzing
(13)
14. Illustrate the procedure for designing a Loop filter using Spur based BTL 2 Understanding
approach with example. (13)
PART C
1. Perform Tuning of Ring Oscillator and derive Kvco (15) BTL 6 Creating
2. Derive the small signal model of LC oscillator with supporting diagrams(15) BTL 5 Evaluating
3. Construct the architecture of complete synthesizer with DECT as example. BTL 6 Creating
(15)
4. Describe the loop filter design by any one approach. (15) BTL 5 Evaluating

UNIT V TRANSMITTER ARCHITECTURES & POWER AMPLIFIERS

Transmitter back end design – Quadrature LO generator – Power amplifier design
PART A

Q.No Questions BT Level Competence

1. For the indirect conversion transmitter architecture, explain its BTL 1 Remembering
performance advantages over the direct conversion transmitter.
2. Give the architecture of the Indirect conversion transmitter. BTL 2 Understanding
3. Describe Harmonic rejection transmitter. BTL 1 Remembering
4. Analyze the quadrature LO generator. BTL 4 Analyzing
5. Define power amplifier. BTL 1 Remembering
6. Narrate about single ended RC circuits response. BTL 2 Understanding
7. Evaluate the relative phase of 90◦ for single ended LC. BTL 5 Evaluating
8. Explain LMS algorithm? BTL 4 Analyzing
9. Identify the expression for LOq for RC with differential stages BTL 1 Remembering
10. Summarize the functions of quadrature generator. BTL 2 Understanding
11. Evaluate the advantage of digital based generator. BTL 5 Evaluating
12. Draw the PA output power level for GSM. BTL 3 Applying
13. Tabulate the PA design issues. BTL 1 Remembering
14. Examine the matching network of Class A – PA. BTL 3 Applying
15. Determine the maximum power delivered to the load of a Class A BTL 3 Applying
amplifier.
16. Show the diagrammatic representation of Class E amplifier. BTL 2 Understanding
17. Analyze the Circuit details of Class C amplifier. BTL 6 Creating
18. State expression for PA efficiency. BTL 1 Remembering
19. What are some of the potential drawbacks of using passive methods BTL 6 Creating
such as RC filter, polyphase filter as quadrature LO generator?
20. For the differential RC quadrature LO generator, derive the relation BTL 4 Analyzing
between R1, ωLO, C and R2 if LOI and LOQ have equal amplitudes.
PART B

1. Evaluate different RF transmitter architecture will illustrative BTL 5 Evaluating

figures. (13)
2. With a neat diagram, explain the Frequency translation architecture. BTL 1 Remembering
(13)
3. Describe a single ended RC quadrature LO generator with suitable BTL 1 Remembering
diagram. (13)
4. Design a single-ended RC quadrature LO generator such that it gives BTL 3 Applying
a 90◦ at 1GHz. (13)
5. Describe a single ended LC quadrature LO generator with suitable BTL 2 Understanding
diagram. (13)
6. Design a single-ended LC quadrature LO generator such that it gives BTL 3 Applying
a 90◦ at 1GHz. (13)
7. Write in detail about the Poly phase I/Q generator with a neat BTL 2 Understanding
diagram. (13)
8. Narrate about the IIP3 Specs in power amplifier design with the BTL 1 Remembering
expressions. (13)
9. What are the power amplifier design issues and explain? (13) BTL 4 Analyzing
10. Discuss about the Class A amplifier with its circuit. (13) BTL 6 Creating
11. Analyze the various parameters considered for the design of Class C BTL 4 Analyzing
Amplifiers. (13)
12. Summarize the points that takes the choice of Class A Vs Class AB/C BTL 2 Understanding
amplifiers. (13)
13. Examine the timing diagram of Class E amplifier along with its BTL 4 Analyzing
circuit diagram. (13)
14. Design a class A RF single stage PA. Assume the transistor can BTL 1 Remembering
deliver 2W output (challenging for CMOS) with the following
parameters:
Vdd = 4.8V; IDO = 1A; Ls = 0:1nH; Rs = 0.2Ω; Vds sat = 0.6V (13)
PART C
1. What are some of the loss mechanisms of a polyphase filter based BTL 5 Evaluating
quadrature LO generator? A quadrature LO generator is shown in
Figure below that tries to combat this. How does it minimize some
of the loss? (15)

2. Analyze the function of transmitter back end design with neat BTL 6 Creating
diagrams. (15)
3. Discuss the 3 stage class A power amplifier with necessary diagram. BTL 5 Evaluating
(15)
4. Describe the RC differential stage LO with appropriate diagrams. BTL 6 Creating
(15)