*X86963*

Reg. No. :

Question Paper Code : X86963

M.E./M.Tech. Degree Examinations, April/may 2021

Second Semester
VLSI Design
vl5201 – testing of vlsi circuits
(Regulations 2017)

Time : Three Hours Maximum : 100 Marks

Answer all questions

Part – a (10×2=20 Marks)

1. Mention the importance of testing for the semiconductor manufacturing industry.

2. Give the need for delay models which are used in simulation.

3. Difference between structural and functional test in combinational circuits.

4. What are cyclic circuits ? Give an example.

5. Define predictability and list the factors affecting it.

6. How system level DFT is carried out with system buses and scan paths ?

7. Give the significance of signature in BIST algorithm.

8. List the algorithms used for testing the memory elements in VLSI.

9. Mention the importance of fault library and its role in fault diagnosis.

10. What are self checking design in VLSI circuits ?

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Part – B (5×13=65 Marks)

11. a) Illustrate the different types of faults that can occur in the digital circuits with
suitable example.

(OR)
b) With the help of flowchart describe the process of Event driven simulation and
the different delay models associated with it.

12. a) With the help of a suitable example, illustrate the side benefit of redundancy
identification of combinational ATPG algorithm.

(OR)

b) Explain in detail about the role of genetic algorithm in the simulation based
test generation for sequential circuits.

13. a) Discuss in detail about the design for testability techniques associated with
the ad hoc design.

(OR)

b) Compare full serial integrated scan and isolated serial scan techniques used
in scan based design for testability.

14. a) Explain the different test pattern generation techniques used for the Built-in-
self-test algorithm.

(OR)

b) Explain the different techniques used for testing memory in VLSI circuits.

15. a) Explain the guide probe testing technique used for the logic level diagnosis of
digital circuits.

(OR)

b) Describe the application of error detection and error correction codes in self
checking design of VLSI circuits.
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Part – C (1×15=15 Marks)

16. a) Consider the LFSR circuit shown below :

i) Generate all the possible states of the given circuit.
ii) Comment on the reason for including the NOR and OR gate in the circuit.

(OR)

b) Consider the combinational circuit shown in the figure with primary inputs
A, B and C. Generate and compare the test vectors obtained by applying FAN
ATPG and PODEM ATPG algorithm for the fault e S-A-1.

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