ET/PC/B/T/316/2021

JADAVPUR UNIVERSITY
B.E. Electronics & Telecommunication Engineering

3rd Year, 1st Semester Exam. - 2021

Analog CMOS Design & Technology Full Marks : 100

Instructions :
1. Write Part A and Part B of the answer script in sequence. Start Part B in a new sheet.
2. Do not write answers to various parts of a particular question in Part B at non-
contiguous locations of your answer-script.
3. Do not write on the front back cover of your answer booklet (Cover sheet).
4. Keep sufficient margins on all sides of your answer sheet.
5. Write your name and Roll No. (last three digits) at the bottom right corner of each
page.
6. Write the page number at the top right corner of each page.

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Part A
Answer any 15 questions. Each question carries 2 marks. (15 x 2)
1. For the arrangement in Fig. 1, plot the on-resistance of M1 as a function of VG. Assume that
μnCox = 50 μA/V2, W/L = 10, and VTH = 0.3 V. Note that the drain terminal is open.

Fig. 1

2. On a VDS - VGS plane, show the regions of operation of an NMOS transistor.

3. For the arrangement shown in Fig. 2, plot the transconductance as a function of VDS.

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 Fig. 2

4. In Fig. 3, plot the drain current if VX varies from - ∞ to 0. Assume VT H0 = 0.3 V, γ = 0.4 V1/2, and
2φF = 0.7 V.

Fig. 3
5. What are the different aspects of the performance of an amplifier that an analog circuit
designer must optimize ?
6. Sketch the transconductance of M1 in Fig. 4 as a function of the input voltage.

Fig. 4

7. Which properties of a “Source Follower” make it useful as a voltage buffer ?

8. What is cascode topology ? Draw the basic configuration of a cascode stage.
9. Why should one avoid long current mirror chains ?
10. How do we generate a current IREF / 2 from IREF ?
11. In reality, as opposed to an idealized response, a fraction of the input CM (common mode)
variation appears at the output of a differential amplifier. This is because of what reasons ?
12. What is CMRR ?
13. What are the benefits of negative feedback ?
14. Distinguish between open loop gain, closed loop gain, and loop gain of a simple feedback
system.
15. What do you mean by “sheet resistance” of a layer in the context of semiconductor processing
and characterization ?
16. Distinguish between positive and negative photoresist used in photolithography.
17. What are the different functions of the SiO2 layer during device fabrication ?
18. What is “channeling” that may happen during the “ion implantation” process ?
19. What is the difference between pure silicon and polysilicon ?
20. How many different types of masks are basically used during CMOS fabrication ? Name them.

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Part B
Answer all questions. Each question carries 10 marks. Marks for each part question
is indicated next to the part question. (7 x 10)

1. i) Discuss in details, including mathematical representation, any one of the second order effects
of a MOSFET. (5)
ii) For W = 50 μm, L = 0.5 μm, and |ID| = 0.5 mA, calculate the transconductance and output
impedance of both NMOS and PMOS devices. Also find the “intrinsic gain”, defined as gmro. (5)

Use the following data :

For NMOS,

Transconductance parameter, KP = μnCox = 50 x 10-6 A/V2

Threshold voltage, VTH = 0.7 V

Source / Drain lateral diffusion, LD = 0.08 μm

Channel length modulation coefficient, λ = 0.1 V-1

For PMOS,

Corresponding values of KP (μpCox), VTH, LD and λ are 25 x 10-6 A/V2, -0.8 V, 0.09 μm, and 0.2 V-1
respectively.

2. i) Derive the small-signal voltage gain of a CS stage with source degeneration. Neglect channel
length modulation and body effect. (3)
ii) For the following circuit (Fig. 5) of an NMOS cascode amplifier with PMOS cascode load,
calculate the voltage gain. (3)

Fig. 5

iii) For the circuit of Fig. 6, calculate the small-signal voltage gain if (W/L)1 = 50/0.5, (W/L)2 = 10/0.5,
and ID1 = ID2 = 0.5 mA. What is the gain if M2 is implemented as a diode-connected PMOS device
(Fig. 7). Neglect channel length modulation in both cases. [η = 0.25, μn = 350 cm2/Vs, μp = 100
cm2/Vs] (4)

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 Fig. 6 Fig. 7

3. i) What are the advantage(s) and disadvantage(s) of differential operation over single-ended
signaling ? (4)

ii) The circuit of Fig. 8 uses a resistor rather than a current source to define a tail current of 1
mA. Assume that
(W/L)1,2 = 25/0.5, μnCox = 50 μA/V2, VT H = 0.6 V, λ = γ = 0, and VDD = 3 V. (6)

(a) What is the required input CM voltage for which RSS sustains 0.5 V?
(b) Calculate RD for a differential gain of 5.
(c) What happens at the output if the input CM level is 50 mV higher than the value calculated
in (a)?

Fig. 8

OR
Draw the circuit and explain the operation of Gilbert cell. Explain how it can act as an analog
voltage multiplier. (6)

4. i) Calculate the small-signal voltage gain of the circuit shown in Fig. 9. (3)

Fig. 9

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 ii) In Fig. 10, assuming all the transistors to be identical, sketch IX and VB as VX drops from a large
positive value. (4)

Fig. 10

iii)Explain the operation of a “differential pair with active load.” (3)

5. i) Calculate the transimpedance, input impedance and output impedance of a Transimpedance

Amplifier (TIA) employing feedback. (6)
ii) Name and explain one important application of a TIA. (4)

OR
Discuss the logic of sense and return mechanism in a feedback circuit. (4)

6. i) Explain how a voltage amplifier boosts the transconductance of the MOS device in the “gain
boosting” operational amplifier topology. What will be the output resistance of the degenerated
stage ? (3 + 3)

ii) Explain “slewing” in a realistic operational amplifier circuit. What is “slew rate” ? (2 + 2)

7. i) Explain the importance of “channel stop implant” with the help of a diagram. (4)

OR
What is the significance of “etching” in semiconductor device fabrication ? What are the three
different types of etching techniques ? Write in brief about each. (4)

ii) Write in details (with the aid of diagrams) about the fabrication of a CMOS device starting from
the step after channel stop implant. (6)

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